| 1 | /* |
| 2 | * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * File: mcf548x_dspi.h |
| 5 | * Purpose: Register and bit definitions for the MCF548X |
| 6 | * |
| 7 | * Notes: |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | #ifndef _M5485DSPI_H_ |
| 12 | #define _M5485DSPI_H_ |
| 13 | |
| 14 | /* |
| 15 | * |
| 16 | * DMA Serial Peripheral Interface (DSPI) |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | /* Register read/write macros */ |
| 21 | #define MCF_DSPI_DMCR MCF_REG32(0x008A00) |
| 22 | #define MCF_DSPI_DTCR MCF_REG32(0x008A08) |
| 23 | #define MCF_DSPI_DCTAR0 MCF_REG32(0x008A0C) |
| 24 | #define MCF_DSPI_DCTAR1 MCF_REG32(0x008A10) |
| 25 | #define MCF_DSPI_DCTAR2 MCF_REG32(0x008A14) |
| 26 | #define MCF_DSPI_DCTAR3 MCF_REG32(0x008A18) |
| 27 | #define MCF_DSPI_DCTAR4 MCF_REG32(0x008A1C) |
| 28 | #define MCF_DSPI_DCTAR5 MCF_REG32(0x008A20) |
| 29 | #define MCF_DSPI_DCTAR6 MCF_REG32(0x008A24) |
| 30 | #define MCF_DSPI_DCTAR7 MCF_REG32(0x008A28) |
| 31 | #define MCF_DSPI_DCTARn(x) MCF_REG32(0x008A0C+(x*4)) |
| 32 | #define MCF_DSPI_DSR MCF_REG32(0x008A2C) |
| 33 | #define MCF_DSPI_DRSER MCF_REG32(0x008A30) |
| 34 | #define MCF_DSPI_DTFR MCF_REG32(0x008A34) |
| 35 | #define MCF_DSPI_DRFR MCF_REG32(0x008A38) |
| 36 | #define MCF_DSPI_DTFDR0 MCF_REG32(0x008A3C) |
| 37 | #define MCF_DSPI_DTFDR1 MCF_REG32(0x008A40) |
| 38 | #define MCF_DSPI_DTFDR2 MCF_REG32(0x008A44) |
| 39 | #define MCF_DSPI_DTFDR3 MCF_REG32(0x008A48) |
| 40 | #define MCF_DSPI_DTFDRn(x) MCF_REG32(0x008A3C+(x*4)) |
| 41 | #define MCF_DSPI_DRFDR0 MCF_REG32(0x008A7C) |
| 42 | #define MCF_DSPI_DRFDR1 MCF_REG32(0x008A80) |
| 43 | #define MCF_DSPI_DRFDR2 MCF_REG32(0x008A84) |
| 44 | #define MCF_DSPI_DRFDR3 MCF_REG32(0x008A88) |
| 45 | #define MCF_DSPI_DRFDRn(x) MCF_REG32(0x008A7C+(x*4)) |
| 46 | |
| 47 | /* Bit definitions and macros for MCF_DSPI_DMCR */ |
| 48 | #define MCF_DSPI_DMCR_HALT (0x00000001) |
| 49 | #define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) |
| 50 | #define MCF_DSPI_DMCR_CRXF (0x00000400) |
| 51 | #define MCF_DSPI_DMCR_CTXF (0x00000800) |
| 52 | #define MCF_DSPI_DMCR_DRXF (0x00001000) |
| 53 | #define MCF_DSPI_DMCR_DTXF (0x00002000) |
| 54 | #define MCF_DSPI_DMCR_CSIS0 (0x00010000) |
| 55 | #define MCF_DSPI_DMCR_CSIS2 (0x00040000) |
| 56 | #define MCF_DSPI_DMCR_CSIS3 (0x00080000) |
| 57 | #define MCF_DSPI_DMCR_CSIS5 (0x00200000) |
| 58 | #define MCF_DSPI_DMCR_ROOE (0x01000000) |
| 59 | #define MCF_DSPI_DMCR_PCSSE (0x02000000) |
| 60 | #define MCF_DSPI_DMCR_MTFE (0x04000000) |
| 61 | #define MCF_DSPI_DMCR_FRZ (0x08000000) |
| 62 | #define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) |
| 63 | #define MCF_DSPI_DMCR_CSCK (0x40000000) |
| 64 | #define MCF_DSPI_DMCR_MSTR (0x80000000) |
| 65 | |
| 66 | /* Bit definitions and macros for MCF_DSPI_DTCR */ |
| 67 | #define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) |
| 68 | |
| 69 | /* Bit definitions and macros for MCF_DSPI_DCTARn */ |
| 70 | #define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)<<0) |
| 71 | #define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) |
| 72 | #define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) |
| 73 | #define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) |
| 74 | #define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) |
| 75 | #define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) |
| 76 | #define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) |
| 77 | #define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) |
| 78 | #define MCF_DSPI_DCTAR_LSBFE (0x01000000) |
| 79 | #define MCF_DSPI_DCTAR_CPHA (0x02000000) |
| 80 | #define MCF_DSPI_DCTAR_CPOL (0x04000000) |
| 81 | /* #define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) */ |
| 82 | #define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) |
| 83 | #define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) |
| 84 | #define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) |
| 85 | #define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) |
| 86 | #define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) |
| 87 | #define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) |
| 88 | #define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) |
| 89 | #define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) |
| 90 | #define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) |
| 91 | #define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) |
| 92 | #define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) |
| 93 | #define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) |
| 94 | #define MCF_DSPI_DCTAR_PDT_7CLK (0x000A0000) |
| 95 | #define MCF_DSPI_DCTAR_PBR_1CLK (0x00000000) |
| 96 | #define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) |
| 97 | #define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) |
| 98 | #define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) |
| 99 | |
| 100 | /* Bit definitions and macros for MCF_DSPI_DSR */ |
| 101 | #define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) |
| 102 | #define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) |
| 103 | #define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) |
| 104 | #define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) |
| 105 | #define MCF_DSPI_DSR_RFDF (0x00020000) |
| 106 | #define MCF_DSPI_DSR_RFOF (0x00080000) |
| 107 | #define MCF_DSPI_DSR_TFFF (0x02000000) |
| 108 | #define MCF_DSPI_DSR_TFUF (0x08000000) |
| 109 | #define MCF_DSPI_DSR_EOQF (0x10000000) |
| 110 | #define MCF_DSPI_DSR_TXRXS (0x40000000) |
| 111 | #define MCF_DSPI_DSR_TCF (0x80000000) |
| 112 | |
| 113 | /* Bit definitions and macros for MCF_DSPI_DRSER */ |
| 114 | #define MCF_DSPI_DRSER_RFDFS (0x00010000) |
| 115 | #define MCF_DSPI_DRSER_RFDFE (0x00020000) |
| 116 | #define MCF_DSPI_DRSER_RFOFE (0x00080000) |
| 117 | #define MCF_DSPI_DRSER_TFFFS (0x01000000) |
| 118 | #define MCF_DSPI_DRSER_TFFFE (0x02000000) |
| 119 | #define MCF_DSPI_DRSER_TFUFE (0x08000000) |
| 120 | #define MCF_DSPI_DRSER_EOQFE (0x10000000) |
| 121 | #define MCF_DSPI_DRSER_TCFE (0x80000000) |
| 122 | |
| 123 | /* Bit definitions and macros for MCF_DSPI_DTFR */ |
| 124 | #define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) |
| 125 | #define MCF_DSPI_DTFR_CS0 (0x00010000) |
| 126 | #define MCF_DSPI_DTFR_CS2 (0x00040000) |
| 127 | #define MCF_DSPI_DTFR_CS3 (0x00080000) |
| 128 | #define MCF_DSPI_DTFR_CS5 (0x00200000) |
| 129 | #define MCF_DSPI_DTFR_CTCNT (0x04000000) |
| 130 | #define MCF_DSPI_DTFR_EOQ (0x08000000) |
| 131 | #define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) |
| 132 | #define MCF_DSPI_DTFR_CONT (0x80000000) |
| 133 | |
| 134 | /* Bit definitions and macros for MCF_DSPI_DRFR */ |
| 135 | #define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) |
| 136 | |
| 137 | /* Bit definitions and macros for MCF_DSPI_DTFDRn */ |
| 138 | #define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) |
| 139 | #define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) |
| 140 | |
| 141 | /* Bit definitions and macros for MCF_DSPI_DRFDRn */ |
| 142 | #define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) |
| 143 | |
| 144 | /********************************************************************/ |
| 145 | |
| 146 | #endif /* _M5485DSPI_H_ */ |
| 147 | |
