| 1 | /* |
| 2 | * m5485sim.h -- ColdFire 547x/548x System Integration Unit support. |
| 3 | * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
| 4 | */ |
| 5 | #ifndef m5485sim_h |
| 6 | #define m5485sim_h |
| 7 | /* |
| 8 | * System Integration Unit Registers |
| 9 | */ |
| 10 | #define MCF_SDRAMDS MCF_REG32(0x000004) |
| 11 | /* SDRAM Drive Strength */ |
| 12 | #define MCF_SBCR MCF_REG32(0x000010) |
| 13 | /* System Breakpoint Control */ |
| 14 | #define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4)) |
| 15 | /* SDRAM Chip Select X */ |
| 16 | #define MCF_SECSACR MCF_REG32(0x000038) |
| 17 | /* Sequential Access Control */ |
| 18 | #define MCF_RSR MCF_REG32(0x000044) |
| 19 | /* Reset Status */ |
| 20 | #define MCF_JTAGID MCF_REG32(0x000050) |
| 21 | /* JTAG Device Identification */ |
| 22 | #define MCF_XARB_PRIEN MCF_REG32(0x000264) |
| 23 | /* Arbiter master pri enable */ |
| 24 | #define MCF_XARB_PRI MCF_REG32(0x000268) |
| 25 | /* Arbiter master pri levels */ |
| 26 | |
| 27 | /* |
| 28 | * FlexBus Chip Selects Registers |
| 29 | */ |
| 30 | #define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC)) |
| 31 | #define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC)) |
| 32 | #define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC)) |
| 33 | |
| 34 | /* |
| 35 | * Interrupt Controller Registers |
| 36 | */ |
| 37 | #define MCF_IPRH MCF_REG32(0x000700) |
| 38 | #define MCF_IPRL MCF_REG32(0x000704) |
| 39 | #define MCF_IMRH MCF_REG32(0x000708) |
| 40 | #define MCF_IMRL MCF_REG32(0x00070C) |
| 41 | #define MCF_INTFRCH MCF_REG32(0x000710) |
| 42 | #define MCF_INTFRCL MCF_REG32(0x000714) |
| 43 | #define MCF_IRLR MCF_REG08(0x000718) |
| 44 | #define MCF_IACKLPR MCF_REG08(0x000719) |
| 45 | #define MCF_SWIACK MCF_REG08(0x0007E0) |
| 46 | #define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004)) |
| 47 | #define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001)) |
| 48 | |
| 49 | /* |
| 50 | * Slice Timers Registers |
| 51 | */ |
| 52 | #define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010)) |
| 53 | #define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010)) |
| 54 | #define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010)) |
| 55 | #define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010)) |
| 56 | |
| 57 | /* |
| 58 | * Interrupt sources |
| 59 | */ |
| 60 | #define ISC_EPORT_Fn(x) (x) |
| 61 | /* EPORT Interrupts */ |
| 62 | #define ISC_USB_EPn(x) (15+(x)) |
| 63 | /* USB Endopint */ |
| 64 | #define ISC_USB_ISR (22) |
| 65 | /* USB General source */ |
| 66 | #define ISC_USB_AISR (22) |
| 67 | /* USB core source */ |
| 68 | #define ISC_DSPI_OVRFW (25) |
| 69 | /* DSPI overflow */ |
| 70 | #define ISC_DSPI_RFOF (26) |
| 71 | #define ISC_DSPI_RFDF (27) |
| 72 | #define ISC_DSPI_TFUF (28) |
| 73 | #define ISC_DSPI_TCF (29) |
| 74 | #define ISC_DSPI_TFFF (30) |
| 75 | #define ISC_DSPI_EOQF (31) |
| 76 | #define ISC_PSCn(x) (35-(x)) |
| 77 | #define ISC_COMM_TIM (36) |
| 78 | #define ISC_SEC (37) |
| 79 | #define ISC_FEC1 (38) |
| 80 | #define ISC_FEC0 (39) |
| 81 | #define ISC_I2C (40) |
| 82 | #define ISC_PCI_ARB (41) |
| 83 | #define ISC_PCI_CB (42) |
| 84 | #define ISC_PCI_XLB (43) |
| 85 | #define ISC_DMA (48) |
| 86 | #define ISC_CANn_ERR(x) (49+(6*(x))) |
| 87 | #define ISC_CANn_BUSOFF(x) (50+(6*(x))) |
| 88 | #define ISC_CANn_MBOR(x) (51+(6*(x))) |
| 89 | #define ISC_CAN0_WAKEIN (52) |
| 90 | #define ISC_SLTn(x) (54-(x)) |
| 91 | #define ISC_GPTn(x) (62-(x)) |
| 92 | |
| 93 | /* |
| 94 | * Interrupt level and priorities |
| 95 | */ |
| 96 | #define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3)) |
| 97 | #define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2)) |
| 98 | #define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1)) |
| 99 | #define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0)) |
| 100 | #define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7)) |
| 101 | #define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6)) |
| 102 | #define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5)) |
| 103 | #define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4)) |
| 104 | #define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3)) |
| 105 | #define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2)) |
| 106 | #define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1)) |
| 107 | |
| 108 | #define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x))) |
| 109 | #define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7)) |
| 110 | #define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6)) |
| 111 | #define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5)) |
| 112 | #define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4)) |
| 113 | #define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3)) |
| 114 | #define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2)) |
| 115 | #define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1)) |
| 116 | #define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0)) |
| 117 | |
| 118 | #define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7)) |
| 119 | #define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6)) |
| 120 | #define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5)) |
| 121 | #define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4)) |
| 122 | #define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3)) |
| 123 | #define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2)) |
| 124 | #define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1)) |
| 125 | #define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0)) |
| 126 | |
| 127 | #define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7)) |
| 128 | #define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3))) |
| 129 | #define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3)) |
| 130 | #define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2)) |
| 131 | #define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1)) |
| 132 | #define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0)) |
| 133 | |
| 134 | |
| 135 | |
| 136 | |
| 137 | |
| 138 | /********************************************************************/ |
| 139 | |
| 140 | /* |
| 141 | * System Integration Unit Bitfields |
| 142 | */ |
| 143 | |
| 144 | /* SBCR */ |
| 145 | #define MCF_SBCR_PIN2DSPI (0x08000000) |
| 146 | #define MCF_SBCR_DMA2CPU (0x10000000) |
| 147 | #define MCF_SBCR_CPU2DMA (0x20000000) |
| 148 | #define MCF_SBCR_PIN2DMA (0x40000000) |
| 149 | #define MCF_SBCR_PIN2CPU (0x80000000) |
| 150 | |
| 151 | /* SECSACR */ |
| 152 | #define MCF_SECSACR_SEQEN (0x00000001) |
| 153 | |
| 154 | /* RSR */ |
| 155 | #define MCF_RSR_RST (0x00000001) |
| 156 | #define MCF_RSR_RSTWD (0x00000002) |
| 157 | #define MCF_RSR_RSTJTG (0x00000008) |
| 158 | |
| 159 | /* JTAGID */ |
| 160 | #define MCF_JTAGID_REV (0xF0000000) |
| 161 | #define MCF_JTAGID_PROCESSOR (0x0FFFFFFF) |
| 162 | #define MCF_JTAGID_MCF5485 (0x0800C01D) |
| 163 | #define MCF_JTAGID_MCF5484 (0x0800D01D) |
| 164 | #define MCF_JTAGID_MCF5483 (0x0800E01D) |
| 165 | #define MCF_JTAGID_MCF5482 (0x0800F01D) |
| 166 | #define MCF_JTAGID_MCF5481 (0x0801001D) |
| 167 | #define MCF_JTAGID_MCF5480 (0x0801101D) |
| 168 | #define MCF_JTAGID_MCF5475 (0x0801201D) |
| 169 | #define MCF_JTAGID_MCF5474 (0x0801301D) |
| 170 | #define MCF_JTAGID_MCF5473 (0x0801401D) |
| 171 | #define MCF_JTAGID_MCF5472 (0x0801501D) |
| 172 | #define MCF_JTAGID_MCF5471 (0x0801601D) |
| 173 | #define MCF_JTAGID_MCF5470 (0x0801701D) |
| 174 | |
| 175 | |
| 176 | /* |
| 177 | * Interrupt Controller Bitfields |
| 178 | */ |
| 179 | #define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1) |
| 180 | #define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0) |
| 181 | #define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4) |
| 182 | #define MCF_ICR_IP(x) (((x)&0x07)<<0) |
| 183 | #define MCF_ICR_IL(x) (((x)&0x07)<<3) |
| 184 | |
| 185 | /* |
| 186 | * Slice Timers Bitfields |
| 187 | */ |
| 188 | #define MCF_SCR_TEN (0x01000000) |
| 189 | #define MCF_SCR_IEN (0x02000000) |
| 190 | #define MCF_SCR_RUN (0x04000000) |
| 191 | #define MCF_SSR_ST (0x01000000) |
| 192 | #define MCF_SSR_BE (0x02000000) |
| 193 | |
| 194 | |
| 195 | /* |
| 196 | * Some needed coldfire registers |
| 197 | */ |
| 198 | #define MCF_PAR_PCIBG MCF_REG16(0x000A48) |
| 199 | #define MCF_PAR_PCIBR MCF_REG16(0x000A4A) |
| 200 | #define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3)) |
| 201 | #define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44) |
| 202 | #define MCF_PAR_DSPI MCF_REG16(0x000A50) |
| 203 | #define MCF_PAR_TIMER MCF_REG08(0X000A52) |
| 204 | #define MCF_EPPAR MCF_REG16(0x000F00) |
| 205 | #define MCF_EPDDR MCF_REG08(0x000F04) |
| 206 | #define MCF_EPIER MCF_REG08(0x000F05) |
| 207 | #define MCF_EPFR MCF_REG08(0x000F0C) |
| 208 | |
| 209 | /* |
| 210 | * Some GPIO bitfields |
| 211 | */ |
| 212 | #define MCF_PAR_SDA (0x0008) |
| 213 | #define MCF_PAR_SCL (0x0004) |
| 214 | #define MCF_PAR_PSC_TXD (0x04) |
| 215 | #define MCF_PAR_PSC_RXD (0x08) |
| 216 | #define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) |
| 217 | #define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) |
| 218 | #define MCF_PAR_PSC_CTS_GPIO (0x00) |
| 219 | #define MCF_PAR_PSC_CTS_BCLK (0x80) |
| 220 | #define MCF_PAR_PSC_CTS_CTS (0xC0) |
| 221 | #define MCF_PAR_PSC_RTS_GPIO (0x00) |
| 222 | #define MCF_PAR_PSC_RTS_FSYNC (0x20) |
| 223 | #define MCF_PAR_PSC_RTS_RTS (0x30) |
| 224 | #define MCF_PAR_PSC_CANRX (0x40) |
| 225 | |
| 226 | /* |
| 227 | * FlexCAN Module Configuration Register |
| 228 | */ |
| 229 | #define CANMCR_MDIS (0x80000000) |
| 230 | #define CANMCR_FRZ (0x40000000) |
| 231 | #define CANMCR_HALT (0x10000000) |
| 232 | #define CANMCR_SOFTRST (0x02000000) |
| 233 | #define CANMCR_NOTRDY (0x08000000) |
| 234 | #define CANMCR_FRZACK (0x01000000) |
| 235 | #define CANMCR_SUPV (0x00800000) |
| 236 | #define CANMCR_MAXMB (0x0F) |
| 237 | /* |
| 238 | * FlexCAN Control Register |
| 239 | */ |
| 240 | #define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) |
| 241 | #define CANCTRL_RJW(x) (((x)&0x03)<<22) |
| 242 | #define CANCTRL_PSEG1(x) (((x)&0x07)<<19) |
| 243 | #define CANCTRL_PSEG2(x) (((x)&0x07)<<16) |
| 244 | #define CANCTRL_BOFFMSK (0x00008000) |
| 245 | #define CANCTRL_ERRMSK (0x00004000) |
| 246 | #define CANCTRL_CLKSRC (0x00002000) |
| 247 | #define CANCTRL_LPB (0x00001000) |
| 248 | #define CANCTRL_SAMP(x) (((x)&0x01)<<7) |
| 249 | #define CANCTRL_BOFFREC (0x00000040) |
| 250 | #define CANCTRL_TSYNC (0x00000020) |
| 251 | #define CANCTRL_LBUF (0x00000010) |
| 252 | #define CANCTRL_LOM (0x00000008) |
| 253 | #define CANCTRL_PROPSEG(x) ((x)&0x07) |
| 254 | |
| 255 | /* |
| 256 | * FlexCAN Error Counter Register |
| 257 | */ |
| 258 | #define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) |
| 259 | #define ERRCNT_TXECTR(x) ((x)&0xFF) |
| 260 | |
| 261 | /* |
| 262 | * FlexCAN Error and Status Register |
| 263 | */ |
| 264 | #define ERRSTAT_BITERR(x) (((x)&0x03)<<14) |
| 265 | #define ERRSTAT_ACKERR (0x00002000) |
| 266 | #define ERRSTAT_CRCERR (0x00001000) |
| 267 | #define ERRSTAT_FRMERR (0x00000800) |
| 268 | #define ERRSTAT_STFERR (0x00000400) |
| 269 | #define ERRSTAT_TXWRN (0x00000200) |
| 270 | #define ERRSTAT_RXWRN (0x00000100) |
| 271 | #define ERRSTAT_IDLE (0x00000080) |
| 272 | #define ERRSTAT_TXRX (0x00000040) |
| 273 | #define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) |
| 274 | #define ERRSTAT_BOFFINT (0x00000004) |
| 275 | #define ERRSTAT_ERRINT (0x00000002) |
| 276 | |
| 277 | /* |
| 278 | * Interrupt Mask Register |
| 279 | */ |
| 280 | #define IMASK_BUF15M (0x8000) |
| 281 | #define IMASK_BUF14M (0x4000) |
| 282 | #define IMASK_BUF13M (0x2000) |
| 283 | #define IMASK_BUF12M (0x1000) |
| 284 | #define IMASK_BUF11M (0x0800) |
| 285 | #define IMASK_BUF10M (0x0400) |
| 286 | #define IMASK_BUF9M (0x0200) |
| 287 | #define IMASK_BUF8M (0x0100) |
| 288 | #define IMASK_BUF7M (0x0080) |
| 289 | #define IMASK_BUF6M (0x0040) |
| 290 | #define IMASK_BUF5M (0x0020) |
| 291 | #define IMASK_BUF4M (0x0010) |
| 292 | #define IMASK_BUF3M (0x0008) |
| 293 | #define IMASK_BUF2M (0x0004) |
| 294 | #define IMASK_BUF1M (0x0002) |
| 295 | #define IMASK_BUF0M (0x0001) |
| 296 | #define IMASK_BUFnM(x) (0x1<<(x)) |
| 297 | #define IMASK_BUFF_ENABLE_ALL (0xFFFF) |
| 298 | #define IMASK_BUFF_DISABLE_ALL (0x0000) |
| 299 | |
| 300 | /* |
| 301 | * Interrupt Flag Register |
| 302 | */ |
| 303 | #define IFLAG_BUF15M (0x8000) |
| 304 | #define IFLAG_BUF14M (0x4000) |
| 305 | #define IFLAG_BUF13M (0x2000) |
| 306 | #define IFLAG_BUF12M (0x1000) |
| 307 | #define IFLAG_BUF11M (0x0800) |
| 308 | #define IFLAG_BUF10M (0x0400) |
| 309 | #define IFLAG_BUF9M (0x0200) |
| 310 | #define IFLAG_BUF8M (0x0100) |
| 311 | #define IFLAG_BUF7M (0x0080) |
| 312 | #define IFLAG_BUF6M (0x0040) |
| 313 | #define IFLAG_BUF5M (0x0020) |
| 314 | #define IFLAG_BUF4M (0x0010) |
| 315 | #define IFLAG_BUF3M (0x0008) |
| 316 | #define IFLAG_BUF2M (0x0004) |
| 317 | #define IFLAG_BUF1M (0x0002) |
| 318 | #define IFLAG_BUF0M (0x0001) |
| 319 | #define IFLAG_BUFF_SET_ALL (0xFFFF) |
| 320 | #define IFLAG_BUFF_CLEAR_ALL (0x0000) |
| 321 | #define IFLAG_BUFnM(x) (0x1<<(x)) |
| 322 | |
| 323 | /* |
| 324 | * Message Buffers |
| 325 | */ |
| 326 | #define MB_CNT_CODE(x) (((x)&0x0F)<<24) |
| 327 | #define MB_CNT_SRR (0x00400000) |
| 328 | #define MB_CNT_IDE (0x00200000) |
| 329 | #define MB_CNT_RTR (0x00100000) |
| 330 | #define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) |
| 331 | #define MB_ID_STD (0x07FF) |
| 332 | #define MB_ID_EXT (0x1FFFFFFF) |
| 333 | #define MB_CODE_MASK (0xF0FFFFFF) |
| 334 | #define CAN_MB 16 |
| 335 | #define PDEV_MAX 2 |
| 336 | |
| 337 | /* |
| 338 | * Some used coldfire values |
| 339 | */ |
| 340 | #define MCF_EPIER_EPIE(x) (0x01 << (x)) |
| 341 | #define MCF_EPPAR_EPPAx_FALLING (2) |
| 342 | #define MCF_EPPAR_EPPA(n, x) (((x)&0x0003) << (2*n)) |
| 343 | |
| 344 | |
| 345 | #endif /* m5485sim_h */ |
| 346 | |
