Root/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/mcffec.h

1/*
2 * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All rights reserved.
3 * Author: Chenghu Wu <b16972@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
20 */
21#ifndef __MCFFEC_H__
22#define __MCFFEC_H
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/skbuff.h>
26#include <linux/spinlock.h>
27#include <linux/workqueue.h>
28#include <linux/platform_device.h>
29#include <asm/pgtable.h>
30
31/* The FEC stores dest/src/type, data, and checksum for receive packets.
32 */
33#define PKT_MAXBUF_SIZE 1518
34
35/*
36 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
37 * size bits. Other FEC hardware does not, so we need to take that into
38 * account when setting it.
39 */
40#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
41    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
42    defined(CONFIG_M537x) || defined(CONFIG_M5301x) || \
43    defined(CONFIG_M5445X)
44#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
45#else
46#define OPT_FRAME_SIZE 0
47#endif
48/*
49 * Some hardware gets it MAC address out of local flash memory.
50 * if this is non-zero then assume it is the address to get MAC from.
51 */
52#if defined(CONFIG_NETtel)
53#define FEC_FLASHMAC 0xf0006006
54#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
55#define FEC_FLASHMAC 0xf0006000
56#elif defined(CONFIG_CANCam)
57#define FEC_FLASHMAC 0xf0020000
58#elif defined(CONFIG_M5272C3)
59#define FEC_FLASHMAC (0xffe04000 + 4)
60#elif defined(CONFIG_MOD5272)
61#define FEC_FLASHMAC 0xffc0406b
62#else
63#define FEC_FLASHMAC 0
64#endif
65
66#ifdef CONFIG_FEC_DMA_USE_SRAM
67#define TX_RING_SIZE 8 /* Must be power of two */
68#define TX_RING_MOD_MASK 7 /* for this to work */
69#else
70#define TX_RING_SIZE 16 /* Must be power of two */
71#define TX_RING_MOD_MASK 15 /* for this to work */
72#endif
73
74typedef struct fec {
75    unsigned long fec_reserved0;
76    unsigned long fec_ievent; /* Interrupt event reg */
77    unsigned long fec_imask; /* Interrupt mask reg */
78    unsigned long fec_reserved1;
79    unsigned long fec_r_des_active; /* Receive descriptor reg */
80    unsigned long fec_x_des_active; /* Transmit descriptor reg */
81    unsigned long fec_reserved2[3];
82    unsigned long fec_ecntrl; /* Ethernet control reg */
83    unsigned long fec_reserved3[6];
84    unsigned long fec_mii_data; /* MII manage frame reg */
85    unsigned long fec_mii_speed; /* MII speed control reg */
86    unsigned long fec_reserved4[7];
87    unsigned long fec_mib_ctrlstat; /* MIB control/status reg */
88    unsigned long fec_reserved5[7];
89    unsigned long fec_r_cntrl; /* Receive control reg */
90    unsigned long fec_reserved6[15];
91    unsigned long fec_x_cntrl; /* Transmit Control reg */
92    unsigned long fec_reserved7[7];
93    unsigned long fec_addr_low; /* Low 32bits MAC address */
94    unsigned long fec_addr_high; /* High 16bits MAC address */
95    unsigned long fec_opd; /* Opcode + Pause duration */
96    unsigned long fec_reserved8[10];
97    unsigned long fec_hash_table_high; /* High 32bits hash table */
98    unsigned long fec_hash_table_low; /* Low 32bits hash table */
99    unsigned long fec_grp_hash_table_high;/* High 32bits hash table */
100    unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */
101    unsigned long fec_reserved9[7];
102    unsigned long fec_x_wmrk; /* FIFO transmit water mark */
103    unsigned long fec_reserved10;
104    unsigned long fec_r_bound; /* FIFO receive bound reg */
105    unsigned long fec_r_fstart; /* FIFO receive start reg */
106    unsigned long fec_reserved11[11];
107    unsigned long fec_r_des_start; /* Receive descriptor ring */
108    unsigned long fec_x_des_start; /* Transmit descriptor ring */
109    unsigned long fec_r_buff_size; /* Maximum receive buff size */
110} fec_t;
111
112/*
113 * Define the buffer descriptor structure.
114 */
115typedef struct bufdesc {
116    unsigned short cbd_sc; /* Control and status info */
117    unsigned short cbd_datlen; /* Data length */
118    unsigned long cbd_bufaddr; /* Buffer address */
119} cbd_t;
120
121/* Forward declarations of some structures to support different PHYs
122 */
123typedef struct {
124    uint mii_data;
125    void (*funct)(uint mii_reg, struct net_device *dev);
126} phy_cmd_t;
127
128typedef struct {
129    uint id;
130    char *name;
131
132    const phy_cmd_t *config;
133    const phy_cmd_t *startup;
134    const phy_cmd_t *ack_int;
135    const phy_cmd_t *shutdown;
136} phy_info_t;
137
138/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
139 * tx_bd_base always point to the base of the buffer descriptors. The
140 * cur_rx and cur_tx point to the currently available buffer.
141 * The dirty_tx tracks the current buffer that is being sent by the
142 * controller. The cur_tx and dirty_tx are equal under both completely
143 * empty and completely full conditions. The empty/ready indicator in
144 * the buffer descriptor determines the actual condition.
145 */
146struct fec_enet_private {
147    /* Hardware registers of the FEC device */
148    volatile fec_t *hwp;
149
150    struct net_device *netdev;
151    struct platform_device *pdev;
152    /* The saved address of a sent-in-place packet/buffer, for skfree(). */
153    unsigned char *tx_bounce[TX_RING_SIZE];
154    struct sk_buff *tx_skbuff[TX_RING_SIZE];
155    ushort skb_cur;
156    ushort skb_dirty;
157
158    /* CPM dual port RAM relative addresses.
159    */
160    cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
161    cbd_t *tx_bd_base;
162    cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
163    cbd_t *dirty_tx; /* The ring entries to be free()ed. */
164    uint tx_full;
165    /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
166    spinlock_t hw_lock;
167
168    /* hold while accessing the mii_list_t() elements */
169    spinlock_t mii_lock;
170    struct mii_bus *mdio_bus;
171    struct phy_device *phydev;
172
173    uint phy_id;
174    uint phy_id_done;
175    uint phy_status;
176    uint phy_speed;
177    phy_info_t const *phy;
178    struct work_struct phy_task;
179    volatile fec_t *phy_hwp;
180
181    uint sequence_done;
182    uint mii_phy_task_queued;
183
184    uint phy_addr;
185
186    int index;
187    int opened;
188    int link;
189    int old_link;
190    int full_duplex;
191    int duplex;
192    int speed;
193    int msg_enable;
194};
195
196struct fec_platform_private {
197    struct platform_device *pdev;
198
199    unsigned long quirks;
200    int num_slots; /* Slots on controller */
201    struct fec_enet_private *fep_host[0]; /* Pointers to hosts */
202};
203
204#endif
205

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