| 1 | |
| 2 | #define FEC_BASE_ADDR_FEC0 ((unsigned int)MCF_MBAR + 0x9000) |
| 3 | #define FEC_BASE_ADDR_FEC1 ((unsigned int)MCF_MBAR + 0x9800) |
| 4 | |
| 5 | /* |
| 6 | #define FEC_INTC_IMRH_INT_MASK38 (0x00000040) |
| 7 | #define FEC_INTC_IMRH_INT_MASK39 (0x00000080) |
| 8 | #define FEC_INTC_ICR_FEC0 (0x30) |
| 9 | #define FEC_INTC_ICR_FEC1 (0x31) |
| 10 | */ |
| 11 | #define FEC_FECI2CIRQ (0xFFC0) |
| 12 | #define FEC_GPIO_PAR_FECI2CIRQ \ |
| 13 | (*(volatile unsigned short *)((unsigned int)MCF_MBAR + 0xA44)) |
| 14 | /* |
| 15 | #define FEC_INTC_ICRn(x) \ |
| 16 | (*(volatile unsigned char *)(void*) |
| 17 | ((unsigned int) MCF_MBAR + 0x000740+((x)*0x001))) |
| 18 | #define FEC_INTC_IMRH \ |
| 19 | *(volatile unsigned int*)((unsigned int)MCF_MBAR + 0x000708) |
| 20 | */ |
| 21 | #define FEC_ECR_DISABLE (0x00000000) |
| 22 | |
| 23 | #define FEC_ECR(x) \ |
| 24 | (*(volatile unsigned int *)(x + 0x024)) |
| 25 | #define FEC_EIR(x) \ |
| 26 | (*(volatile unsigned int *)(x + 0x004)) |
| 27 | #define FEC_PALR(x) \ |
| 28 | (*(volatile unsigned int *)(x + 0x0E4)) |
| 29 | #define FEC_PAUR(x) \ |
| 30 | (*(volatile unsigned int *)(x + 0x0E8)) |
| 31 | #define FEC_IALR(x) \ |
| 32 | (*(volatile unsigned int *)(x + 0x11C)) |
| 33 | #define FEC_IAUR(x) \ |
| 34 | (*(volatile unsigned int *)(x + 0x118)) |
| 35 | #define FEC_GALR(x) \ |
| 36 | (*(volatile unsigned int *)(x + 0x124)) |
| 37 | #define FEC_GAUR(x) \ |
| 38 | (*(volatile unsigned int *)(x + 0x120)) |
| 39 | #define FEC_RCR(x) \ |
| 40 | (*(volatile unsigned int *)(x + 0x084)) |
| 41 | #define FEC_FECRFCR(x) \ |
| 42 | (*(volatile unsigned int *)(x + 0x18C)) |
| 43 | #define FEC_FECRFAR(x) \ |
| 44 | (*(volatile unsigned int *)(x + 0x198)) |
| 45 | #define FEC_FECTFCR(x) \ |
| 46 | (*(volatile unsigned int *)(x + 0x1AC)) |
| 47 | #define FEC_FECTFAR(x) \ |
| 48 | (*(volatile unsigned int *)(x + 0x1B8)) |
| 49 | #define FEC_FECTFWR(x) \ |
| 50 | (*(volatile unsigned int *)(x + 0x144)) |
| 51 | #define FEC_CTCWR(x) \ |
| 52 | (*(volatile unsigned int *)(x + 0x1C8)) |
| 53 | #define FEC_EIMR(x) \ |
| 54 | (*(volatile unsigned int *)(x + 0x008)) |
| 55 | #define FEC_TCR(x) \ |
| 56 | (*(volatile unsigned int *)(x + 0x0C4)) |
| 57 | #define FEC_MIBC(x) \ |
| 58 | (*(volatile unsigned int *)(x + 0x064)) |
| 59 | #define FEC_MSCR(x) \ |
| 60 | (*(volatile unsigned int *)(x + 0x044)) |
| 61 | #define FEC_FECTFDR(x) \ |
| 62 | (*(volatile unsigned int *)(x + 0x1A4)) |
| 63 | #define FEC_FECRFDR(x) \ |
| 64 | (*(volatile unsigned int *)(x + 0x184)) |
| 65 | #define FEC_FECTFSR(x) \ |
| 66 | (*(volatile unsigned int *)(x + 0x1A8)) |
| 67 | #define FEC_FECRFSR(x) \ |
| 68 | (*(volatile unsigned int *)(x + 0x188)) |
| 69 | #define FECSTAT_RMON_R_PACKETS(x) \ |
| 70 | (*(volatile unsigned int *)(x + 0x284)) |
| 71 | #define FECSTAT_RMON_T_PACKETS(x) \ |
| 72 | (*(volatile unsigned int *)(x + 0x204)) |
| 73 | #define FECSTAT_RMON_R_OCTETS(x) \ |
| 74 | (*(volatile unsigned int *)(x + 0x2C4)) |
| 75 | #define FECSTAT_RMON_T_OCTETS(x) \ |
| 76 | (*(volatile unsigned int *)(x + 0x244)) |
| 77 | #define FECSTAT_RMON_R_UNDERSIZE(x) \ |
| 78 | (*(volatile unsigned int *)(x + 0x294)) |
| 79 | #define FECSTAT_RMON_R_OVERSIZE(x) \ |
| 80 | (*(volatile unsigned int *)(x + 0x298)) |
| 81 | #define FECSTAT_RMON_R_FRAG(x) \ |
| 82 | (*(volatile unsigned int *)(x + 0x29C)) |
| 83 | #define FECSTAT_RMON_R_JAB(x) \ |
| 84 | (*(volatile unsigned int *)(x + 0x2A0)) |
| 85 | #define FECSTAT_RMON_R_MC_PKT(x) \ |
| 86 | (*(volatile unsigned int *)(x + 0x28C)) |
| 87 | #define FECSTAT_RMON_T_COL(x) \ |
| 88 | (*(volatile unsigned int *)(x + 0x224)) |
| 89 | #define FECSTAT_IEEE_R_ALIGN(x) \ |
| 90 | (*(volatile unsigned int *)(x + 0x2D4)) |
| 91 | #define FECSTAT_IEEE_R_CRC(x) \ |
| 92 | (*(volatile unsigned int *)(x + 0x2D0)) |
| 93 | #define FECSTAT_IEEE_R_MACERR(x) \ |
| 94 | (*(volatile unsigned int *)(x + 0x2D8)) |
| 95 | #define FECSTAT_IEEE_T_CSERR(x) \ |
| 96 | (*(volatile unsigned int *)(x + 0x268)) |
| 97 | #define FECSTAT_IEEE_T_MACERR(x) \ |
| 98 | (*(volatile unsigned int *)(x + 0x264)) |
| 99 | #define FECSTAT_IEEE_T_LCOL(x) \ |
| 100 | (*(volatile unsigned int *)(x + 0x25C)) |
| 101 | #define FECSTAT_IEEE_R_OCTETS_OK(x) \ |
| 102 | (*(volatile unsigned int *)(x + 0x2E0)) |
| 103 | #define FECSTAT_IEEE_T_OCTETS_OK(x) \ |
| 104 | (*(volatile unsigned int *)(x + 0x274)) |
| 105 | #define FECSTAT_IEEE_R_DROP(x) \ |
| 106 | (*(volatile unsigned int *)(x + 0x2C8)) |
| 107 | #define FECSTAT_IEEE_T_DROP(x) \ |
| 108 | (*(volatile unsigned int *)(x + 0x248)) |
| 109 | #define FECSTAT_IEEE_R_FRAME_OK(x) \ |
| 110 | (*(volatile unsigned int *)(x + 0x2CC)) |
| 111 | #define FECSTAT_IEEE_T_FRAME_OK(x) \ |
| 112 | (*(volatile unsigned int *)(x + 0x24C)) |
| 113 | #define FEC_MMFR(x) \ |
| 114 | (*(volatile unsigned int *)(x + 0x040)) |
| 115 | #define FEC_FECFRST(x) \ |
| 116 | (*(volatile unsigned int *)(x + 0x1C4)) |
| 117 | |
| 118 | #define FEC_MAX_FRM_SIZE (1518) |
| 119 | #define FEC_MAXBUF_SIZE (1520) |
| 120 | |
| 121 | /* Register values */ |
| 122 | #define FEC_ECR_RESET (0x00000001) |
| 123 | #define FEC_EIR_CLEAR (0xFFFFFFFF) |
| 124 | #define FEC_EIR_RL (0x00100000) |
| 125 | #define FEC_EIR_HBERR (0x80000000) |
| 126 | #define FEC_EIR_BABR (0x40000000) |
| 127 | /* babbling receive error */ |
| 128 | #define FEC_EIR_BABT (0x20000000) |
| 129 | /* babbling transmit error */ |
| 130 | #define FEC_EIR_TXF (0x08000000) |
| 131 | /* transmit frame interrupt */ |
| 132 | #define FEC_EIR_MII (0x00800000) |
| 133 | /* MII interrupt */ |
| 134 | #define FEC_EIR_LC (0x00200000) |
| 135 | /* late collision */ |
| 136 | #define FEC_EIR_XFUN (0x00080000) |
| 137 | /* transmit FIFO underrun */ |
| 138 | #define FEC_EIR_XFERR (0x00040000) |
| 139 | /* transmit FIFO error */ |
| 140 | #define FEC_EIR_RFERR (0x00020000) |
| 141 | /* receive FIFO error */ |
| 142 | #define FEC_RCR_MAX_FRM_SIZE (FEC_MAX_FRM_SIZE << 16) |
| 143 | #define FEC_RCR_MII (0x00000004) |
| 144 | #define FEC_FECRFCR_FAE (0x00400000) |
| 145 | /* frame accept error */ |
| 146 | #define FEC_FECRFCR_RXW (0x00200000) |
| 147 | /* receive wait condition */ |
| 148 | #define FEC_FECRFCR_UF (0x00100000) |
| 149 | /* receive FIFO underflow */ |
| 150 | #define FEC_FECRFCR_FRM (0x08000000) |
| 151 | #define FEC_FECRFCR_GR (0x7 << 24) |
| 152 | |
| 153 | #define FEC_EIMR_DISABLE (0x00000000) |
| 154 | |
| 155 | #define FEC_FECRFAR_ALARM (0x300) |
| 156 | #define FEC_FECTFCR_FRM (0x08000000) |
| 157 | #define FEC_FECTFCR_GR (0x7 << 24) |
| 158 | #define FEC_FECTFCR_FAE (0x00400000) |
| 159 | /* frame accept error */ |
| 160 | #define FEC_FECTFCR_TXW (0x00040000) |
| 161 | /* transmit wait condition */ |
| 162 | #define FEC_FECTFCR_UF (0x00100000) |
| 163 | /* transmit FIFO underflow */ |
| 164 | #define FEC_FECTFCR_OF (0x00080000) |
| 165 | /* transmit FIFO overflow */ |
| 166 | |
| 167 | #define FEC_FECTFAR_ALARM (0x100) |
| 168 | #define FEC_FECTFWR_XWMRK (0x00000000) |
| 169 | |
| 170 | #define FEC_FECTFSR_MSK (0xC0B00000) |
| 171 | #define FEC_FECTFSR_TXW (0x40000000) |
| 172 | /* transmit wait condition */ |
| 173 | #define FEC_FECTFSR_FAE (0x00800000) |
| 174 | /* frame accept error */ |
| 175 | #define FEC_FECTFSR_UF (0x00200000) |
| 176 | /* transmit FIFO underflow */ |
| 177 | #define FEC_FECTFSR_OF (0x00100000) |
| 178 | /* transmit FIFO overflow */ |
| 179 | |
| 180 | #define FEC_FECRFSR_MSK (0x80F00000) |
| 181 | #define FEC_FECRFSR_FAE (0x00800000) |
| 182 | /* frame accept error */ |
| 183 | #define FEC_FECRFSR_RXW (0x00400000) |
| 184 | /* receive wait condition */ |
| 185 | #define FEC_FECRFSR_UF (0x00200000) |
| 186 | /* receive FIFO underflow */ |
| 187 | |
| 188 | #define FEC_CTCWR_TFCW_CRC (0x03000000) |
| 189 | #define FEC_TCR_FDEN (0x00000004) |
| 190 | #define FEC_TCR_HBC (0x00000002) |
| 191 | #define FEC_RCR_DRT (0x00000002) |
| 192 | #define FEC_EIMR_MASK (FEC_EIR_RL | FEC_EIR_HBERR) |
| 193 | #define FEC_ECR_ETHEREN (0x00000002) |
| 194 | #define FEC_FECTFCR_MSK (0x00FC0000) |
| 195 | #define FEC_FECRFCR_MSK (0x00F80000) |
| 196 | #define FEC_EIR_GRA (0x10000000) |
| 197 | #define FEC_TCR_GTS (0x00000001) |
| 198 | #define FEC_MIBC_ENABLE (0x00000000) |
| 199 | #define FEC_MIB_LEN (228) |
| 200 | #define FEC_PHY_ADDR (0x01) |
| 201 | |
| 202 | #define FEC_RX_DMA_PRI (6) |
| 203 | #define FEC_TX_DMA_PRI (6) |
| 204 | |
| 205 | #define FEC_TX_BUF_NUMBER (8) |
| 206 | #define FEC_RX_BUF_NUMBER (64) |
| 207 | |
| 208 | #define FEC_TX_INDEX_MASK (0x7) |
| 209 | #define FEC_RX_INDEX_MASK (0x3f) |
| 210 | |
| 211 | #define FEC_RX_DESC_FEC0 SYS_SRAM_FEC_START |
| 212 | #define FEC_TX_DESC_FEC0 \ |
| 213 | (FEC_RX_DESC_FEC0 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)) |
| 214 | |
| 215 | #define FEC_RX_DESC_FEC1 \ |
| 216 | (SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE/2) |
| 217 | #define FEC_TX_DESC_FEC1 \ |
| 218 | (FEC_RX_DESC_FEC1 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)) |
| 219 | |
| 220 | #define FEC_EIR_MII (0x00800000) |
| 221 | #define FEC_MMFR_READ (0x60020000) |
| 222 | #define FEC_MMFR_WRITE (0x50020000) |
| 223 | |
| 224 | #define FEC_FLAGS_RX (0x00000001) |
| 225 | |
| 226 | #define FEC_CRCPOL (0xEDB88320) |
| 227 | |
| 228 | #define FEC_MII_TIMEOUT (2) |
| 229 | #define FEC_GR_TIMEOUT (1) |
| 230 | #define FEC_TX_TIMEOUT (1) |
| 231 | #define FEC_RX_TIMEOUT (1) |
| 232 | |
| 233 | #define FEC_SW_RST 0x2000000 |
| 234 | #define FEC_RST_CTL 0x1000000 |
| 235 | |
| 236 | int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, |
| 237 | unsigned int *data); |
| 238 | int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, |
| 239 | unsigned int data); |
| 240 | |
| 241 | #define FEC_MII_SPEED \ |
| 242 | ((MCF_CLK / 2) / ((2500000 / 2) * 2)) |
| 243 | |
