Root/target/linux/gemini/patches/001-git_sync.patch

1--- a/arch/arm/boot/compressed/head.S
2+++ b/arch/arm/boot/compressed/head.S
3@@ -9,6 +9,7 @@
4  * published by the Free Software Foundation.
5  */
6 #include <linux/linkage.h>
7+#include <asm/cache.h>
8 
9 /*
10  * Debugging stuff
11@@ -355,7 +356,7 @@ params: ldr r0, =0x10000100 @ params_p
12  * This routine must preserve:
13  * r4, r5, r6, r7, r8
14  */
15- .align 5
16+ .align L1_CACHE_SHIFT
17 cache_on: mov r3, #8 @ cache_on function
18         b call_cache_fn
19 
20@@ -544,7 +545,7 @@ __common_mmu_cache_on:
21         mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
22         mcr p15, 0, r1, c3, c0, 0 @ load domain access control
23         b 1f
24- .align 5 @ cache line aligned
25+ .align L1_CACHE_SHIFT @ cache line aligned
26 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
27         mrc p15, 0, r0, c1, c0, 0 @ and read it back to
28         sub pc, lr, r0, lsr #32 @ properly flush pipeline
29@@ -563,7 +564,7 @@ __common_mmu_cache_on:
30  * r8 = atags pointer
31  * r9-r12,r14 = corrupted
32  */
33- .align 5
34+ .align L1_CACHE_SHIFT
35 reloc_start: add r9, r5, r0
36         sub r9, r9, #128 @ do not copy the stack
37         debug_reloc_start
38@@ -793,7 +794,7 @@ proc_types:
39  * This routine must preserve:
40  * r4, r6, r7
41  */
42- .align 5
43+ .align L1_CACHE_SHIFT
44 cache_off: mov r3, #12 @ cache_off function
45         b call_cache_fn
46 
47@@ -868,7 +869,7 @@ __armv3_mmu_cache_off:
48  * This routine must preserve:
49  * r0, r4, r5, r6, r7
50  */
51- .align 5
52+ .align L1_CACHE_SHIFT
53 cache_clean_flush:
54         mov r3, #16
55         b call_cache_fn
56--- a/arch/arm/Kconfig
57+++ b/arch/arm/Kconfig
58@@ -307,6 +307,7 @@ config ARCH_GEMINI
59     select CPU_FA526
60     select ARCH_REQUIRE_GPIOLIB
61     select ARCH_USES_GETTIMEOFFSET
62+ select PCI
63     help
64       Support for the Cortina Systems Gemini family SoCs
65 
66@@ -1164,7 +1165,7 @@ config ISA_DMA_API
67     bool
68 
69 config PCI
70- bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
71+ bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX || ARCH_GEMINI
72     help
73       Find out whether you have a PCI motherboard. PCI is the name of a
74       bus system, i.e. the way the CPU talks to the other stuff inside
75--- a/arch/arm/kernel/entry-armv.S
76+++ b/arch/arm/kernel/entry-armv.S
77@@ -23,6 +23,7 @@
78 #include <asm/unwind.h>
79 #include <asm/unistd.h>
80 #include <asm/tls.h>
81+#include <asm/cache.h>
82 
83 #include "entry-header.S"
84 
85@@ -167,7 +168,7 @@ ENDPROC(__und_invalid)
86     stmia r5, {r0 - r4}
87     .endm
88 
89- .align 5
90+ .align L1_CACHE_SHIFT
91 __dabt_svc:
92     svc_entry
93 
94@@ -215,7 +216,7 @@ __dabt_svc:
95  UNWIND(.fnend )
96 ENDPROC(__dabt_svc)
97 
98- .align 5
99+ .align L1_CACHE_SHIFT
100 __irq_svc:
101     svc_entry
102 
103@@ -259,7 +260,7 @@ svc_preempt:
104     b 1b
105 #endif
106 
107- .align 5
108+ .align L1_CACHE_SHIFT
109 __und_svc:
110 #ifdef CONFIG_KPROBES
111     @ If a kprobe is about to simulate a "stmdb sp..." instruction,
112@@ -305,7 +306,7 @@ __und_svc:
113  UNWIND(.fnend )
114 ENDPROC(__und_svc)
115 
116- .align 5
117+ .align L1_CACHE_SHIFT
118 __pabt_svc:
119     svc_entry
120 
121@@ -341,7 +342,7 @@ __pabt_svc:
122  UNWIND(.fnend )
123 ENDPROC(__pabt_svc)
124 
125- .align 5
126+ .align L1_CACHE_SHIFT
127 .LCcralign:
128     .word cr_alignment
129 #ifdef MULTI_DABORT
130@@ -414,7 +415,7 @@ ENDPROC(__pabt_svc)
131 #endif
132     .endm
133 
134- .align 5
135+ .align L1_CACHE_SHIFT
136 __dabt_usr:
137     usr_entry
138     kuser_cmpxchg_check
139@@ -446,7 +447,7 @@ __dabt_usr:
140  UNWIND(.fnend )
141 ENDPROC(__dabt_usr)
142 
143- .align 5
144+ .align L1_CACHE_SHIFT
145 __irq_usr:
146     usr_entry
147     kuser_cmpxchg_check
148@@ -475,7 +476,7 @@ ENDPROC(__irq_usr)
149 
150     .ltorg
151 
152- .align 5
153+ .align L1_CACHE_SHIFT
154 __und_usr:
155     usr_entry
156 
157@@ -691,7 +692,7 @@ __und_usr_unknown:
158     b do_undefinstr
159 ENDPROC(__und_usr_unknown)
160 
161- .align 5
162+ .align L1_CACHE_SHIFT
163 __pabt_usr:
164     usr_entry
165 
166@@ -805,7 +806,7 @@ ENDPROC(__switch_to)
167 #endif
168     .endm
169 
170- .align 5
171+ .align L1_CACHE_SHIFT
172     .globl __kuser_helper_start
173 __kuser_helper_start:
174 
175@@ -845,7 +846,7 @@ __kuser_memory_barrier: @ 0xffff0fa0
176     smp_dmb
177     usr_ret lr
178 
179- .align 5
180+ .align L1_CACHE_SHIFT
181 
182 /*
183  * Reference prototype:
184@@ -972,7 +973,7 @@ kuser_cmpxchg_fixup:
185 
186 #endif
187 
188- .align 5
189+ .align L1_CACHE_SHIFT
190 
191 /*
192  * Reference prototype:
193@@ -1050,7 +1051,7 @@ __kuser_helper_end:
194  * of which is copied into r0 for the mode specific abort handler.
195  */
196     .macro vector_stub, name, mode, correction=0
197- .align 5
198+ .align L1_CACHE_SHIFT
199 
200 vector_\name:
201     .if \correction
202@@ -1181,7 +1182,7 @@ __stubs_start:
203     .long __und_invalid @ e
204     .long __und_invalid @ f
205 
206- .align 5
207+ .align L1_CACHE_SHIFT
208 
209 /*=============================================================================
210  * Undefined FIQs
211@@ -1211,7 +1212,7 @@ vector_addrexcptn:
212  * We group all the following data together to optimise
213  * for CPUs with separate I & D caches.
214  */
215- .align 5
216+ .align L1_CACHE_SHIFT
217 
218 .LCvswi:
219     .word vector_swi
220--- a/arch/arm/kernel/entry-common.S
221+++ b/arch/arm/kernel/entry-common.S
222@@ -10,13 +10,14 @@
223 
224 #include <asm/unistd.h>
225 #include <asm/ftrace.h>
226+#include <asm/cache.h>
227 #include <mach/entry-macro.S>
228 #include <asm/unwind.h>
229 
230 #include "entry-header.S"
231 
232 
233- .align 5
234+ .align L1_CACHE_SHIFT
235 /*
236  * This is the fast syscall return path. We do as little as
237  * possible here, and this includes saving r0 back into the SVC
238@@ -266,7 +267,7 @@ ENDPROC(ftrace_stub)
239 #define A710(code...)
240 #endif
241 
242- .align 5
243+ .align L1_CACHE_SHIFT
244 ENTRY(vector_swi)
245     sub sp, sp, #S_FRAME_SIZE
246     stmia sp, {r0 - r12} @ Calling r0 - r12
247@@ -410,7 +411,7 @@ __sys_trace_return:
248     bl syscall_trace
249     b ret_slow_syscall
250 
251- .align 5
252+ .align L1_CACHE_SHIFT
253 #ifdef CONFIG_ALIGNMENT_TRAP
254     .type __cr_alignment, #object
255 __cr_alignment:
256--- a/arch/arm/kernel/head.S
257+++ b/arch/arm/kernel/head.S
258@@ -21,6 +21,7 @@
259 #include <asm/memory.h>
260 #include <asm/thread_info.h>
261 #include <asm/system.h>
262+#include <asm/cache.h>
263 
264 #ifdef CONFIG_DEBUG_LL
265 #include <mach/debug-macro.S>
266@@ -378,7 +379,7 @@ ENDPROC(__enable_mmu)
267  *
268  * other registers depend on the function called upon completion
269  */
270- .align 5
271+ .align L1_CACHE_SHIFT
272 __turn_mmu_on:
273     mov r0, r0
274     mcr p15, 0, r0, c1, c0, 0 @ write control reg
275--- a/arch/arm/lib/memchr.S
276+++ b/arch/arm/lib/memchr.S
277@@ -11,9 +11,10 @@
278  */
279 #include <linux/linkage.h>
280 #include <asm/assembler.h>
281+#include <asm/cache.h>
282 
283     .text
284- .align 5
285+ .align L1_CACHE_SHIFT
286 ENTRY(memchr)
287 1: subs r2, r2, #1
288     bmi 2f
289--- a/arch/arm/lib/memset.S
290+++ b/arch/arm/lib/memset.S
291@@ -11,9 +11,10 @@
292  */
293 #include <linux/linkage.h>
294 #include <asm/assembler.h>
295+#include <asm/cache.h>
296 
297     .text
298- .align 5
299+ .align L1_CACHE_SHIFT
300     .word 0
301 
302 1: subs r2, r2, #4 @ 1 do we have enough
303--- a/arch/arm/lib/memzero.S
304+++ b/arch/arm/lib/memzero.S
305@@ -9,9 +9,10 @@
306  */
307 #include <linux/linkage.h>
308 #include <asm/assembler.h>
309+#include <asm/cache.h>
310 
311     .text
312- .align 5
313+ .align L1_CACHE_SHIFT
314     .word 0
315 /*
316  * Align the pointer in r0. r3 contains the number of bytes that we are
317--- a/arch/arm/lib/strchr.S
318+++ b/arch/arm/lib/strchr.S
319@@ -11,9 +11,10 @@
320  */
321 #include <linux/linkage.h>
322 #include <asm/assembler.h>
323+#include <asm/cache.h>
324 
325         .text
326- .align 5
327+ .align L1_CACHE_SHIFT
328 ENTRY(strchr)
329         and r1, r1, #0xff
330 1: ldrb r2, [r0], #1
331--- a/arch/arm/lib/strncpy_from_user.S
332+++ b/arch/arm/lib/strncpy_from_user.S
333@@ -10,9 +10,10 @@
334 #include <linux/linkage.h>
335 #include <asm/assembler.h>
336 #include <asm/errno.h>
337+#include <asm/cache.h>
338 
339     .text
340- .align 5
341+ .align L1_CACHE_SHIFT
342 
343 /*
344  * Copy a string from user space to kernel space.
345--- a/arch/arm/lib/strnlen_user.S
346+++ b/arch/arm/lib/strnlen_user.S
347@@ -10,9 +10,10 @@
348 #include <linux/linkage.h>
349 #include <asm/assembler.h>
350 #include <asm/errno.h>
351+#include <asm/cache.h>
352 
353     .text
354- .align 5
355+ .align L1_CACHE_SHIFT
356 
357 /* Prototype: unsigned long __strnlen_user(const char *str, long n)
358  * Purpose : get length of a string in user memory
359--- a/arch/arm/lib/strrchr.S
360+++ b/arch/arm/lib/strrchr.S
361@@ -11,9 +11,10 @@
362  */
363 #include <linux/linkage.h>
364 #include <asm/assembler.h>
365+#include <asm/cache.h>
366 
367         .text
368- .align 5
369+ .align L1_CACHE_SHIFT
370 ENTRY(strrchr)
371         mov r3, #0
372 1: ldrb r2, [r0], #1
373--- a/arch/arm/mach-gemini/board-rut1xx.c
374+++ b/arch/arm/mach-gemini/board-rut1xx.c
375@@ -14,13 +14,35 @@
376 #include <linux/leds.h>
377 #include <linux/input.h>
378 #include <linux/gpio_keys.h>
379+#include <linux/mdio-gpio.h>
380 
381 #include <asm/mach-types.h>
382 #include <asm/mach/arch.h>
383 #include <asm/mach/time.h>
384 
385+#include <mach/gmac.h>
386+
387 #include "common.h"
388 
389+static struct mdio_gpio_platform_data rut1xx_mdio = {
390+ .mdc = 22,
391+ .mdio = 21,
392+ .phy_mask = ~(1 << 1),
393+};
394+
395+static struct platform_device rut1xx_phy_device = {
396+ .name = "mdio-gpio",
397+ .id = 0,
398+ .dev = {
399+ .platform_data = &rut1xx_mdio,
400+ },
401+};
402+
403+static struct gemini_gmac_platform_data gmac_data = {
404+ .bus_id[0] = "0:01",
405+ .interface[0] = PHY_INTERFACE_MODE_MII,
406+};
407+
408 static struct gpio_keys_button rut1xx_keys[] = {
409     {
410         .code = KEY_SETUP,
411@@ -79,9 +101,13 @@ static void __init rut1xx_init(void)
412 {
413     gemini_gpio_init();
414     platform_register_uart();
415+ platform_register_watchdog();
416+ platform_register_usb(0);
417     platform_register_pflash(SZ_8M, NULL, 0);
418     platform_device_register(&rut1xx_leds);
419     platform_device_register(&rut1xx_keys_device);
420+ platform_device_register(&rut1xx_phy_device);
421+ platform_register_ethernet(&gmac_data);
422 }
423 
424 MACHINE_START(RUT100, "Teltonika RUT100")
425--- a/arch/arm/mach-gemini/common.h
426+++ b/arch/arm/mach-gemini/common.h
427@@ -13,6 +13,7 @@
428 #define __GEMINI_COMMON_H__
429 
430 struct mtd_partition;
431+struct gemini_gmac_platform_data;
432 
433 extern void gemini_map_io(void);
434 extern void gemini_init_irq(void);
435@@ -21,8 +22,11 @@ extern void gemini_gpio_init(void);
436 
437 /* Common platform devices registration functions */
438 extern int platform_register_uart(void);
439+extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
440 extern int platform_register_pflash(unsigned int size,
441                     struct mtd_partition *parts,
442                     unsigned int nr_parts);
443+extern int platform_register_usb(unsigned int i);
444+extern int platform_register_watchdog(void);
445 
446 #endif /* __GEMINI_COMMON_H__ */
447--- a/arch/arm/mach-gemini/devices.c
448+++ b/arch/arm/mach-gemini/devices.c
449@@ -17,6 +17,7 @@
450 #include <mach/irqs.h>
451 #include <mach/hardware.h>
452 #include <mach/global_reg.h>
453+#include <mach/gmac.h>
454 
455 static struct plat_serial8250_port serial_platform_data[] = {
456     {
457@@ -45,6 +46,116 @@ int platform_register_uart(void)
458     return platform_device_register(&serial_device);
459 }
460 
461+static struct resource usb0_resources[] = {
462+ {
463+ .start = 0x68000000,
464+ .end = 0x68000fff,
465+ .flags = IORESOURCE_MEM,
466+ },
467+ {
468+ .start = IRQ_USB0,
469+ .end = IRQ_USB0,
470+ .flags = IORESOURCE_IRQ,
471+ },
472+};
473+
474+static struct resource usb1_resources[] = {
475+ {
476+ .start = 0x69000000,
477+ .end = 0x69000fff,
478+ .flags = IORESOURCE_MEM,
479+ },
480+ {
481+ .start = IRQ_USB1,
482+ .end = IRQ_USB1,
483+ .flags = IORESOURCE_IRQ,
484+ },
485+};
486+
487+static u64 usb0_dmamask = 0xffffffffUL;
488+
489+static u64 usb1_dmamask = 0xffffffffUL;
490+
491+static struct platform_device usb_device[] = {
492+ {
493+ .name = "ehci-fotg2xx",
494+ .id = 0,
495+ .dev = {
496+ .dma_mask = &usb0_dmamask,
497+ .coherent_dma_mask = 0xffffffff,
498+ },
499+ .num_resources = ARRAY_SIZE(usb0_resources),
500+ .resource = usb0_resources,
501+ },
502+ {
503+ .name = "ehci-fotg2xx",
504+ .id = 1,
505+ .dev = {
506+ .dma_mask = &usb1_dmamask,
507+ .coherent_dma_mask = 0xffffffff,
508+ },
509+ .num_resources = ARRAY_SIZE(usb1_resources),
510+ .resource = usb1_resources,
511+ },
512+};
513+
514+int platform_register_usb(unsigned int i)
515+{
516+ if (i > 1)
517+ return -EINVAL;
518+
519+ return platform_device_register(&usb_device[i]);
520+}
521+
522+static struct resource gmac_resources[] = {
523+ {
524+ .start = 0x60000000,
525+ .end = 0x6000ffff,
526+ .flags = IORESOURCE_MEM,
527+ },
528+ {
529+ .start = IRQ_GMAC0,
530+ .end = IRQ_GMAC0,
531+ .flags = IORESOURCE_IRQ,
532+ },
533+ {
534+ .start = IRQ_GMAC1,
535+ .end = IRQ_GMAC1,
536+ .flags = IORESOURCE_IRQ,
537+ },
538+};
539+
540+static u64 gmac_dmamask = 0xffffffffUL;
541+
542+static struct platform_device ethernet_device = {
543+ .name = "gemini-gmac",
544+ .id = 0,
545+ .dev = {
546+ .dma_mask = &gmac_dmamask,
547+ .coherent_dma_mask = 0xffffffff,
548+ },
549+ .num_resources = ARRAY_SIZE(gmac_resources),
550+ .resource = gmac_resources,
551+};
552+
553+int platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
554+{
555+ unsigned int reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
556+
557+ reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
558+
559+ if (pdata->bus_id[1])
560+ reg |= GMAC_1_ENABLE;
561+ else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
562+ reg |= GMAC_GMII;
563+
564+ __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
565+
566+ ethernet_device.dev.platform_data = pdata;
567+
568+ return platform_device_register(&ethernet_device);
569+}
570+
571 static struct resource flash_resource = {
572     .start = GEMINI_FLASH_BASE,
573     .flags = IORESOURCE_MEM,
574@@ -90,3 +201,21 @@ int platform_register_pflash(unsigned in
575 
576     return platform_device_register(&pflash_device);
577 }
578+
579+static struct resource wdt_resource = {
580+ .start = GEMINI_WAQTCHDOG_BASE,
581+ .end = GEMINI_WAQTCHDOG_BASE + 0x18,
582+ .flags = IORESOURCE_MEM,
583+};
584+
585+static struct platform_device wdt_device = {
586+ .name = "gemini-wdt",
587+ .id = 0,
588+ .resource = &wdt_resource,
589+ .num_resources = 1,
590+};
591+
592+int platform_register_watchdog(void)
593+{
594+ return platform_device_register(&wdt_device);
595+}
596--- /dev/null
597+++ b/arch/arm/mach-gemini/include/mach/gmac.h
598@@ -0,0 +1,21 @@
599+/*
600+ * Gemini GMAC specific defines
601+ *
602+ * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
603+ *
604+ * This program is free software; you can redistribute it and/or modify
605+ * it under the terms of the GNU General Public License as published by
606+ * the Free Software Foundation; either version 2 of the License, or
607+ * (at your option) any later version.
608+ */
609+#ifndef __MACH_GMAC_H__
610+#define __MACH_GMAC_H__
611+
612+#include <linux/phy.h>
613+
614+struct gemini_gmac_platform_data {
615+ char *bus_id[2]; /* NULL means that this port is not used */
616+ phy_interface_t interface[2];
617+};
618+
619+#endif /* __MACH_GMAC_H__ */
620--- a/arch/arm/mach-gemini/include/mach/hardware.h
621+++ b/arch/arm/mach-gemini/include/mach/hardware.h
622@@ -71,4 +71,12 @@
623  */
624 #define IO_ADDRESS(x) ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
625 
626+/*
627+ * PCI subsystem macros
628+ */
629+#define PCIBIOS_MIN_IO 0x00000100
630+#define PCIBIOS_MIN_MEM 0x00000000
631+
632+#define pcibios_assign_all_busses() 1
633+
634 #endif
635--- a/arch/arm/mach-gemini/include/mach/irqs.h
636+++ b/arch/arm/mach-gemini/include/mach/irqs.h
637@@ -43,11 +43,14 @@
638 
639 #define NORMAL_IRQ_NUM 32
640 
641-#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
642+#define PCI_IRQ_BASE NORMAL_IRQ_NUM
643+#define PCI_IRQ_NUM 4
644+
645+#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM)
646 #define GPIO_IRQ_NUM (3 * 32)
647 
648 #define ARCH_TIMER_IRQ IRQ_TIMER2
649 
650-#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
651+#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM)
652 
653 #endif /* __MACH_IRQS_H__ */
654--- a/arch/arm/mach-gemini/Makefile
655+++ b/arch/arm/mach-gemini/Makefile
656@@ -6,6 +6,8 @@
657 
658 obj-y := irq.o mm.o time.o devices.o gpio.o
659 
660+obj-$(CONFIG_PCI) += pci.o
661+
662 # Board-specific support
663 obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
664 obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
665--- a/arch/arm/mach-gemini/mm.c
666+++ b/arch/arm/mach-gemini/mm.c
667@@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[]
668         .length = SZ_512K,
669         .type = MT_DEVICE,
670     }, {
671+ .virtual = IO_ADDRESS(GEMINI_PCI_IO_BASE),
672+ .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE),
673+ .length = SZ_512K,
674+ .type = MT_DEVICE,
675+ }, {
676         .virtual = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
677         .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
678         .length = SZ_512K,
679--- /dev/null
680+++ b/arch/arm/mach-gemini/pci.c
681@@ -0,0 +1,315 @@
682+/*
683+ * Support for Gemini PCI Controller
684+ *
685+ * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
686+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
687+ *
688+ * based on SL2312 PCI controller code
689+ * Storlink (C) 2003
690+ *
691+ * This program is free software; you can redistribute it and/or modify
692+ * it under the terms of the GNU General Public License as published by
693+ * the Free Software Foundation; either version 2 of the License, or
694+ * (at your option) any later version.
695+ */
696+
697+#include <linux/kernel.h>
698+#include <linux/pci.h>
699+#include <linux/irq.h>
700+
701+#include <asm/mach/pci.h>
702+#include <asm/gpio.h>
703+
704+#include <mach/irqs.h>
705+
706+#define GEMINI_PCI_IOSIZE_1M 0x0000
707+
708+#define GEMINI_PCI_PMC 0x40
709+#define GEMINI_PCI_PMCSR 0x44
710+#define GEMINI_PCI_CTRL1 0x48
711+#define GEMINI_PCI_CTRL2 0x4C
712+#define GEMINI_PCI_MEM1_BASE_SIZE 0x50
713+#define GEMINI_PCI_MEM2_BASE_SIZE 0x54
714+#define GEMINI_PCI_MEM3_BASE_SIZE 0x58
715+
716+#define PCI_CTRL2_INTSTS_OFFSET 28
717+#define PCI_CTRL2_INTMASK_OFFSET 22
718+
719+#define GEMINI_PCI_DMA_MASK 0xFFF00000
720+#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000
721+#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000
722+#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000
723+#define GEMINI_PCI_DMA_MEM1_SIZE 7
724+#define GEMINI_PCI_DMA_MEM2_SIZE 6
725+#define GEMINI_PCI_DMA_MEM3_SIZE 6
726+
727+#define PCI_CONF_ENABLE (1 << 31)
728+#define PCI_CONF_WHERE(r) ((r) & 0xFC)
729+#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
730+#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
731+#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
732+
733+#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE))
734+#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04)
735+#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08)
736+#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10)
737+#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28)
738+#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C)
739+
740+
741+static DEFINE_SPINLOCK(gemini_pci_lock);
742+
743+static struct resource gemini_pci_resource_io = {
744+ .name = "PCI I/O Space",
745+ .start = IO_ADDRESS(GEMINI_PCI_IO_BASE),
746+ .end = IO_ADDRESS(GEMINI_PCI_IO_BASE) + SZ_1M - 1,
747+ .flags = IORESOURCE_IO,
748+};
749+
750+static struct resource gemini_pci_resource_mem = {
751+ .name = "PCI Memory Space",
752+ .start = GEMINI_PCI_MEM_BASE,
753+ .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1,
754+ .flags = IORESOURCE_MEM,
755+};
756+
757+static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn,
758+ int config, int size, u32* value)
759+{
760+ unsigned long irq_flags;
761+
762+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
763+
764+ __raw_writel(PCI_CONF_BUS(bus->number) |
765+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
766+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
767+ PCI_CONF_WHERE(config) |
768+ PCI_CONF_ENABLE,
769+ PCI_CONFIG_REG);
770+
771+ *value = __raw_readl(PCI_DATA_REG);
772+
773+ if (size == 1)
774+ *value = (*value >> (8 * (config & 3))) & 0xFF;
775+ else if (size == 2)
776+ *value = (*value >> (8 * (config & 3))) & 0xFFFF;
777+
778+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
779+
780+ dev_dbg(&bus->dev,
781+ "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
782+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
783+
784+ return PCIBIOS_SUCCESSFUL;
785+}
786+
787+static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn,
788+ int config, int size, u32 value)
789+{
790+ unsigned long irq_flags = 0;
791+ int ret = PCIBIOS_SUCCESSFUL;
792+
793+ dev_dbg(&bus->dev,
794+ "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
795+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
796+
797+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
798+
799+ __raw_writel(PCI_CONF_BUS(bus->number) |
800+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
801+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
802+ PCI_CONF_WHERE(config) |
803+ PCI_CONF_ENABLE,
804+ PCI_CONFIG_REG);
805+
806+ switch(size) {
807+ case 4:
808+ __raw_writel(value, PCI_DATA_REG);
809+ break;
810+ case 2:
811+ __raw_writew(value, PCI_DATA_REG + (config & 3));
812+ break;
813+ case 1:
814+ __raw_writeb(value, PCI_DATA_REG + (config & 3));
815+ break;
816+ default:
817+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
818+ }
819+
820+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
821+
822+ return ret;
823+}
824+
825+static struct pci_ops gemini_pci_ops = {
826+ .read = gemini_pci_read_config,
827+ .write = gemini_pci_write_config,
828+};
829+
830+static int __init gemini_pci_request_resources(struct pci_sys_data *sys)
831+{
832+ if (request_resource(&ioport_resource, &gemini_pci_resource_io))
833+ goto bad_resources;
834+ if (request_resource(&iomem_resource, &gemini_pci_resource_mem))
835+ goto bad_resources;
836+
837+ sys->resource[0] = &gemini_pci_resource_io;
838+ sys->resource[1] = &gemini_pci_resource_mem;
839+ sys->resource[2] = 0;
840+
841+ return 0;
842+
843+bad_resources:
844+ pr_err("Gemini PCI: request_resource() failed. "
845+ "Abort PCI bus enumeration.\n");
846+ return -1;
847+}
848+
849+static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys)
850+{
851+ unsigned int cmd;
852+
853+ if ((nr > 0) || gemini_pci_request_resources(sys))
854+ return 0;
855+
856+ /* setup I/O space to 1MB size */
857+ __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG);
858+
859+ /* setup hostbridge */
860+ cmd = __raw_readl(PCI_CTRL_REG);
861+ cmd |= PCI_COMMAND_IO;
862+ cmd |= PCI_COMMAND_MEMORY;
863+ cmd |= PCI_COMMAND_MASTER;
864+ __raw_writel(cmd, PCI_CTRL_REG);
865+
866+ return 1;
867+}
868+
869+static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys)
870+{
871+ unsigned int reg = 0;
872+ struct pci_bus* bus = 0;
873+
874+ bus = pci_scan_bus(nr, &gemini_pci_ops, sys);
875+ if (bus) {
876+ dev_dbg(&bus->dev, "setting up PCI DMA\n");
877+ reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK)
878+ | (GEMINI_PCI_DMA_MEM1_SIZE << 16);
879+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg);
880+ reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK)
881+ | (GEMINI_PCI_DMA_MEM2_SIZE << 16);
882+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg);
883+ reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK)
884+ | (GEMINI_PCI_DMA_MEM3_SIZE << 16);
885+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg);
886+ }
887+
888+ return bus;
889+}
890+
891+/* Should work with all boards based on original Storlink EVB */
892+static int __init gemini_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
893+{
894+ if (slot < 9 || slot > 12)
895+ return -1;
896+
897+ return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3);
898+}
899+
900+static struct hw_pci gemini_hw_pci __initdata = {
901+ .nr_controllers = 1,
902+ .setup = gemini_pci_setup,
903+ .scan = gemini_pci_scan_bus,
904+ .swizzle = pci_std_swizzle,
905+ .map_irq = gemini_pci_map_irq,
906+};
907+
908+/* we need this for muxed PCI interrupts handling */
909+static struct pci_bus bogus_pci_bus;
910+
911+static void gemini_pci_ack_irq(unsigned int irq)
912+{
913+ unsigned int reg;
914+
915+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
916+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
917+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET);
918+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
919+}
920+
921+static void gemini_pci_mask_irq(unsigned int irq)
922+{
923+ unsigned int reg;
924+
925+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
926+ reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET)
927+ | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET)));
928+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
929+}
930+
931+static void gemini_pci_unmask_irq(unsigned int irq)
932+{
933+ unsigned int reg;
934+
935+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
936+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
937+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET);
938+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
939+}
940+
941+static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
942+{
943+ unsigned int pci_irq_no, irq_stat, reg, i;
944+
945+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
946+ irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET;
947+
948+ for (i = 0; i < 4; i++) {
949+
950+ if ((irq_stat & (1 << i)) == 0)
951+ continue;
952+
953+ pci_irq_no = PCI_IRQ_BASE + i;
954+
955+ BUG_ON(!(irq_desc[pci_irq_no].handle_irq));
956+ irq_desc[pci_irq_no].handle_irq(pci_irq_no,
957+ &irq_desc[pci_irq_no]);
958+ }
959+}
960+
961+static struct irq_chip gemini_pci_irq_chip = {
962+ .name = "PCI",
963+ .ack = gemini_pci_ack_irq,
964+ .mask = gemini_pci_mask_irq,
965+ .unmask = gemini_pci_unmask_irq,
966+};
967+
968+static int __init gemini_pci_init(void)
969+{
970+ int i;
971+
972+ for (i = 72; i <= 95; i++)
973+ gpio_request(i, "PCI");
974+
975+ /* initialize our bogus bus */
976+ dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler");
977+ bogus_pci_bus.number = 0;
978+
979+ /* mask and clear all interrupts */
980+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2,
981+ 0xF000);
982+
983+ for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) {
984+ set_irq_chip(i, &gemini_pci_irq_chip);
985+ set_irq_handler(i, handle_level_irq);
986+ set_irq_flags(i, IRQF_VALID);
987+ }
988+
989+ set_irq_chained_handler(IRQ_PCI, gemini_pci_irq_handler);
990+
991+ pci_common_init(&gemini_hw_pci);
992+
993+ return 0;
994+}
995+
996+subsys_initcall(gemini_pci_init);
997--- a/arch/arm/mm/abort-ev4.S
998+++ b/arch/arm/mm/abort-ev4.S
999@@ -1,5 +1,6 @@
1000 #include <linux/linkage.h>
1001 #include <asm/assembler.h>
1002+#include <asm/cache.h>
1003 /*
1004  * Function: v4_early_abort
1005  *
1006@@ -17,7 +18,7 @@
1007  * abort here if the I-TLB and D-TLB aren't seeing the same
1008  * picture. Unfortunately, this does happen. We live with it.
1009  */
1010- .align 5
1011+ .align L1_CACHE_SHIFT
1012 ENTRY(v4_early_abort)
1013     mrc p15, 0, r1, c5, c0, 0 @ get FSR
1014     mrc p15, 0, r0, c6, c0, 0 @ get FAR
1015--- a/arch/arm/mm/abort-nommu.S
1016+++ b/arch/arm/mm/abort-nommu.S
1017@@ -1,5 +1,6 @@
1018 #include <linux/linkage.h>
1019 #include <asm/assembler.h>
1020+#include <asm/cache.h>
1021 /*
1022  * Function: nommu_early_abort
1023  *
1024@@ -12,7 +13,7 @@
1025  * Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
1026  * Just fill zero into the registers.
1027  */
1028- .align 5
1029+ .align L1_CACHE_SHIFT
1030 ENTRY(nommu_early_abort)
1031     mov r0, #0 @ clear r0, r1 (no FSR/FAR)
1032     mov r1, #0
1033--- /dev/null
1034+++ b/drivers/net/gemini_negmac/gm_gmac.c
1035@@ -0,0 +1,1350 @@
1036+/*
1037+ * Ethernet device driver for Gemini SoC.
1038+ *
1039+ * Copyright (C) 2006, Storlink, Corp.
1040+ * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
1041+ *
1042+ * This program is free software; you can redistribute it and/or modify
1043+ * it under the terms of the GNU General Public License as published by
1044+ * the Free Software Foundation; either version 2 of the License, or
1045+ * (at your option) any later version.
1046+ */
1047+#include <linux/module.h>
1048+#include <linux/kernel.h>
1049+#include <linux/platform_device.h>
1050+#include <linux/slab.h>
1051+#include <linux/mm.h>
1052+#include <linux/compiler.h>
1053+#include <linux/dma-mapping.h>
1054+#include <linux/init.h>
1055+#include <linux/ioport.h>
1056+#include <linux/netdevice.h>
1057+#include <linux/etherdevice.h>
1058+#include <linux/rtnetlink.h>
1059+#include <linux/delay.h>
1060+#include <linux/ethtool.h>
1061+#include <linux/mii.h>
1062+#include <linux/phy.h>
1063+#include <linux/completion.h>
1064+#include <linux/kthread.h>
1065+#include <linux/io.h>
1066+#include <mach/hardware.h>
1067+#include <asm/irq.h>
1068+#include <linux/semaphore.h>
1069+#include <mach/irqs.h>
1070+#include <linux/skbuff.h>
1071+#include <linux/in.h>
1072+#include <linux/ip.h>
1073+#include <linux/tcp.h>
1074+#include <linux/udp.h>
1075+#include <mach/gmac.h>
1076+
1077+#include "gm_gmac.h"
1078+
1079+/* #define GMAX_TX_INTR_DISABLED */
1080+#define DO_HW_CHKSUM
1081+/* #define ENABLE_TSO */
1082+#define GMAC_USE_TXQ0
1083+/* #define GMAC_LEN_1_2_ISSUE */
1084+
1085+#define DEFAULT_RXQ_MAX_CNT 256
1086+
1087+/* define chip information */
1088+#define DRV_VERSION "0.2"
1089+#define SL351x_DRIVER_NAME "Gemini Ethernet driver " DRV_VERSION
1090+
1091+#ifdef GMAC_LEN_1_2_ISSUE
1092+ #define _DEBUG_PREFETCH_NUM 256
1093+static int _debug_prefetch_cnt;
1094+static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
1095+#endif
1096+
1097+static inline void gmac_write_reg(unsigned int base, unsigned int offset, unsigned int data, unsigned int bit_mask)
1098+{
1099+ unsigned int reg_val;
1100+
1101+ reg_val = (__raw_readl(base + offset) & (~bit_mask)) | (data & bit_mask);
1102+ __raw_writel(reg_val, base + offset);
1103+}
1104+
1105+/*----------------------------------------------------------------------
1106+* toe_init_free_queue
1107+* (1) Initialize the Free Queue Descriptor Base Address & size
1108+* Register: TOE_GLOBAL_BASE + 0x0004
1109+* (2) Initialize DMA Read/Write pointer for
1110+* SW Free Queue and HW Free Queue
1111+* (3) Initialize DMA Descriptors for
1112+* SW Free Queue and HW Free Queue,
1113+*----------------------------------------------------------------------*/
1114+static void toe_init_free_queue(struct toe_private *toe)
1115+{
1116+ int i;
1117+ DMA_RWPTR_T rwptr_reg;
1118+ void *desc_buf;
1119+ GMAC_RXDESC_T *sw_desc_ptr;
1120+ struct sk_buff *skb;
1121+
1122+ desc_buf = dma_alloc_coherent(toe->dev, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
1123+ &toe->sw_freeq_desc_base_dma, GFP_KERNEL);
1124+ sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
1125+ if (!desc_buf) {
1126+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1127+ return;
1128+ }
1129+ memset(desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
1130+
1131+ /* DMA Queue Base & Size */
1132+ __raw_writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
1133+ toe->global_base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1134+
1135+ /* init descriptor base */
1136+ toe->swfq_desc_base = (unsigned int)desc_buf;
1137+
1138+ /* SW Free Queue Descriptors */
1139+ for (i = 0; i < TOE_SW_FREEQ_DESC_NUM; i++) {
1140+ sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
1141+ skb = dev_alloc_skb(SW_RX_BUF_SIZE); /* allocate socket buffer */
1142+ if (!skb) {
1143+ dev_err(toe->dev, "%s::skb buffer allocation fail\n", __func__);
1144+ return;
1145+ }
1146+ REG32(skb->data) = (unsigned int)skb;
1147+ skb_reserve(skb, SKB_RESERVE_BYTES);
1148+ sw_desc_ptr->word2.buf_adr = dma_map_single(toe->dev, skb->data,
1149+ SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
1150+ DMA_FROM_DEVICE);
1151+ sw_desc_ptr++;
1152+ }
1153+
1154+ dma_sync_single_for_device(toe->dev, toe->sw_freeq_desc_base_dma,
1155+ TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
1156+ DMA_TO_DEVICE);
1157+
1158+ /* SW Free Queue Read/Write Pointer */
1159+ rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
1160+ rwptr_reg.bits.rptr = 0;
1161+ __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
1162+
1163+ /* DMA Queue Base & Size */
1164+ __raw_writel(TOE_HW_FREEQ_DESC_POWER,
1165+ toe->global_base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
1166+ rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
1167+ rwptr_reg.bits.rptr = 0;
1168+ __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_HWFQ_RWPTR_REG);
1169+}
1170+
1171+/*----------------------------------------------------------------------
1172+* toe_init_swtx_queue
1173+* (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
1174+* GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
1175+* (2) Initialize DMA Read/Write pointer for
1176+* GMAC 0/1 SW TX Q0-5
1177+*----------------------------------------------------------------------*/
1178+static void toe_init_swtx_queue(struct net_device *dev)
1179+{
1180+ int i;
1181+ struct gmac_private *gmac = netdev_priv(dev);
1182+ struct toe_private *toe = dev->ml_priv;
1183+ DMA_RWPTR_T rwptr_reg;
1184+ unsigned int rwptr_addr;
1185+ void *desc_buf;
1186+ unsigned int offset;
1187+
1188+ desc_buf = dma_alloc_coherent(toe->dev, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
1189+ &gmac->swtxq_desc_base_dma, GFP_KERNEL);
1190+ gmac->swtxq_desc_base = (unsigned int)desc_buf;
1191+ if (!desc_buf) {
1192+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1193+ return;
1194+ }
1195+ memset(desc_buf, 0, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
1196+ dma_sync_single_for_device(toe->dev, gmac->swtxq_desc_base_dma,
1197+ TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
1198+ DMA_TO_DEVICE);
1199+ __raw_writel((gmac->swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC_SWTXQ_DESC_POWER,
1200+ gmac->dma_base_addr + GMAC_SW_TX_QUEUE_BASE_REG);
1201+
1202+ /* GMAC0 SW TX Q0-Q5 */
1203+ offset = 0;
1204+ rwptr_reg.bits.wptr = 0;
1205+ rwptr_reg.bits.rptr = 0;
1206+ rwptr_addr = gmac->dma_base_addr + GMAC_SW_TX_QUEUE0_PTR_REG;
1207+ for (i = 0; i < TOE_SW_TXQ_NUM; i++) {
1208+ gmac->swtxq[i].rwptr_reg = rwptr_addr;
1209+ gmac->swtxq[i].desc_base_dma = (unsigned int)gmac->swtxq_desc_base_dma + offset;
1210+ gmac->swtxq[i].desc_base = (unsigned int)desc_buf + offset;
1211+ offset += TOE_GMAC_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
1212+ __raw_writel(rwptr_reg.bits32, rwptr_addr);
1213+ rwptr_addr += 4;
1214+ }
1215+}
1216+
1217+/*----------------------------------------------------------------------
1218+* toe_init_default_queue
1219+* (1) Initialize the default 0/1 Queue Header
1220+* Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
1221+* TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
1222+* (2) Initialize Descriptors of Default Queue 0/1
1223+*----------------------------------------------------------------------*/
1224+static void toe_init_default_queue(struct net_device *dev)
1225+{
1226+ struct gmac_private *gmac = netdev_priv(dev);
1227+ struct toe_private *toe = dev->ml_priv;
1228+ volatile NONTOE_QHDR_T *qhdr;
1229+ GMAC_RXDESC_T *desc_ptr;
1230+
1231+ desc_ptr = dma_alloc_coherent(toe->dev, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
1232+ &gmac->default_desc_base_dma, GFP_KERNEL);
1233+ if (!desc_ptr) {
1234+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1235+ return;
1236+ }
1237+ memset(desc_ptr, 0, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T));
1238+ dma_sync_single_for_device(toe->dev, gmac->default_desc_base_dma,
1239+ TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
1240+ DMA_TO_DEVICE);
1241+ gmac->default_desc_base = (unsigned int)desc_ptr;
1242+ qhdr = (volatile NONTOE_QHDR_T *)(toe->global_base + TOE_DEFAULT_Q_HDR_BASE(gmac->port_id));
1243+ qhdr->word0.base_size = ((unsigned int)gmac->default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q_DESC_POWER;
1244+ qhdr->word1.bits32 = 0;
1245+ gmac->default_qhdr = (NONTOE_QHDR_T *)qhdr;
1246+}
1247+
1248+/*----------------------------------------------------------------------
1249+* toe_init_interrupt_config
1250+* Interrupt Select Registers are used to map interrupt to int0 or int1
1251+* Int0 and int1 are wired to CPU 0/1 GMAC 0/1
1252+* Interrupt Device Inteface data are used to pass device info to
1253+* upper device driver or store status/statistics
1254+* ISR handler
1255+* (1) If status bit ON but masked, the prinf error message (bug issue)
1256+* (2) If select bits are for me, handle it, else skip to let
1257+* the other ISR handles it.
1258+* Notes:
1259+* GMACx init routine (for eCOS) or open routine (for Linux)
1260+* enable the interrupt bits only which are selected for it.
1261+*
1262+* Default Setting:
1263+* GMAC0 intr bits ------> int0 ----> eth0
1264+* GMAC1 intr bits ------> int1 ----> eth1
1265+* TOE intr -------------> int0 ----> eth0
1266+* Classification Intr --> int0 ----> eth0
1267+* Default Q0 -----------> int0 ----> eth0
1268+* Default Q1 -----------> int1 ----> eth1
1269+*----------------------------------------------------------------------*/
1270+static void toe_init_interrupt_config(struct toe_private *toe)
1271+{
1272+ /* clear all status bits */
1273+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
1274+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
1275+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
1276+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
1277+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
1278+
1279+ /* Init select registers */
1280+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1281+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1282+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1283+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1284+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1285+
1286+ /* disable all interrupt */
1287+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1288+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1289+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1290+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1291+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1292+}
1293+
1294+static void toe_gmac_hw_start(struct gmac_private *gmac)
1295+{
1296+ GMAC_DMA_CTRL_T dma_ctrl;
1297+
1298+ /* program dma control register */
1299+ dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1300+ dma_ctrl.bits.rd_enable = 1;
1301+ dma_ctrl.bits.td_enable = 1;
1302+ dma_ctrl.bits.loopback = 0;
1303+ dma_ctrl.bits.drop_small_ack = 0;
1304+ dma_ctrl.bits.rd_prot = 0;
1305+ dma_ctrl.bits.rd_burst_size = 3;
1306+ dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
1307+ dma_ctrl.bits.rd_bus = 3;
1308+ dma_ctrl.bits.td_prot = 0;
1309+ dma_ctrl.bits.td_burst_size = 3;
1310+ dma_ctrl.bits.td_bus = 3;
1311+
1312+ __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1313+}
1314+
1315+static void toe_gmac_hw_stop(struct gmac_private *gmac)
1316+{
1317+ GMAC_DMA_CTRL_T dma_ctrl;
1318+
1319+ /* program dma control register */
1320+ dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1321+ dma_ctrl.bits.rd_enable = 0;
1322+ dma_ctrl.bits.td_enable = 0;
1323+ __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1324+}
1325+
1326+static void toe_gmac_init_chip(struct net_device *dev)
1327+{
1328+ struct gmac_private *gmac = netdev_priv(dev);
1329+ GMAC_CONFIG2_T config2_val;
1330+ GMAC_CONFIG0_T config0;
1331+ GMAC_CONFIG1_T config1;
1332+ GMAC_STATUS_T status;
1333+ GMAC_TX_WCR0_T hw_weigh;
1334+ GMAC_TX_WCR1_T sw_weigh;
1335+ GMAC_RX_FLTR_T rx_filter;
1336+
1337+ /* set RX_FLTR register to receive all multicast packet */
1338+ rx_filter.bits32 = __raw_readl(dev->base_addr + GMAC_RX_FLTR);
1339+ rx_filter.bits.unicast = 1;
1340+ rx_filter.bits.multicast = 1;
1341+ rx_filter.bits.broadcast = 1;
1342+ __raw_writel(rx_filter.bits32, dev->base_addr + GMAC_RX_FLTR);
1343+
1344+ /* set flow control threshold */
1345+ config1.bits32 = 0;
1346+ config1.bits.set_threshold = 32 / 2;
1347+ config1.bits.rel_threshold = 32 / 4 * 3;
1348+ __raw_writel(config1.bits32, dev->base_addr + GMAC_CONFIG1);
1349+
1350+ /* set flow control threshold */
1351+ config2_val.bits32 = 0;
1352+ config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM / 4;
1353+ config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM / 2;
1354+ __raw_writel(config2_val.bits32, dev->base_addr + GMAC_CONFIG2);
1355+
1356+ /* disable TX/RX and disable internal loop back */
1357+ config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1358+
1359+ config0.bits.max_len = 2;
1360+
1361+ gmac->flow_control_enable = 0;
1362+
1363+ config0.bits.tx_fc_en = 0; /* disable tx flow control */
1364+ config0.bits.rx_fc_en = 0; /* disable rx flow control */
1365+ config0.bits.dis_rx = 1; /* disable rx */
1366+ config0.bits.dis_tx = 1; /* disable tx */
1367+ config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
1368+ config0.bits.rx_err_detect = 1;
1369+ config0.bits.rgmii_en = 0;
1370+ config0.bits.rgmm_edge = 1;
1371+ config0.bits.rxc_inv = 0;
1372+ config0.bits.ipv4_rx_chksum = 1; /* enable H/W to check ip checksum */
1373+ config0.bits.ipv6_rx_chksum = 1; /* enable H/W to check ip checksum */
1374+ config0.bits.port0_chk_hwq = 1;
1375+ config0.bits.port1_chk_hwq = 1;
1376+ config0.bits.port0_chk_toeq = 1;
1377+ config0.bits.port1_chk_toeq = 1;
1378+ config0.bits.port0_chk_classq = 1;
1379+ config0.bits.port1_chk_classq = 1;
1380+
1381+ __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1382+
1383+ hw_weigh.bits32 = 0;
1384+ hw_weigh.bits.hw_tq3 = 1;
1385+ hw_weigh.bits.hw_tq2 = 1;
1386+ hw_weigh.bits.hw_tq1 = 1;
1387+ hw_weigh.bits.hw_tq0 = 1;
1388+ __raw_writel(hw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_0_REG);
1389+
1390+ sw_weigh.bits32 = 0;
1391+ sw_weigh.bits.sw_tq5 = 1;
1392+ sw_weigh.bits.sw_tq4 = 1;
1393+ sw_weigh.bits.sw_tq3 = 1;
1394+ sw_weigh.bits.sw_tq2 = 1;
1395+ sw_weigh.bits.sw_tq1 = 1;
1396+ sw_weigh.bits.sw_tq0 = 1;
1397+ __raw_writel(sw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_1_REG);
1398+
1399+ /* set interface type */
1400+ status.bits32 = __raw_readl(dev->base_addr + GMAC_STATUS);
1401+
1402+ switch (gmac->phydev->interface) {
1403+ case PHY_INTERFACE_MODE_MII:
1404+ status.bits.mii_rmii = GMAC_PHY_MII;
1405+ break;
1406+ case PHY_INTERFACE_MODE_GMII:
1407+ status.bits.mii_rmii = GMAC_PHY_GMII;
1408+ break;
1409+ case PHY_INTERFACE_MODE_RGMII:
1410+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
1411+ break;
1412+ default:
1413+ dev_err(&dev->dev, "Unsupported MII interface\n");
1414+ return;
1415+ }
1416+
1417+ __raw_writel(status.bits32, dev->base_addr + GMAC_STATUS);
1418+}
1419+
1420+static void toe_init_gmac(struct net_device *dev)
1421+{
1422+ struct gmac_private *gmac = netdev_priv(dev);
1423+ struct toe_private *toe = dev->ml_priv;
1424+ u32 data;
1425+
1426+ /* GMAC initialization */
1427+ toe_gmac_init_chip(dev);
1428+
1429+ /* -----------------------------------------------------------
1430+ Enable GMAC interrupt & disable loopback
1431+ Notes:
1432+ GMACx init routine (for eCOS) or open routine (for Linux)
1433+ enable the interrupt bits only which are selected for him.
1434+ --------------------------------------------------------------*/
1435+
1436+ /* Enable Interrupt Bits */
1437+ if (gmac->port_id == 0) {
1438+ gmac->intr0_selected = GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |
1439+ GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |
1440+ GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
1441+ GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
1442+ GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
1443+ GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
1444+ GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
1445+ GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
1446+
1447+#ifdef GMAX_TX_INTR_DISABLED
1448+ gmac->intr0_enabled = 0;
1449+#else
1450+ gmac->intr0_enabled = GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
1451+#endif
1452+
1453+ gmac->intr1_selected = TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
1454+ GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
1455+ GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
1456+ DEFAULT_Q0_INT_BIT;
1457+ gmac->intr1_enabled = DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
1458+ gmac->intr2_selected = 0xffffffff; /* TOE Queue 32-63 FUUL Intr */
1459+ gmac->intr2_enabled = 0xffffffff;
1460+ gmac->intr3_selected = 0xffffffff; /* TOE Queue 0-31 FUUL Intr */
1461+ gmac->intr3_enabled = 0xffffffff;
1462+ gmac->intr4_selected = GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
1463+ HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
1464+ gmac->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
1465+
1466+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) & ~gmac->intr0_selected;
1467+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1468+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) & ~gmac->intr1_selected;
1469+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1470+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) & ~gmac->intr2_selected;
1471+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1472+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) & ~gmac->intr3_selected;
1473+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1474+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) & ~gmac->intr4_selected;
1475+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1476+ } else {
1477+ gmac->intr0_selected = GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |
1478+ GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT |
1479+ GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
1480+ GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
1481+ GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
1482+ GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
1483+ GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
1484+ GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
1485+#ifdef GMAX_TX_INTR_DISABLED
1486+ gmac->intr0_enabled = 0;
1487+#else
1488+ gmac->intr0_enabled = GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
1489+#endif
1490+
1491+ gmac->intr1_selected = DEFAULT_Q1_INT_BIT;
1492+ gmac->intr1_enabled = DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
1493+ gmac->intr2_selected = 0; /* TOE Queue 32-63 FUUL Intr */
1494+ gmac->intr2_enabled = 0;
1495+ gmac->intr3_selected = 0; /* TOE Queue 0-31 FUUL Intr */
1496+ gmac->intr3_enabled = 0;
1497+ gmac->intr4_selected = GMAC1_INT_BITS;
1498+ gmac->intr4_enabled = GMAC1_INT_BITS;
1499+
1500+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) | gmac->intr0_selected;
1501+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1502+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) | gmac->intr1_selected;
1503+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1504+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) | gmac->intr2_selected;
1505+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1506+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) | gmac->intr3_selected;
1507+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1508+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) | gmac->intr4_selected;
1509+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1510+ }
1511+
1512+ /* enable only selected bits */
1513+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_0_REG,
1514+ gmac->intr0_enabled, gmac->intr0_selected);
1515+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_1_REG,
1516+ gmac->intr1_enabled, gmac->intr1_selected);
1517+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_2_REG,
1518+ gmac->intr2_enabled, gmac->intr2_selected);
1519+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_3_REG,
1520+ gmac->intr3_enabled, gmac->intr3_selected);
1521+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_4_REG,
1522+ gmac->intr4_enabled, gmac->intr4_selected);
1523+
1524+ /* start DMA process */
1525+ toe_gmac_hw_start(gmac);
1526+}
1527+
1528+static void toe_gmac_enable_tx_rx(struct net_device *dev)
1529+{
1530+ GMAC_CONFIG0_T config0;
1531+
1532+ /* enable TX/RX */
1533+ config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1534+ config0.bits.dis_rx = 0; /* enable rx */
1535+ config0.bits.dis_tx = 0; /* enable tx */
1536+ __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1537+}
1538+
1539+static void toe_gmac_disable_tx_rx(struct net_device *dev)
1540+{
1541+ GMAC_CONFIG0_T config0;
1542+
1543+ /* enable TX/RX */
1544+ config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1545+ config0.bits.dis_rx = 1; /* disable rx */
1546+ config0.bits.dis_tx = 1; /* disable tx */
1547+ __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1548+}
1549+
1550+static void toe_gmac_tx_complete(struct net_device *dev, unsigned int tx_qid)
1551+{
1552+ struct gmac_private *gmac = netdev_priv(dev);
1553+ struct toe_private *toe = dev->ml_priv;
1554+ GMAC_TXDESC_T *curr_desc;
1555+ GMAC_TXDESC_0_T word0;
1556+ GMAC_TXDESC_1_T word1;
1557+ unsigned int desc_count;
1558+ GMAC_SWTXQ_T *swtxq;
1559+ DMA_RWPTR_T rwptr;
1560+
1561+ /* get tx H/W completed descriptor virtual address */
1562+ /* check tx status and accumulate tx statistics */
1563+ swtxq = &gmac->swtxq[tx_qid];
1564+ for (;;) {
1565+ rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
1566+ if (rwptr.bits.rptr == swtxq->finished_idx)
1567+ break;
1568+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
1569+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1570+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1571+ sizeof(GMAC_TXDESC_T),
1572+ DMA_FROM_DEVICE);
1573+ word0.bits32 = curr_desc->word0.bits32;
1574+ word1.bits32 = curr_desc->word1.bits32;
1575+
1576+ if (word0.bits.status_tx_ok) {
1577+ dev->stats.tx_bytes += word1.bits.byte_count;
1578+ desc_count = word0.bits.desc_count;
1579+ if (desc_count == 0) {
1580+ dev_err(&dev->dev, "%s::Desc 0x%x = 0x%x, desc_count=%d\n", __func__, (u32)curr_desc, word0.bits32, desc_count);
1581+ BUG();
1582+ }
1583+ while (--desc_count) {
1584+ word0.bits.status_tx_ok = 0;
1585+ curr_desc->word0.bits32 = word0.bits32;
1586+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1587+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1588+ sizeof(GMAC_TXDESC_T),
1589+ DMA_TO_DEVICE);
1590+ swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
1591+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
1592+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1593+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1594+ sizeof(GMAC_TXDESC_T),
1595+ DMA_FROM_DEVICE);
1596+ word0.bits32 = curr_desc->word0.bits32;
1597+ }
1598+
1599+ word0.bits.status_tx_ok = 0;
1600+ dev_kfree_skb_any(swtxq->tx_skb[swtxq->finished_idx]);
1601+ swtxq->tx_skb[swtxq->finished_idx] = NULL;
1602+
1603+ curr_desc->word0.bits32 = word0.bits32;
1604+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1605+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1606+ sizeof(GMAC_TXDESC_T),
1607+ DMA_TO_DEVICE);
1608+ dev->stats.tx_packets++;
1609+ swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
1610+ } else {
1611+ break;
1612+ }
1613+ }
1614+
1615+ if (netif_queue_stopped(dev))
1616+ netif_wake_queue(dev);
1617+}
1618+
1619+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
1620+{
1621+ struct gmac_private *gmac = netdev_priv(dev);
1622+ struct toe_private *toe = dev->ml_priv;
1623+ DMA_RWPTR_T rwptr;
1624+ GMAC_TXDESC_T *curr_desc;
1625+ int snd_pages = skb_shinfo(skb)->nr_frags + 1; /* get number of descriptor */
1626+ int frag_id = 0;
1627+ int len, total_len = skb->len;
1628+ struct net_device_stats *isPtr = &dev->stats;
1629+ unsigned int free_desc;
1630+ GMAC_SWTXQ_T *swtxq;
1631+ register unsigned long word0, word1, word2, word3;
1632+ unsigned short wptr, rptr;
1633+
1634+#ifdef GMAC_LEN_1_2_ISSUE
1635+ int total_pages;
1636+ total_pages = snd_pages;
1637+#endif
1638+
1639+ if (skb->len >= 0x10000) {
1640+ isPtr->tx_dropped++;
1641+ dev_err(&dev->dev, "%s::skb->len %d >= 64K\n", __func__, skb->len);
1642+ netif_stop_queue(dev);
1643+ return 1;
1644+ }
1645+
1646+#ifdef GMAC_USE_TXQ0
1647+ #define tx_qid 0
1648+#endif
1649+
1650+ swtxq = &gmac->swtxq[tx_qid];
1651+
1652+ rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
1653+ wptr = rwptr.bits.wptr;
1654+ rptr = rwptr.bits.rptr;
1655+
1656+ /*
1657+ * check finished desc or empty BD
1658+ * cannot check by read ptr of RW PTR register,
1659+ * because the HW complete to send but the SW may NOT handle it
1660+ */
1661+#ifdef GMAX_TX_INTR_DISABLED
1662+ toe_gmac_tx_complete(dev, tx_qid);
1663+#endif
1664+ if (wptr >= swtxq->finished_idx)
1665+ free_desc = TOE_GMAC_SWTXQ_DESC_NUM - wptr + swtxq->finished_idx;
1666+ else
1667+ free_desc = swtxq->finished_idx - wptr;
1668+
1669+ if (free_desc < snd_pages) {
1670+ isPtr->tx_dropped++;
1671+ netif_stop_queue(dev);
1672+ return 1;
1673+ }
1674+
1675+ while (snd_pages) {
1676+ char *pkt_datap;
1677+
1678+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
1679+ if (frag_id == 0) {
1680+ len = skb_headlen(skb);
1681+ pkt_datap = dma_map_single(toe->dev, skb->data, len, DMA_TO_DEVICE);
1682+ } else {
1683+ skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_id - 1];
1684+ len = frag->size;
1685+ pkt_datap = dma_map_page(toe->dev, frag->page, frag->page_offset, len, DMA_TO_DEVICE);
1686+ }
1687+
1688+ /* set TX descriptor */
1689+ word0 = len;
1690+ word3 = (dev->mtu + 14) | EOFIE_BIT;
1691+
1692+#ifdef DO_HW_CHKSUM
1693+ if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
1694+ word1 = total_len |
1695+ TSS_IP_CHKSUM_BIT |
1696+ TSS_IPV6_ENABLE_BIT |
1697+ TSS_MTU_ENABLE_BIT;
1698+ else
1699+ word1 = total_len |
1700+ TSS_UDP_CHKSUM_BIT |
1701+ TSS_TCP_CHKSUM_BIT |
1702+ TSS_IP_CHKSUM_BIT |
1703+ TSS_IPV6_ENABLE_BIT |
1704+ TSS_MTU_ENABLE_BIT;
1705+#else
1706+ word1 = total_len | TSS_MTU_ENABLE_BIT;
1707+#endif
1708+ word2 = pkt_datap;
1709+
1710+ if (frag_id == 0)
1711+ word3 |= SOF_BIT;
1712+
1713+ if (snd_pages == 1) {
1714+ word3 |= EOF_BIT;
1715+ swtxq->tx_skb[wptr] = skb;
1716+ } else
1717+ swtxq->tx_skb[wptr] = NULL;
1718+
1719+#ifdef GMAC_LEN_1_2_ISSUE
1720+ if ((total_pages != snd_pages) && (len == 1 || len == 2) && ((u32)pkt_datap & 0x03)) {
1721+ memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
1722+ pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
1723+ word2 = (unsigned long)__pa(pkt_datap);
1724+ _debug_prefetch_cnt++;
1725+ if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
1726+ _debug_prefetch_cnt = 0;
1727+ }
1728+#endif
1729+ curr_desc->word0.bits32 = word0;
1730+ curr_desc->word1.bits32 = word1;
1731+ curr_desc->word2.bits32 = word2;
1732+ curr_desc->word3.bits32 = word3;
1733+ free_desc--;
1734+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1735+ wptr * sizeof(GMAC_TXDESC_T),
1736+ sizeof(GMAC_TXDESC_T),
1737+ DMA_TO_DEVICE);
1738+ wptr = RWPTR_ADVANCE_ONE(wptr, TOE_GMAC_SWTXQ_DESC_NUM);
1739+ frag_id++;
1740+ snd_pages--;
1741+ }
1742+
1743+ SET_WPTR(swtxq->rwptr_reg, wptr);
1744+ dev->trans_start = jiffies;
1745+
1746+ return 0;
1747+}
1748+
1749+static void __gmac_set_mac_address(struct net_device *dev)
1750+{
1751+ unsigned int reg_val;
1752+
1753+ reg_val = dev->dev_addr[0] + (dev->dev_addr[1] << 8) +
1754+ (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1755+ __raw_writel(reg_val, dev->base_addr + GMAC_STA_ADD0);
1756+ reg_val = (__raw_readl(dev->base_addr + GMAC_STA_ADD1) & 0xFFFF0000) +
1757+ dev->dev_addr[4] + (dev->dev_addr[5] << 8);
1758+ __raw_writel(reg_val, dev->base_addr + GMAC_STA_ADD1);
1759+}
1760+
1761+static int gmac_set_mac_address(struct net_device *dev, void *addr)
1762+{
1763+ struct sockaddr *sa = addr;
1764+
1765+ memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
1766+
1767+ __gmac_set_mac_address(dev);
1768+
1769+ return 0;
1770+}
1771+
1772+static void gmac_get_mac_address(struct net_device *dev)
1773+{
1774+ unsigned int reg_val;
1775+
1776+ reg_val = __raw_readl(dev->base_addr + GMAC_STA_ADD0);
1777+ dev->dev_addr[0] = reg_val & 0xFF;
1778+ dev->dev_addr[1] = (reg_val >> 8) & 0xFF;
1779+ dev->dev_addr[2] = (reg_val >> 16) & 0xFF;
1780+ dev->dev_addr[3] = (reg_val >> 24) & 0xFF;
1781+ reg_val = __raw_readl(dev->base_addr + GMAC_STA_ADD1);
1782+ dev->dev_addr[4] = reg_val & 0xFF;
1783+ dev->dev_addr[5] = (reg_val >> 8) & 0xFF;
1784+
1785+ if (!is_valid_ether_addr(dev->dev_addr)) {
1786+ random_ether_addr(dev->dev_addr);
1787+ __gmac_set_mac_address(dev);
1788+ }
1789+}
1790+
1791+struct net_device_stats *gmac_get_stats(struct net_device *dev)
1792+{
1793+ if (netif_running(dev)) {
1794+ unsigned short multicast;
1795+
1796+ multicast = __raw_readw(dev->base_addr + GMAC_IN_MCAST) +
1797+ __raw_readw(dev->base_addr + GMAC_IN_BCAST);
1798+
1799+ dev->stats.rx_dropped += __raw_readw(dev->base_addr + GMAC_IN_DISCARDS);
1800+ dev->stats.rx_errors += __raw_readw(dev->base_addr + GMAC_IN_ERRORS);
1801+ dev->stats.rx_packets += __raw_readl(dev->base_addr + GMAC_IN_MAC1) + multicast;
1802+ dev->stats.multicast += multicast;
1803+ }
1804+
1805+ return &dev->stats;
1806+}
1807+
1808+/* TODO: If possible use crc32 from kernel lib */
1809+static unsigned const ethernet_polynomial = 0x04c11db7U;
1810+static unsigned int ether_crc(int length, unsigned char *data)
1811+{
1812+ int crc = -1;
1813+ unsigned int i;
1814+ unsigned int crc_val = 0;
1815+
1816+ while (--length >= 0) {
1817+ unsigned char current_octet = *data++;
1818+ int bit;
1819+ for (bit = 0; bit < 8; bit++, current_octet >>= 1)
1820+ crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
1821+ ethernet_polynomial : 0);
1822+ }
1823+ crc = ~crc;
1824+ for (i = 0; i < 32; i++)
1825+ crc_val = crc_val + (((crc << i) & 0x80000000) >> (31 - i));
1826+
1827+ return crc_val;
1828+}
1829+
1830+/*----------------------------------------------------------------------
1831+* toe_gmac_fill_free_q
1832+* allocate buffers for free queue.
1833+*----------------------------------------------------------------------*/
1834+static void toe_gmac_fill_free_q(struct toe_private *toe)
1835+{
1836+ struct sk_buff *skb;
1837+ DMA_RWPTR_T fq_rwptr;
1838+ GMAC_RXDESC_T *fq_desc;
1839+ unsigned long flags;
1840+
1841+ spin_lock_irqsave(&toe->freeq_lock, flags);
1842+ fq_rwptr.bits32 = __raw_readl(toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
1843+ while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
1844+ TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
1845+ skb = dev_alloc_skb(SW_RX_BUF_SIZE);
1846+ if (skb == NULL) {
1847+ dev_err(toe->dev, "%s::skb allocation fail\n", __func__);
1848+ break;
1849+ }
1850+ REG32(skb->data) = (unsigned int)skb;
1851+ skb_reserve(skb, SKB_RESERVE_BYTES);
1852+ fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
1853+ TOE_SW_FREEQ_DESC_NUM);
1854+ fq_desc = (GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
1855+ fq_desc->word2.buf_adr = dma_map_single(toe->dev, skb->data,
1856+ SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
1857+ DMA_FROM_DEVICE);
1858+ dma_sync_single_range_for_device(toe->dev,
1859+ toe->sw_freeq_desc_base_dma,
1860+ fq_rwptr.bits.wptr * sizeof(GMAC_RXDESC_T),
1861+ sizeof(GMAC_RXDESC_T),
1862+ DMA_TO_DEVICE);
1863+ SET_WPTR(toe->global_base + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
1864+ }
1865+ spin_unlock_irqrestore(&toe->freeq_lock, flags);
1866+}
1867+
1868+static void fill_free_q_worker(struct work_struct *work)
1869+{
1870+ struct toe_private *toe = container_of(work, struct toe_private, freq_work);
1871+
1872+ toe_gmac_fill_free_q(toe);
1873+}
1874+
1875+/*----------------------------------------------------------------------
1876+* toe_gmac_handle_default_rxq
1877+* (1) Get rx Buffer for default Rx queue
1878+* (2) notify or call upper-routine to handle it
1879+* (3) get a new buffer and insert it into SW free queue
1880+* (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
1881+*----------------------------------------------------------------------*/
1882+static void toe_gmac_handle_default_rxq(struct net_device *dev)
1883+{
1884+ struct gmac_private *gmac = netdev_priv(dev);
1885+ struct toe_private *toe = dev->ml_priv;
1886+ GMAC_RXDESC_T *curr_desc;
1887+ struct sk_buff *skb;
1888+ DMA_RWPTR_T rwptr;
1889+ unsigned int pkt_size;
1890+ int max_cnt;
1891+ unsigned int desc_count;
1892+ unsigned int chksum_status, rx_status;
1893+ struct net_device_stats *isPtr = &dev->stats;
1894+
1895+ rwptr.bits32 = __raw_readl(&gmac->default_qhdr->word1);
1896+ max_cnt = DEFAULT_RXQ_MAX_CNT;
1897+ while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr) {
1898+ curr_desc = (GMAC_RXDESC_T *)gmac->default_desc_base + rwptr.bits.rptr;
1899+ dma_sync_single_range_for_device(toe->dev,
1900+ gmac->default_desc_base_dma,
1901+ rwptr.bits.rptr * sizeof(GMAC_RXDESC_T),
1902+ sizeof(GMAC_RXDESC_T),
1903+ DMA_FROM_DEVICE);
1904+ rx_status = curr_desc->word0.bits.status;
1905+ chksum_status = curr_desc->word0.bits.chksum_status;
1906+ pkt_size = curr_desc->word1.bits.byte_count; /* total byte count in a frame */
1907+ desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
1908+ skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1909+
1910+ if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
1911+ || (pkt_size < 60) || (chksum_status & 0x4) || rx_status) {
1912+ if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
1913+ dev_err(&dev->dev, "%s::derr\n", __func__);
1914+ if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
1915+ dev_err(&dev->dev, "%s::perr\n", __func__);
1916+ if (rx_status && (rx_status == 4 || rx_status == 7))
1917+ isPtr->rx_crc_errors++;
1918+
1919+ dev_kfree_skb_irq(skb);
1920+ goto bad_frame;
1921+ }
1922+
1923+ if (curr_desc->word0.bits.drop)
1924+ dev_warn(&dev->dev, "%s::Drop\n", __func__);
1925+
1926+ /* get frame information from the first descriptor of the frame */
1927+ skb_reserve(skb, RX_INSERT_BYTES); /* 16 byte align the IP fields. */
1928+ skb_put(skb, pkt_size);
1929+ skb->dev = dev;
1930+ skb->protocol = eth_type_trans(skb, dev);
1931+ if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK || chksum_status == RX_CHKSUM_IP_OK_ONLY)
1932+ skb->ip_summed = CHECKSUM_UNNECESSARY;
1933+
1934+ netif_rx(skb); /* socket rx */
1935+ dev->last_rx = jiffies;
1936+
1937+ isPtr->rx_bytes += pkt_size;
1938+
1939+bad_frame:
1940+ /* advance one for Rx default Q 0/1 */
1941+ rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, TOE_DEFAULT_Q_DESC_NUM);
1942+ SET_RPTR(&gmac->default_qhdr->word1, rwptr.bits.rptr);
1943+ }
1944+
1945+ schedule_work(&toe->freq_work);
1946+}
1947+
1948+static irqreturn_t toe_gmac_interrupt(int irq, void *dev_instance)
1949+{
1950+ struct net_device *dev = dev_instance;
1951+ struct gmac_private *gmac = netdev_priv(dev);
1952+ struct toe_private *toe = dev->ml_priv;
1953+ unsigned int status0;
1954+ unsigned int status1;
1955+ unsigned int status2;
1956+ unsigned int status3;
1957+ unsigned int status4;
1958+ int handled = 0;
1959+
1960+ /* read Interrupt status */
1961+ status0 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
1962+ status1 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
1963+ status2 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
1964+ status3 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
1965+ status4 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
1966+
1967+ /* clear interrupts */
1968+ if (status0)
1969+ __raw_writel(status0, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
1970+ if (status1)
1971+ __raw_writel(status1, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
1972+ if (status2)
1973+ __raw_writel(status2, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
1974+ if (status3)
1975+ __raw_writel(status3, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
1976+ if (status4)
1977+ __raw_writel(status4, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
1978+
1979+ /* handle freeq interrupt first */
1980+ if (status4 & gmac->intr4_enabled) {
1981+ if ((status4 & SWFQ_EMPTY_INT_BIT) && (gmac->intr4_enabled & SWFQ_EMPTY_INT_BIT)) {
1982+ toe_gmac_fill_free_q(toe);
1983+ handled = 1;
1984+ }
1985+ }
1986+
1987+ /* Interrupt Status 1 */
1988+ if (status1 & gmac->intr1_enabled) {
1989+ /*
1990+ * Handle GMAC 0/1 HW Tx queue 0-3 EOF events
1991+ * Only count
1992+ * TOE, Classification, and default queues interrupts are handled by ISR
1993+ * because they should pass packets to upper layer
1994+ */
1995+ if (gmac->port_id == 0) {
1996+ if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q0_INT_BIT)) {
1997+ toe_gmac_handle_default_rxq(dev);
1998+ handled = 1;
1999+ }
2000+ } else if (gmac->port_id == 1) {
2001+ if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q1_INT_BIT)) {
2002+ toe_gmac_handle_default_rxq(dev);
2003+ handled = 1;
2004+ }
2005+ }
2006+ }
2007+
2008+ /* Interrupt Status 0 */
2009+ if (status0 & gmac->intr0_enabled) {
2010+#ifndef GMAX_TX_INTR_DISABLED
2011+ if (gmac->port_id == 1 && netif_running(dev) &&
2012+ (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
2013+ ||
2014+ ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT)))) {
2015+ toe_gmac_tx_complete(dev, 0);
2016+ handled = 1;
2017+ }
2018+
2019+ if (gmac->port_id == 0 && netif_running(dev) &&
2020+ (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
2021+ ||
2022+ ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT)))) {
2023+ toe_gmac_tx_complete(dev, 0);
2024+ handled = 1;
2025+ }
2026+#endif
2027+ }
2028+
2029+ return IRQ_RETVAL(handled);
2030+}
2031+
2032+static int gmac_open(struct net_device *dev)
2033+{
2034+ struct gmac_private *gmac = netdev_priv(dev);
2035+ int retval;
2036+
2037+ /* hook ISR */
2038+ retval = request_irq(dev->irq, toe_gmac_interrupt, 0, dev->name, dev);
2039+ if (retval)
2040+ return retval;
2041+
2042+ toe_init_gmac(dev);
2043+
2044+ netif_carrier_off(dev);
2045+ phy_start(gmac->phydev);
2046+
2047+ netif_start_queue(dev);
2048+
2049+ return 0;
2050+}
2051+
2052+static int gmac_close(struct net_device *dev)
2053+{
2054+ struct gmac_private *gmac = netdev_priv(dev);
2055+
2056+ netif_stop_queue(dev);
2057+ mdelay(20);
2058+
2059+ if (gmac->phydev)
2060+ phy_stop(gmac->phydev);
2061+
2062+ /* stop tx/rx packet */
2063+ toe_gmac_disable_tx_rx(dev);
2064+ mdelay(20);
2065+
2066+ /* stop the chip's Tx and Rx DMA processes */
2067+ toe_gmac_hw_stop(gmac);
2068+
2069+ disable_irq(dev->irq);
2070+ free_irq(dev->irq, dev);
2071+
2072+ return 0;
2073+}
2074+
2075+static void gmac_get_phy_status(struct net_device *dev)
2076+{
2077+ struct gmac_private *gmac = netdev_priv(dev);
2078+ GMAC_CONFIG0_T config0;
2079+ GMAC_STATUS_T status, old_status;
2080+ struct phy_device *phydev = gmac->phydev;
2081+
2082+ old_status.bits32 = status.bits32 = __raw_readl(dev->base_addr + GMAC_STATUS);
2083+
2084+ status.bits.link = phydev->link;
2085+ status.bits.duplex = phydev->duplex;
2086+
2087+ switch (phydev->speed) {
2088+ case 1000:
2089+ status.bits.speed = GMAC_SPEED_1000;
2090+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2091+ status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
2092+ break;
2093+ case 100:
2094+ status.bits.speed = GMAC_SPEED_100;
2095+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2096+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
2097+ break;
2098+ case 10:
2099+ status.bits.speed = GMAC_SPEED_10;
2100+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2101+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
2102+ break;
2103+ default:
2104+ dev_warn(&dev->dev, "Not supported PHY speed (%d)\n", phydev->speed);
2105+ }
2106+
2107+ if (phydev->pause) {
2108+ if (gmac->flow_control_enable == 0) {
2109+ config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
2110+ config0.bits.tx_fc_en = 1; /* enable tx flow control */
2111+ config0.bits.rx_fc_en = 1; /* enable rx flow control */
2112+ __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
2113+ dev_info(&dev->dev, "MII flow control enabled\n");
2114+ }
2115+ gmac->flow_control_enable = 1;
2116+ } else {
2117+ if (gmac->flow_control_enable == 1) {
2118+ config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
2119+ config0.bits.tx_fc_en = 0; /* disable tx flow control */
2120+ config0.bits.rx_fc_en = 0; /* disable rx flow control */
2121+ __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
2122+ dev_info(&dev->dev, "MII flow control disabled\n");
2123+ }
2124+ gmac->flow_control_enable = 0;
2125+ }
2126+
2127+ if (old_status.bits32 != status.bits32) {
2128+ toe_gmac_disable_tx_rx(dev);
2129+ phy_print_status(phydev);
2130+ mdelay(10); /* let GMAC consume packet */
2131+ __raw_writel(status.bits32, dev->base_addr + GMAC_STATUS);
2132+ if (status.bits.link)
2133+ toe_gmac_enable_tx_rx(dev);
2134+ }
2135+}
2136+
2137+static void gmac_set_rx_mode(struct net_device *dev)
2138+{
2139+ GMAC_RX_FLTR_T filter;
2140+ unsigned int mc_filter[2]; /* Multicast hash filter */
2141+ int bit_nr;
2142+ unsigned int i;
2143+
2144+ filter.bits32 = 0;
2145+ filter.bits.error = 0;
2146+ if (dev->flags & IFF_PROMISC) {
2147+ filter.bits.error = 1;
2148+ filter.bits.promiscuous = 1;
2149+ filter.bits.broadcast = 1;
2150+ filter.bits.multicast = 1;
2151+ filter.bits.unicast = 1;
2152+ mc_filter[1] = mc_filter[0] = 0xffffffff;
2153+ } else if (dev->flags & IFF_ALLMULTI) {
2154+ filter.bits.broadcast = 1;
2155+ filter.bits.multicast = 1;
2156+ filter.bits.unicast = 1;
2157+ mc_filter[1] = mc_filter[0] = 0xffffffff;
2158+ } else {
2159+ struct netdev_hw_addr *ha;
2160+
2161+ filter.bits.broadcast = 1;
2162+ filter.bits.multicast = 1;
2163+ filter.bits.unicast = 1;
2164+ mc_filter[1] = mc_filter[0] = 0;
2165+ netdev_for_each_mc_addr(ha, dev) {
2166+ bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
2167+ if (bit_nr <= 32)
2168+ mc_filter[0] = mc_filter[0] | (1 << bit_nr);
2169+ else
2170+ mc_filter[1] = mc_filter[1] | (1 << (bit_nr - 32));
2171+ }
2172+ }
2173+ __raw_writel(filter.bits32, dev->base_addr + GMAC_RX_FLTR);
2174+ __raw_writel(mc_filter[0], dev->base_addr + GMAC_MCAST_FIL0);
2175+ __raw_writel(mc_filter[1], dev->base_addr + GMAC_MCAST_FIL1);
2176+}
2177+
2178+static void gmac_tx_timeout(struct net_device *dev)
2179+{
2180+ if (!netif_queue_stopped(dev))
2181+ netif_wake_queue(dev);
2182+
2183+ dev_warn(&dev->dev, "TX timeout\n");
2184+}
2185+
2186+const static struct net_device_ops gemini_gmac_ops = {
2187+ .ndo_open = gmac_open,
2188+ .ndo_stop = gmac_close,
2189+ .ndo_start_xmit = gmac_start_xmit,
2190+ .ndo_get_stats = gmac_get_stats,
2191+ .ndo_set_multicast_list = gmac_set_rx_mode,
2192+ .ndo_set_mac_address = gmac_set_mac_address,
2193+ .ndo_tx_timeout = gmac_tx_timeout,
2194+};
2195+
2196+static void __init mac_init_drv(struct toe_private *toe)
2197+{
2198+ QUEUE_THRESHOLD_T threshold;
2199+ DMA_SKB_SIZE_T skb_size;
2200+
2201+ /* clear non TOE Queue Header Area */
2202+ memset(toe->global_base + TOE_NONTOE_QUE_HDR_BASE, 0,
2203+ NONTOE_Q_HDR_AREA_END - TOE_NONTOE_QUE_HDR_BASE);
2204+
2205+ /* clear TOE Queue Header Area */
2206+ memset(toe->global_base + TOE_TOE_QUE_HDR_BASE, 0,
2207+ TOE_Q_HDR_AREA_END - TOE_TOE_QUE_HDR_BASE);
2208+
2209+ /* Write GLOBAL_QUEUE_THRESHOLD_REG */
2210+ threshold.bits32 = 0;
2211+ threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
2212+ TOE_SW_FREEQ_DESC_NUM / 2;
2213+ threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256 / 4 :
2214+ TOE_HW_FREEQ_DESC_NUM / 4;
2215+ threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256 / 4 :
2216+ TOE_TOE_DESC_NUM / 4;
2217+ threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256 / 4 :
2218+ TOE_INTR_DESC_NUM / 4;
2219+ __raw_writel(threshold.bits32, toe->global_base + GLOBAL_QUEUE_THRESHOLD_REG);
2220+
2221+ /* Init skb size */
2222+ skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
2223+ skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
2224+ __raw_writel(skb_size.bits32, toe->global_base + GLOBAL_DMA_SKB_SIZE_REG);
2225+
2226+ toe_init_free_queue(toe);
2227+ toe_init_interrupt_config(toe);
2228+}
2229+
2230+static int __init gmac_init_eth(struct platform_device *pdev, unsigned int num)
2231+{
2232+ struct gmac_private *gmac;
2233+ struct net_device *dev;
2234+ struct toe_private *toe = platform_get_drvdata(pdev);
2235+ struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
2236+
2237+ if (!pdata->bus_id[num])
2238+ return 0;
2239+
2240+ dev = alloc_etherdev(sizeof(*gmac));
2241+ if (dev == NULL) {
2242+ dev_err(&pdev->dev, "Can't allocate ethernet device #%d\n", num);
2243+ return -ENOMEM;
2244+ }
2245+
2246+ gmac = netdev_priv(dev);
2247+ dev->ml_priv = toe;
2248+ toe->net_dev[num] = dev;
2249+
2250+ gmac->dma_base_addr = toe->global_base + TOE_GMAC_DMA_BASE(num);
2251+ gmac->port_id = num;
2252+
2253+ dev->base_addr = toe->global_base + TOE_GMAC_BASE(num);
2254+ dev->irq = platform_get_irq(pdev, num);
2255+ dev->netdev_ops = &gemini_gmac_ops;
2256+ dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
2257+ dev->tx_queue_len = TOE_GMAC_SWTXQ_DESC_NUM;
2258+
2259+#ifdef DO_HW_CHKSUM
2260+ dev->features = NETIF_F_SG | NETIF_F_HW_CSUM;
2261+#ifdef ENABLE_TSO
2262+ dev->features |= NETIF_F_TSO;
2263+#endif
2264+#endif
2265+
2266+ toe_init_swtx_queue(dev);
2267+ toe_init_default_queue(dev);
2268+
2269+ gmac_get_mac_address(dev);
2270+
2271+ /* TODO: Do we need this? */
2272+ __raw_writel(0x55aa55aa, dev->base_addr + GMAC_STA_ADD2);
2273+
2274+ if (register_netdev(dev))
2275+ return -1;
2276+
2277+ gmac->phydev = phy_connect(dev, pdata->bus_id[num], &gmac_get_phy_status, 0,
2278+ pdata->interface[num]);
2279+ if (IS_ERR(gmac->phydev))
2280+ return PTR_ERR(gmac->phydev);
2281+
2282+ gmac->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause;
2283+ gmac->phydev->advertising = gmac->phydev->supported;
2284+
2285+ return 0;
2286+}
2287+
2288+static int __init gmac_probe(struct platform_device *pdev)
2289+{
2290+ struct resource *res;
2291+ struct toe_private *toe;
2292+ int retval;
2293+
2294+ if (!pdev->dev.platform_data)
2295+ return -EINVAL;
2296+
2297+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2298+ if (!res) {
2299+ dev_err(&pdev->dev, "can't get device resources\n");
2300+ return -ENODEV;
2301+ }
2302+
2303+ toe = kzalloc(sizeof(struct toe_private), GFP_KERNEL);
2304+ if (!toe)
2305+ return -ENOMEM;
2306+
2307+ toe->dev = &pdev->dev;
2308+
2309+ toe->global_base = ioremap(res->start, resource_size(res));
2310+ if (!toe->global_base) {
2311+ dev_err(toe->dev, "ioremap failed\n");
2312+ retval = -EIO;
2313+ goto err_data;
2314+ }
2315+
2316+ platform_set_drvdata(pdev, toe);
2317+
2318+ mac_init_drv(toe);
2319+
2320+ INIT_WORK(&toe->freq_work, fill_free_q_worker);
2321+ spin_lock_init(&toe->freeq_lock);
2322+
2323+ retval = gmac_init_eth(pdev, GMAC_PORT0);
2324+ if (retval)
2325+ goto err_unmap;
2326+ retval = gmac_init_eth(pdev, GMAC_PORT1);
2327+ if (retval)
2328+ goto err_unmap;
2329+
2330+ dev_info(&pdev->dev, SL351x_DRIVER_NAME "\n");
2331+
2332+ return 0;
2333+
2334+err_unmap:
2335+ iounmap(toe->global_base);
2336+err_data:
2337+ kfree(toe);
2338+ return retval;
2339+}
2340+
2341+static int __exit gmac_remove(struct platform_device *pdev)
2342+{
2343+ struct toe_private *toe = platform_get_drvdata(pdev);
2344+ int i;
2345+
2346+ for (i = 0; i < 2; i++)
2347+ if (toe->net_dev[i]) {
2348+ unregister_netdev(toe->net_dev[i]);
2349+ kfree(toe->net_dev[i]);
2350+ }
2351+
2352+ iounmap(toe->global_base);
2353+
2354+ kfree(toe);
2355+
2356+ return 0;
2357+}
2358+
2359+static struct platform_driver gemini_gmac_driver = {
2360+ .probe = gmac_probe,
2361+ .remove = __exit_p(gmac_remove),
2362+
2363+ .driver = {
2364+ .name = "gemini-gmac",
2365+ .owner = THIS_MODULE,
2366+ },
2367+};
2368+
2369+static int __init gemini_gmac_init(void)
2370+{
2371+ return platform_driver_register(&gemini_gmac_driver);
2372+}
2373+
2374+static void __exit gemini_gmac_exit(void)
2375+{
2376+ platform_driver_unregister(&gemini_gmac_driver);
2377+}
2378+
2379+module_init(gemini_gmac_init);
2380+module_exit(gemini_gmac_exit);
2381+
2382+MODULE_AUTHOR("Paulius Zaleckas");
2383+MODULE_DESCRIPTION("Ethernet device driver for Gemini SoC");
2384+MODULE_LICENSE("GPL");
2385+MODULE_ALIAS("platform:gemini-gmac");
2386--- /dev/null
2387+++ b/drivers/net/gemini_negmac/gm_gmac.h
2388@@ -0,0 +1,1488 @@
2389+/*
2390+ * Register definitions for Gemini Ethernet device driver.
2391+ *
2392+ * Copyright (C) 2006, Storlink, Corp.
2393+ * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
2394+ *
2395+ * This program is free software; you can redistribute it and/or modify
2396+ * it under the terms of the GNU General Public License as published by
2397+ * the Free Software Foundation; either version 2 of the License, or
2398+ * (at your option) any later version.
2399+ */
2400+#ifndef _GMAC_SL351x_H
2401+#define _GMAC_SL351x_H
2402+#include <linux/skbuff.h>
2403+
2404+#define _PACKED_ __attribute__ ((aligned(1), packed))
2405+
2406+#ifndef BIT
2407+#define BIT(x) (1 << (x))
2408+#endif
2409+
2410+#define REG32(addr) (*(volatile unsigned long * const)(addr))
2411+
2412+/* Define frame size */
2413+#define GMAC_MAX_ETH_FRAME_SIZE 1514
2414+#define GMAC_TX_BUF_SIZE ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
2415+
2416+#define SW_RX_BUF_SIZE 1536
2417+#define HW_RX_BUF_SIZE 1536
2418+
2419+#define GMAC_DEV_TX_TIMEOUT (10*HZ)
2420+#define SKB_RESERVE_BYTES 16
2421+
2422+/*
2423+ * Base Registers
2424+ */
2425+#define TOE_NONTOE_QUE_HDR_BASE 0x2000
2426+#define TOE_TOE_QUE_HDR_BASE 0x3000
2427+#define TOE_V_BIT_BASE 0x4000
2428+#define TOE_A_BIT_BASE 0x6000
2429+#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x))
2430+#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x))
2431+
2432+/*
2433+ * Queue ID
2434+ */
2435+#define TOE_SW_FREE_QID 0x00
2436+#define TOE_HW_FREE_QID 0x01
2437+#define TOE_GMAC0_SW_TXQ0_QID 0x02
2438+#define TOE_GMAC0_SW_TXQ1_QID 0x03
2439+#define TOE_GMAC0_SW_TXQ2_QID 0x04
2440+#define TOE_GMAC0_SW_TXQ3_QID 0x05
2441+#define TOE_GMAC0_SW_TXQ4_QID 0x06
2442+#define TOE_GMAC0_SW_TXQ5_QID 0x07
2443+#define TOE_GMAC0_HW_TXQ0_QID 0x08
2444+#define TOE_GMAC0_HW_TXQ1_QID 0x09
2445+#define TOE_GMAC0_HW_TXQ2_QID 0x0A
2446+#define TOE_GMAC0_HW_TXQ3_QID 0x0B
2447+#define TOE_GMAC1_SW_TXQ0_QID 0x12
2448+#define TOE_GMAC1_SW_TXQ1_QID 0x13
2449+#define TOE_GMAC1_SW_TXQ2_QID 0x14
2450+#define TOE_GMAC1_SW_TXQ3_QID 0x15
2451+#define TOE_GMAC1_SW_TXQ4_QID 0x16
2452+#define TOE_GMAC1_SW_TXQ5_QID 0x17
2453+#define TOE_GMAC1_HW_TXQ0_QID 0x18
2454+#define TOE_GMAC1_HW_TXQ1_QID 0x19
2455+#define TOE_GMAC1_HW_TXQ2_QID 0x1A
2456+#define TOE_GMAC1_HW_TXQ3_QID 0x1B
2457+#define TOE_GMAC0_DEFAULT_QID 0x20
2458+#define TOE_GMAC1_DEFAULT_QID 0x21
2459+#define TOE_CLASSIFICATION_QID(x) (0x22 + x) // 0x22 ~ 0x2F
2460+#define TOE_TOE_QID(x) (0x40 + x) // 0x40 ~ 0x7F
2461+
2462+/*
2463+ * TOE DMA Queue Number should be 2^n, n = 6...12
2464+ * TOE DMA Queues are the following queue types:
2465+ * SW Free Queue, HW Free Queue,
2466+ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
2467+ * They have same descriptor numbers.
2468+ * The base address and descriptor number are configured at
2469+ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
2470+ */
2471+#define TOE_SW_FREEQ_DESC_POWER 8
2472+#define TOE_SW_FREEQ_DESC_NUM (1<<TOE_SW_FREEQ_DESC_POWER)
2473+#define TOE_HW_FREEQ_DESC_POWER 8
2474+#define TOE_HW_FREEQ_DESC_NUM (1<<TOE_HW_FREEQ_DESC_POWER)
2475+#define TOE_GMAC_SWTXQ_DESC_POWER 8
2476+#define TOE_GMAC_SWTXQ_DESC_NUM (1<<TOE_GMAC_SWTXQ_DESC_POWER)
2477+#define TOE_GMAC_HWTXQ_DESC_POWER 8
2478+#define TOE_GMAC_HWTXQ_DESC_NUM (1<<TOE_GMAC_HWTXQ_DESC_POWER)
2479+#define TOE_DEFAULT_Q_DESC_POWER 8
2480+#define TOE_DEFAULT_Q_DESC_NUM (1<<TOE_DEFAULT_Q_DESC_POWER)
2481+#define TOE_TOE_DESC_POWER 8
2482+#define TOE_TOE_DESC_NUM (1<<TOE_TOE_DESC_POWER)
2483+#define TOE_CLASS_DESC_POWER 8
2484+#define TOE_CLASS_DESC_NUM (1<<TOE_CLASS_DESC_POWER)
2485+#define TOE_INTR_DESC_POWER 8
2486+#define TOE_INTR_DESC_NUM (1<<TOE_INTR_DESC_POWER)
2487+
2488+#define TOE_TOE_QUEUE_MAX 64
2489+#define TOE_TOE_QUEUE_NUM 64
2490+#define TOE_CLASS_QUEUE_MAX 14
2491+#define TOE_CLASS_QUEUE_NUM 14
2492+#define TOE_INTR_QUEUE_MAX 4
2493+#define TOE_INTR_QUEUE_NUM 4
2494+#define TOE_SW_TXQ_MAX 6
2495+#define TOE_SW_TXQ_NUM 1
2496+#define TOE_HW_TXQ_MAX 4
2497+#define TOE_HW_TXQ_NUM 4
2498+
2499+#define RWPTR_ADVANCE_ONE(x, max) ((x == (max -1)) ? 0 : x+1)
2500+#define RWPTR_RECEDE_ONE(x, max) ((x == 0) ? (max -1) : x-1)
2501+#define SET_WPTR(addr, data) (*(volatile u16 * const)((u32)(addr) + 2) = (u16)data)
2502+#define SET_RPTR(addr, data) (*(volatile u16 * const)((u32)(addr)) = (u16)data)
2503+
2504+/*
2505+ * Global registers
2506+ * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000)
2507+ * Base 0x60000000
2508+ */
2509+#define GLOBAL_TOE_VERSION_REG 0x0000
2510+#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
2511+#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
2512+#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
2513+#define GLOBAL_SWFQ_RWPTR_REG 0x0014
2514+#define GLOBAL_HWFQ_RWPTR_REG 0x0018
2515+#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
2516+#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
2517+#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
2518+#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
2519+#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
2520+#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
2521+#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
2522+#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
2523+#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
2524+#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
2525+#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
2526+#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
2527+#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
2528+#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
2529+#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
2530+#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
2531+#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
2532+
2533+/*
2534+ * GMAC 0/1 DMA/TOE register
2535+ * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000)
2536+ * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000)
2537+ * Base 0x60008000 or 0x6000C000
2538+ */
2539+#define GMAC_DMA_CTRL_REG 0x0000
2540+#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
2541+#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
2542+#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
2543+#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
2544+#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
2545+#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
2546+#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
2547+#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
2548+#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
2549+#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
2550+#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
2551+#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
2552+#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
2553+#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
2554+#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
2555+#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
2556+#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
2557+#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
2558+#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
2559+#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
2560+#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
2561+#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
2562+#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
2563+#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
2564+#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
2565+#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
2566+#define GMAC_HASH_ENGINE_REG0 0x0070
2567+#define GMAC_HASH_ENGINE_REG1 0x0074
2568+/* matching rule 0 Control register 0 */
2569+#define GMAC_MR0CR0 0x0078
2570+#define GMAC_MR0CR1 0x007C
2571+#define GMAC_MR0CR2 0x0080
2572+#define GMAC_MR1CR0 0x0084
2573+#define GMAC_MR1CR1 0x0088
2574+#define GMAC_MR1CR2 0x008C
2575+#define GMAC_MR2CR0 0x0090
2576+#define GMAC_MR2CR1 0x0094
2577+#define GMAC_MR2CR2 0x0098
2578+#define GMAC_MR3CR0 0x009C
2579+#define GMAC_MR3CR1 0x00A0
2580+#define GMAC_MR3CR2 0x00A4
2581+/* Support Protocol Regsister 0 */
2582+#define GMAC_SPR0 0x00A8
2583+#define GMAC_SPR1 0x00AC
2584+#define GMAC_SPR2 0x00B0
2585+#define GMAC_SPR3 0x00B4
2586+#define GMAC_SPR4 0x00B8
2587+#define GMAC_SPR5 0x00BC
2588+#define GMAC_SPR6 0x00C0
2589+#define GMAC_SPR7 0x00C4
2590+/* GMAC Hash/Rx/Tx AHB Weighting register */
2591+#define GMAC_AHB_WEIGHT_REG 0x00C8
2592+
2593+/*
2594+ * TOE GMAC 0/1 register
2595+ * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000)
2596+ * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000)
2597+ * Base 0x6000A000 or 0x6000E000
2598+ */
2599+enum GMAC_REGISTER {
2600+ GMAC_STA_ADD0 = 0x0000,
2601+ GMAC_STA_ADD1 = 0x0004,
2602+ GMAC_STA_ADD2 = 0x0008,
2603+ GMAC_RX_FLTR = 0x000c,
2604+ GMAC_MCAST_FIL0 = 0x0010,
2605+ GMAC_MCAST_FIL1 = 0x0014,
2606+ GMAC_CONFIG0 = 0x0018,
2607+ GMAC_CONFIG1 = 0x001c,
2608+ GMAC_CONFIG2 = 0x0020,
2609+ GMAC_CONFIG3 = 0x0024,
2610+ GMAC_RESERVED = 0x0028,
2611+ GMAC_STATUS = 0x002c,
2612+ GMAC_IN_DISCARDS= 0x0030,
2613+ GMAC_IN_ERRORS = 0x0034,
2614+ GMAC_IN_MCAST = 0x0038,
2615+ GMAC_IN_BCAST = 0x003c,
2616+ GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */
2617+ GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */
2618+};
2619+
2620+/*
2621+ * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
2622+ */
2623+typedef union {
2624+ unsigned int bits32;
2625+ unsigned int base_size;
2626+} DMA_Q_BASE_SIZE_T;
2627+#define DMA_Q_BASE_MASK (~0x0f)
2628+
2629+/*
2630+ * DMA SKB Buffer register (offset 0x0008)
2631+ */
2632+typedef union {
2633+ unsigned int bits32;
2634+ struct bit_0008 {
2635+ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
2636+ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
2637+ } bits;
2638+} DMA_SKB_SIZE_T;
2639+
2640+/*
2641+ * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
2642+ */
2643+typedef union {
2644+ unsigned int bits32;
2645+ struct bit_000c {
2646+ unsigned int rptr : 16; /* Read Ptr, RO */
2647+ unsigned int wptr : 16; /* Write Ptr, RW */
2648+ } bits;
2649+} DMA_RWPTR_T;
2650+
2651+/*
2652+ * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
2653+ * see DMA_RWPTR_T structure
2654+ */
2655+
2656+/*
2657+ * Interrupt Status Register 0 (offset 0x0020)
2658+ * Interrupt Mask Register 0 (offset 0x0024)
2659+ * Interrupt Select Register 0 (offset 0x0028)
2660+ */
2661+typedef union {
2662+ unsigned int bits32;
2663+ struct bit_0020 {
2664+ /* GMAC0 SW Tx Queue 0 EOF Interrupt */
2665+ unsigned int swtq00_eof : 1;
2666+ unsigned int swtq01_eof : 1;
2667+ unsigned int swtq02_eof : 1;
2668+ unsigned int swtq03_eof : 1;
2669+ unsigned int swtq04_eof : 1;
2670+ unsigned int swtq05_eof : 1;
2671+ /* GMAC1 SW Tx Queue 0 EOF Interrupt */
2672+ unsigned int swtq10_eof : 1;
2673+ unsigned int swtq11_eof : 1;
2674+ unsigned int swtq12_eof : 1;
2675+ unsigned int swtq13_eof : 1;
2676+ unsigned int swtq14_eof : 1;
2677+ unsigned int swtq15_eof : 1;
2678+ /* GMAC0 SW Tx Queue 0 Finish Interrupt */
2679+ unsigned int swtq00_fin : 1;
2680+ unsigned int swtq01_fin : 1;
2681+ unsigned int swtq02_fin : 1;
2682+ unsigned int swtq03_fin : 1;
2683+ unsigned int swtq04_fin : 1;
2684+ unsigned int swtq05_fin : 1;
2685+ /* GMAC1 SW Tx Queue 0 Finish Interrupt */
2686+ unsigned int swtq10_fin : 1;
2687+ unsigned int swtq11_fin : 1;
2688+ unsigned int swtq12_fin : 1;
2689+ unsigned int swtq13_fin : 1;
2690+ unsigned int swtq14_fin : 1;
2691+ unsigned int swtq15_fin : 1;
2692+ /* GMAC0 Rx Descriptor Protocol Error */
2693+ unsigned int rxPerr0 : 1;
2694+ /* GMAC0 AHB Bus Error while Rx */
2695+ unsigned int rxDerr0 : 1;
2696+ /* GMAC1 Rx Descriptor Protocol Error */
2697+ unsigned int rxPerr1 : 1;
2698+ /* GMAC1 AHB Bus Error while Rx */
2699+ unsigned int rxDerr1 : 1;
2700+ /* GMAC0 Tx Descriptor Protocol Error */
2701+ unsigned int txPerr0 : 1;
2702+ /* GMAC0 AHB Bus Error while Tx */
2703+ unsigned int txDerr0 : 1;
2704+ /* GMAC1 Tx Descriptor Protocol Error */
2705+ unsigned int txPerr1 : 1;
2706+ /* GMAC1 AHB Bus Error while Tx */
2707+ unsigned int txDerr1 : 1;
2708+ } bits;
2709+} INTR_REG0_T;
2710+
2711+#define GMAC1_TXDERR_INT_BIT BIT(31)
2712+#define GMAC1_TXPERR_INT_BIT BIT(30)
2713+#define GMAC0_TXDERR_INT_BIT BIT(29)
2714+#define GMAC0_TXPERR_INT_BIT BIT(28)
2715+#define GMAC1_RXDERR_INT_BIT BIT(27)
2716+#define GMAC1_RXPERR_INT_BIT BIT(26)
2717+#define GMAC0_RXDERR_INT_BIT BIT(25)
2718+#define GMAC0_RXPERR_INT_BIT BIT(24)
2719+#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
2720+#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
2721+#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
2722+#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
2723+#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
2724+#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
2725+#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
2726+#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
2727+#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
2728+#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
2729+#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
2730+#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
2731+#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
2732+#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
2733+#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
2734+#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
2735+#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
2736+#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
2737+#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
2738+#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
2739+#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
2740+#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
2741+#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
2742+#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
2743+
2744+/*
2745+ * Interrupt Status Register 1 (offset 0x0030)
2746+ * Interrupt Mask Register 1 (offset 0x0034)
2747+ * Interrupt Select Register 1 (offset 0x0038)
2748+ */
2749+typedef union {
2750+ unsigned int bits32;
2751+ struct bit_0030 {
2752+ unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */
2753+ unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */
2754+ unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */
2755+ unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */
2756+ unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */
2757+ unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */
2758+ unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */
2759+ unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */
2760+ unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */
2761+ unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */
2762+ unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */
2763+ unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */
2764+ unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */
2765+ unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */
2766+ unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */
2767+ unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */
2768+ unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */
2769+ unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */
2770+ unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */
2771+ } bits;
2772+} INTR_REG1_T;
2773+
2774+#define TOE_IQ3_FULL_INT_BIT BIT(31)
2775+#define TOE_IQ2_FULL_INT_BIT BIT(30)
2776+#define TOE_IQ1_FULL_INT_BIT BIT(29)
2777+#define TOE_IQ0_FULL_INT_BIT BIT(28)
2778+#define TOE_IQ3_INT_BIT BIT(27)
2779+#define TOE_IQ2_INT_BIT BIT(26)
2780+#define TOE_IQ1_INT_BIT BIT(25)
2781+#define TOE_IQ0_INT_BIT BIT(24)
2782+#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
2783+#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
2784+#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
2785+#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
2786+#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
2787+#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
2788+#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
2789+#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
2790+#define CLASS_RX_INT_BIT(x) BIT((x + 2))
2791+#define DEFAULT_Q1_INT_BIT BIT(1)
2792+#define DEFAULT_Q0_INT_BIT BIT(0)
2793+
2794+#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
2795+ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
2796+#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
2797+ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
2798+#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
2799+#define TOE_CLASS_RX_INT_BITS 0xfffc
2800+
2801+/*
2802+ * Interrupt Status Register 2 (offset 0x0040)
2803+ * Interrupt Mask Register 2 (offset 0x0044)
2804+ * Interrupt Select Register 2 (offset 0x0048)
2805+ */
2806+typedef union {
2807+ unsigned int bits32;
2808+ struct bit_0040 {
2809+ unsigned int toe_q0_full : 1; // bit 0 TOE Queue 0 Full Interrupt
2810+ unsigned int toe_q1_full : 1; // bit 1 TOE Queue 1 Full Interrupt
2811+ unsigned int toe_q2_full : 1; // bit 2 TOE Queue 2 Full Interrupt
2812+ unsigned int toe_q3_full : 1; // bit 3 TOE Queue 3 Full Interrupt
2813+ unsigned int toe_q4_full : 1; // bit 4 TOE Queue 4 Full Interrupt
2814+ unsigned int toe_q5_full : 1; // bit 5 TOE Queue 5 Full Interrupt
2815+ unsigned int toe_q6_full : 1; // bit 6 TOE Queue 6 Full Interrupt
2816+ unsigned int toe_q7_full : 1; // bit 7 TOE Queue 7 Full Interrupt
2817+ unsigned int toe_q8_full : 1; // bit 8 TOE Queue 8 Full Interrupt
2818+ unsigned int toe_q9_full : 1; // bit 9 TOE Queue 9 Full Interrupt
2819+ unsigned int toe_q10_full : 1; // bit 10 TOE Queue 10 Full Interrupt
2820+ unsigned int toe_q11_full : 1; // bit 11 TOE Queue 11 Full Interrupt
2821+ unsigned int toe_q12_full : 1; // bit 12 TOE Queue 12 Full Interrupt
2822+ unsigned int toe_q13_full : 1; // bit 13 TOE Queue 13 Full Interrupt
2823+ unsigned int toe_q14_full : 1; // bit 14 TOE Queue 14 Full Interrupt
2824+ unsigned int toe_q15_full : 1; // bit 15 TOE Queue 15 Full Interrupt
2825+ unsigned int toe_q16_full : 1; // bit 16 TOE Queue 16 Full Interrupt
2826+ unsigned int toe_q17_full : 1; // bit 17 TOE Queue 17 Full Interrupt
2827+ unsigned int toe_q18_full : 1; // bit 18 TOE Queue 18 Full Interrupt
2828+ unsigned int toe_q19_full : 1; // bit 19 TOE Queue 19 Full Interrupt
2829+ unsigned int toe_q20_full : 1; // bit 20 TOE Queue 20 Full Interrupt
2830+ unsigned int toe_q21_full : 1; // bit 21 TOE Queue 21 Full Interrupt
2831+ unsigned int toe_q22_full : 1; // bit 22 TOE Queue 22 Full Interrupt
2832+ unsigned int toe_q23_full : 1; // bit 23 TOE Queue 23 Full Interrupt
2833+ unsigned int toe_q24_full : 1; // bit 24 TOE Queue 24 Full Interrupt
2834+ unsigned int toe_q25_full : 1; // bit 25 TOE Queue 25 Full Interrupt
2835+ unsigned int toe_q26_full : 1; // bit 26 TOE Queue 26 Full Interrupt
2836+ unsigned int toe_q27_full : 1; // bit 27 TOE Queue 27 Full Interrupt
2837+ unsigned int toe_q28_full : 1; // bit 28 TOE Queue 28 Full Interrupt
2838+ unsigned int toe_q29_full : 1; // bit 29 TOE Queue 29 Full Interrupt
2839+ unsigned int toe_q30_full : 1; // bit 30 TOE Queue 30 Full Interrupt
2840+ unsigned int toe_q31_full : 1; // bit 31 TOE Queue 31 Full Interrupt
2841+ } bits;
2842+} INTR_REG2_T;
2843+
2844+#define TOE_QL_FULL_INT_BIT(x) BIT(x)
2845+
2846+/*
2847+ * Interrupt Status Register 3 (offset 0x0050)
2848+ * Interrupt Mask Register 3 (offset 0x0054)
2849+ * Interrupt Select Register 3 (offset 0x0058)
2850+ */
2851+typedef union {
2852+ unsigned int bits32;
2853+ struct bit_0050 {
2854+ unsigned int toe_q32_full : 1; // bit 32 TOE Queue 32 Full Interrupt
2855+ unsigned int toe_q33_full : 1; // bit 33 TOE Queue 33 Full Interrupt
2856+ unsigned int toe_q34_full : 1; // bit 34 TOE Queue 34 Full Interrupt
2857+ unsigned int toe_q35_full : 1; // bit 35 TOE Queue 35 Full Interrupt
2858+ unsigned int toe_q36_full : 1; // bit 36 TOE Queue 36 Full Interrupt
2859+ unsigned int toe_q37_full : 1; // bit 37 TOE Queue 37 Full Interrupt
2860+ unsigned int toe_q38_full : 1; // bit 38 TOE Queue 38 Full Interrupt
2861+ unsigned int toe_q39_full : 1; // bit 39 TOE Queue 39 Full Interrupt
2862+ unsigned int toe_q40_full : 1; // bit 40 TOE Queue 40 Full Interrupt
2863+ unsigned int toe_q41_full : 1; // bit 41 TOE Queue 41 Full Interrupt
2864+ unsigned int toe_q42_full : 1; // bit 42 TOE Queue 42 Full Interrupt
2865+ unsigned int toe_q43_full : 1; // bit 43 TOE Queue 43 Full Interrupt
2866+ unsigned int toe_q44_full : 1; // bit 44 TOE Queue 44 Full Interrupt
2867+ unsigned int toe_q45_full : 1; // bit 45 TOE Queue 45 Full Interrupt
2868+ unsigned int toe_q46_full : 1; // bit 46 TOE Queue 46 Full Interrupt
2869+ unsigned int toe_q47_full : 1; // bit 47 TOE Queue 47 Full Interrupt
2870+ unsigned int toe_q48_full : 1; // bit 48 TOE Queue 48 Full Interrupt
2871+ unsigned int toe_q49_full : 1; // bit 49 TOE Queue 49 Full Interrupt
2872+ unsigned int toe_q50_full : 1; // bit 50 TOE Queue 50 Full Interrupt
2873+ unsigned int toe_q51_full : 1; // bit 51 TOE Queue 51 Full Interrupt
2874+ unsigned int toe_q52_full : 1; // bit 52 TOE Queue 52 Full Interrupt
2875+ unsigned int toe_q53_full : 1; // bit 53 TOE Queue 53 Full Interrupt
2876+ unsigned int toe_q54_full : 1; // bit 54 TOE Queue 54 Full Interrupt
2877+ unsigned int toe_q55_full : 1; // bit 55 TOE Queue 55 Full Interrupt
2878+ unsigned int toe_q56_full : 1; // bit 56 TOE Queue 56 Full Interrupt
2879+ unsigned int toe_q57_full : 1; // bit 57 TOE Queue 57 Full Interrupt
2880+ unsigned int toe_q58_full : 1; // bit 58 TOE Queue 58 Full Interrupt
2881+ unsigned int toe_q59_full : 1; // bit 59 TOE Queue 59 Full Interrupt
2882+ unsigned int toe_q60_full : 1; // bit 60 TOE Queue 60 Full Interrupt
2883+ unsigned int toe_q61_full : 1; // bit 61 TOE Queue 61 Full Interrupt
2884+ unsigned int toe_q62_full : 1; // bit 62 TOE Queue 62 Full Interrupt
2885+ unsigned int toe_q63_full : 1; // bit 63 TOE Queue 63 Full Interrupt
2886+ } bits;
2887+} INTR_REG3_T;
2888+
2889+#define TOE_QH_FULL_INT_BIT(x) BIT(x-32)
2890+
2891+/*
2892+ * Interrupt Status Register 4 (offset 0x0060)
2893+ * Interrupt Mask Register 4 (offset 0x0064)
2894+ * Interrupt Select Register 4 (offset 0x0068)
2895+ */
2896+typedef union {
2897+ unsigned char byte;
2898+ struct bit_0060 {
2899+ unsigned char status_changed : 1; // Status Changed Intr for RGMII Mode
2900+ unsigned char rx_overrun : 1; // GMAC Rx FIFO overrun interrupt
2901+ unsigned char tx_pause_off : 1; // received pause off frame interrupt
2902+ unsigned char rx_pause_off : 1; // received pause off frame interrupt
2903+ unsigned char tx_pause_on : 1; // transmit pause on frame interrupt
2904+ unsigned char rx_pause_on : 1; // received pause on frame interrupt
2905+ unsigned char cnt_full : 1; // MIB counters half full interrupt
2906+ unsigned char reserved : 1; //
2907+ } _PACKED_ bits;
2908+} _PACKED_ GMAC_INTR_T;
2909+
2910+typedef union {
2911+ unsigned int bits32;
2912+ struct bit_0060_2 {
2913+ unsigned int swfq_empty : 1; // bit 0 Software Free Queue Empty Intr.
2914+ unsigned int hwfq_empty : 1; // bit 1 Hardware Free Queue Empty Intr.
2915+ unsigned int class_qf_int : 14; // bit 15:2 Classification Rx Queue13-0 Full Intr.
2916+ GMAC_INTR_T gmac0;
2917+ GMAC_INTR_T gmac1;
2918+ } bits;
2919+} INTR_REG4_T;
2920+
2921+#define GMAC1_RESERVED_INT_BIT BIT(31)
2922+#define GMAC1_MIB_INT_BIT BIT(30)
2923+#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
2924+#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
2925+#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
2926+#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
2927+#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
2928+#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
2929+#define GMAC0_RESERVED_INT_BIT BIT(23)
2930+#define GMAC0_MIB_INT_BIT BIT(22)
2931+#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
2932+#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
2933+#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
2934+#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
2935+#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
2936+#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
2937+#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))
2938+#define HWFQ_EMPTY_INT_BIT BIT(1)
2939+#define SWFQ_EMPTY_INT_BIT BIT(0)
2940+
2941+#if 1
2942+#define GMAC0_INT_BITS (GMAC0_MIB_INT_BIT)
2943+#define GMAC1_INT_BITS (GMAC1_MIB_INT_BIT)
2944+#else
2945+#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
2946+ GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \
2947+ GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \
2948+ GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
2949+#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
2950+ GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \
2951+ GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \
2952+ GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
2953+#endif
2954+
2955+#define CLASS_RX_FULL_INT_BITS 0xfffc
2956+
2957+/*
2958+ * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070)
2959+ */
2960+typedef union {
2961+ unsigned int bits32;
2962+ struct bit_0070_2 {
2963+ unsigned int swfq_empty : 8; // 7:0 Software Free Queue Empty Threshold
2964+ unsigned int hwfq_empty : 8; // 15:8 Hardware Free Queue Empty Threshold
2965+ unsigned int intrq : 8; // 23:16
2966+ unsigned int toe_class : 8; // 31:24
2967+ } bits;
2968+} QUEUE_THRESHOLD_T;
2969+
2970+
2971+/*
2972+ * GMAC DMA Control Register
2973+ * GMAC0 offset 0x8000
2974+ * GMAC1 offset 0xC000
2975+ */
2976+typedef union {
2977+ unsigned int bits32;
2978+ struct bit_8000 {
2979+ unsigned int td_bus : 2; // bit 1:0 Peripheral Bus Width
2980+ unsigned int td_burst_size : 2; // bit 3:2 TxDMA max burst size for every AHB request
2981+ unsigned int td_prot : 4; // bit 7:4 TxDMA protection control
2982+ unsigned int rd_bus : 2; // bit 9:8 Peripheral Bus Width
2983+ unsigned int rd_burst_size : 2; // bit 11:10 DMA max burst size for every AHB request
2984+ unsigned int rd_prot : 4; // bit 15:12 DMA Protection Control
2985+ unsigned int rd_insert_bytes : 2; // bit 17:16
2986+ unsigned int reserved : 10; // bit 27:18
2987+ unsigned int drop_small_ack : 1; // bit 28 1: Drop, 0: Accept
2988+ unsigned int loopback : 1; // bit 29 Loopback TxDMA to RxDMA
2989+ unsigned int td_enable : 1; // bit 30 Tx DMA Enable
2990+ unsigned int rd_enable : 1; // bit 31 Rx DMA Enable
2991+ } bits;
2992+} GMAC_DMA_CTRL_T;
2993+
2994+/*
2995+ * GMAC Tx Weighting Control Register 0
2996+ * GMAC0 offset 0x8004
2997+ * GMAC1 offset 0xC004
2998+ */
2999+typedef union {
3000+ unsigned int bits32;
3001+ struct bit_8004 {
3002+ unsigned int hw_tq0 : 6; // bit 5:0 HW TX Queue 3
3003+ unsigned int hw_tq1 : 6; // bit 11:6 HW TX Queue 2
3004+ unsigned int hw_tq2 : 6; // bit 17:12 HW TX Queue 1
3005+ unsigned int hw_tq3 : 6; // bit 23:18 HW TX Queue 0
3006+ unsigned int reserved : 8; // bit 31:24
3007+ } bits;
3008+} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */
3009+
3010+/*
3011+ * GMAC Tx Weighting Control Register 1
3012+ * GMAC0 offset 0x8008
3013+ * GMAC1 offset 0xC008
3014+ */
3015+typedef union {
3016+ unsigned int bits32;
3017+ struct bit_8008 {
3018+ unsigned int sw_tq0 : 5; // bit 4:0 SW TX Queue 0
3019+ unsigned int sw_tq1 : 5; // bit 9:5 SW TX Queue 1
3020+ unsigned int sw_tq2 : 5; // bit 14:10 SW TX Queue 2
3021+ unsigned int sw_tq3 : 5; // bit 19:15 SW TX Queue 3
3022+ unsigned int sw_tq4 : 5; // bit 24:20 SW TX Queue 4
3023+ unsigned int sw_tq5 : 5; // bit 29:25 SW TX Queue 5
3024+ unsigned int reserved : 2; // bit 31:30
3025+ } bits;
3026+} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */
3027+
3028+/*
3029+ * Queue Read/Write Pointer
3030+ * GMAC SW TX Queue 0~5 Read/Write Pointer register
3031+ * GMAC0 offset 0x800C ~ 0x8020
3032+ * GMAC1 offset 0xC00C ~ 0xC020
3033+ * GMAC HW TX Queue 0~3 Read/Write Pointer register
3034+ * GMAC0 offset 0x8024 ~ 0x8030
3035+ * GMAC1 offset 0xC024 ~ 0xC030
3036+ *
3037+ * see DMA_RWPTR_T structure
3038+ */
3039+
3040+/*
3041+ * GMAC DMA Tx First Description Address Register
3042+ * GMAC0 offset 0x8038
3043+ * GMAC1 offset 0xC038
3044+ */
3045+typedef union {
3046+ unsigned int bits32;
3047+ struct bit_8038 {
3048+ unsigned int reserved : 3;
3049+ unsigned int td_busy : 1; // bit 3 1: TxDMA busy; 0: TxDMA idle
3050+ unsigned int td_first_des_ptr : 28; // bit 31:4 first descriptor address
3051+ } bits;
3052+} GMAC_TXDMA_FIRST_DESC_T;
3053+
3054+/*
3055+ * GMAC DMA Tx Current Description Address Register
3056+ * GMAC0 offset 0x803C
3057+ * GMAC1 offset 0xC03C
3058+ */
3059+typedef union {
3060+ unsigned int bits32;
3061+ struct bit_803C {
3062+ unsigned int reserved : 4;
3063+ unsigned int td_curr_desc_ptr : 28; // bit 31:4 current descriptor address
3064+ } bits;
3065+} GMAC_TXDMA_CURR_DESC_T;
3066+
3067+/*
3068+ * GMAC DMA Tx Description Word 0 Register
3069+ * GMAC0 offset 0x8040
3070+ * GMAC1 offset 0xC040
3071+ */
3072+typedef union {
3073+ unsigned int bits32;
3074+ struct bit_8040 {
3075+ unsigned int buffer_size : 16; // bit 15:0 Transfer size
3076+ unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
3077+ unsigned int status_tx_ok : 1; // bit 22 Tx Status, 1: Successful 0: Failed
3078+ unsigned int status_rvd : 6; // bit 28:23 Tx Status, Reserved bits
3079+ unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
3080+ unsigned int derr : 1; // bit 30 data error during processing this descriptor
3081+ unsigned int reserved : 1; // bit 31
3082+ } bits;
3083+} GMAC_TXDESC_0_T;
3084+
3085+/*
3086+ * GMAC DMA Tx Description Word 1 Register
3087+ * GMAC0 offset 0x8044
3088+ * GMAC1 offset 0xC044
3089+ */
3090+typedef union {
3091+ unsigned int bits32;
3092+ struct txdesc_word1 {
3093+ unsigned int byte_count : 16; // bit 15: 0 Tx Frame Byte Count
3094+ unsigned int mtu_enable : 1; // bit 16 TSS segmentation use MTU setting
3095+ unsigned int ip_chksum : 1; // bit 17 IPV4 Header Checksum Enable
3096+ unsigned int ipv6_enable : 1; // bit 18 IPV6 Tx Enable
3097+ unsigned int tcp_chksum : 1; // bit 19 TCP Checksum Enable
3098+ unsigned int udp_chksum : 1; // bit 20 UDP Checksum Enable
3099+ unsigned int bypass_tss : 1; // bit 21
3100+ unsigned int ip_fixed_len : 1; // bit 22
3101+ unsigned int reserved : 9; // bit 31:23 Tx Flag, Reserved
3102+ } bits;
3103+} GMAC_TXDESC_1_T;
3104+
3105+#define TSS_IP_FIXED_LEN_BIT BIT(22)
3106+#define TSS_UDP_CHKSUM_BIT BIT(20)
3107+#define TSS_TCP_CHKSUM_BIT BIT(19)
3108+#define TSS_IPV6_ENABLE_BIT BIT(18)
3109+#define TSS_IP_CHKSUM_BIT BIT(17)
3110+#define TSS_MTU_ENABLE_BIT BIT(16)
3111+
3112+/*
3113+ * GMAC DMA Tx Description Word 2 Register
3114+ * GMAC0 offset 0x8048
3115+ * GMAC1 offset 0xC048
3116+ */
3117+typedef union {
3118+ unsigned int bits32;
3119+ unsigned int buf_adr;
3120+} GMAC_TXDESC_2_T;
3121+
3122+/*
3123+ * GMAC DMA Tx Description Word 3 Register
3124+ * GMAC0 offset 0x804C
3125+ * GMAC1 offset 0xC04C
3126+ */
3127+typedef union {
3128+ unsigned int bits32;
3129+ struct txdesc_word3 {
3130+ unsigned int mtu_size : 11; // bit 10: 0 Tx Frame Byte Count
3131+ unsigned int reserved : 18; // bit 28:11
3132+ unsigned int eofie : 1; // bit 29 End of frame interrupt enable
3133+ unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
3134+ } bits;
3135+} GMAC_TXDESC_3_T;
3136+#define SOF_EOF_BIT_MASK 0x3fffffff
3137+#define SOF_BIT 0x80000000
3138+#define EOF_BIT 0x40000000
3139+#define EOFIE_BIT BIT(29)
3140+#define MTU_SIZE_BIT_MASK 0x7ff
3141+
3142+/*
3143+ * GMAC Tx Descriptor
3144+ */
3145+typedef struct {
3146+ GMAC_TXDESC_0_T word0;
3147+ GMAC_TXDESC_1_T word1;
3148+ GMAC_TXDESC_2_T word2;
3149+ GMAC_TXDESC_3_T word3;
3150+} GMAC_TXDESC_T;
3151+
3152+/*
3153+ * GMAC DMA Rx First Description Address Register
3154+ * GMAC0 offset 0x8058
3155+ * GMAC1 offset 0xC058
3156+ */
3157+typedef union {
3158+ unsigned int bits32;
3159+ struct bit_8058 {
3160+ unsigned int reserved : 3; // bit 2:0
3161+ unsigned int rd_busy : 1; // bit 3 1-RxDMA busy; 0-RxDMA idle
3162+ unsigned int rd_first_des_ptr : 28; // bit 31:4 first descriptor address
3163+ } bits;
3164+} GMAC_RXDMA_FIRST_DESC_T;
3165+
3166+/*
3167+ * GMAC DMA Rx Current Description Address Register
3168+ * GMAC0 offset 0x805C
3169+ * GMAC1 offset 0xC05C
3170+ */
3171+typedef union {
3172+ unsigned int bits32;
3173+ struct bit_805C {
3174+ unsigned int reserved : 4; // bit 3:0
3175+ unsigned int rd_curr_des_ptr : 28; // bit 31:4 current descriptor address
3176+ } bits;
3177+} GMAC_RXDMA_CURR_DESC_T;
3178+
3179+/*
3180+ * GMAC DMA Rx Description Word 0 Register
3181+ * GMAC0 offset 0x8060
3182+ * GMAC1 offset 0xC060
3183+ */
3184+typedef union {
3185+ unsigned int bits32;
3186+ struct bit_8060 {
3187+ unsigned int buffer_size : 16; // bit 15:0 number of descriptors used for the current frame
3188+ unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
3189+ unsigned int status : 4; // bit 24:22 Status of rx frame
3190+ unsigned int chksum_status : 3; // bit 28:26 Check Sum Status
3191+ unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
3192+ unsigned int derr : 1; // bit 30 data error during processing this descriptor
3193+ unsigned int drop : 1; // bit 31 TOE/CIS Queue Full dropped packet to default queue
3194+ } bits;
3195+} GMAC_RXDESC_0_T;
3196+
3197+#define GMAC_RXDESC_0_T_derr BIT(30)
3198+#define GMAC_RXDESC_0_T_perr BIT(29)
3199+#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26))
3200+#define GMAC_RXDESC_0_T_status(x) BIT((x+22))
3201+#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16))
3202+
3203+#define RX_CHKSUM_IP_UDP_TCP_OK 0
3204+#define RX_CHKSUM_IP_OK_ONLY 1
3205+#define RX_CHKSUM_NONE 2
3206+#define RX_CHKSUM_IP_ERR_UNKNOWN 4
3207+#define RX_CHKSUM_IP_ERR 5
3208+#define RX_CHKSUM_TCP_UDP_ERR 6
3209+#define RX_CHKSUM_NUM 8
3210+
3211+#define RX_STATUS_GOOD_FRAME 0
3212+#define RX_STATUS_TOO_LONG_GOOD_CRC 1
3213+#define RX_STATUS_RUNT_FRAME 2
3214+#define RX_STATUS_SFD_NOT_FOUND 3
3215+#define RX_STATUS_CRC_ERROR 4
3216+#define RX_STATUS_TOO_LONG_BAD_CRC 5
3217+#define RX_STATUS_ALIGNMENT_ERROR 6
3218+#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
3219+#define RX_STATUS_RX_ERR 8
3220+#define RX_STATUS_DA_FILTERED 9
3221+#define RX_STATUS_BUFFER_FULL 10
3222+#define RX_STATUS_NUM 16
3223+
3224+
3225+/*
3226+ * GMAC DMA Rx Description Word 1 Register
3227+ * GMAC0 offset 0x8064
3228+ * GMAC1 offset 0xC064
3229+ */
3230+typedef union {
3231+ unsigned int bits32;
3232+ struct rxdesc_word1 {
3233+ unsigned int byte_count : 16; // bit 15: 0 Rx Frame Byte Count
3234+ unsigned int sw_id : 16; // bit 31:16 Software ID
3235+ } bits;
3236+} GMAC_RXDESC_1_T;
3237+
3238+/*
3239+ * GMAC DMA Rx Description Word 2 Register
3240+ * GMAC0 offset 0x8068
3241+ * GMAC1 offset 0xC068
3242+ */
3243+typedef union {
3244+ unsigned int bits32;
3245+ unsigned int buf_adr;
3246+} GMAC_RXDESC_2_T;
3247+
3248+#define RX_INSERT_NONE 0
3249+#define RX_INSERT_1_BYTE 1
3250+#define RX_INSERT_2_BYTE 2
3251+#define RX_INSERT_3_BYTE 3
3252+
3253+#define RX_INSERT_BYTES RX_INSERT_2_BYTE
3254+/*
3255+ * GMAC DMA Rx Description Word 3 Register
3256+ * GMAC0 offset 0x806C
3257+ * GMAC1 offset 0xC06C
3258+ */
3259+typedef union {
3260+ unsigned int bits32;
3261+ struct rxdesc_word3 {
3262+ unsigned int l3_offset : 8; // bit 7: 0 L3 data offset
3263+ unsigned int l4_offset : 8; // bit 15: 8 L4 data offset
3264+ unsigned int l7_offset : 8; // bit 23: 16 L7 data offset
3265+ unsigned int dup_ack : 1; // bit 24 Duplicated ACK detected
3266+ unsigned int abnormal : 1; // bit 25 abnormal case found
3267+ unsigned int option : 1; // bit 26 IPV4 option or IPV6 extension header
3268+ unsigned int out_of_seq : 1; // bit 27 Out of Sequence packet
3269+ unsigned int ctrl_flag : 1; // bit 28 Control Flag is present
3270+ unsigned int eofie : 1; // bit 29 End of frame interrupt enable
3271+ unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
3272+ } bits;
3273+} GMAC_RXDESC_3_T;
3274+
3275+/*
3276+ * GMAC Rx Descriptor
3277+ */
3278+typedef struct {
3279+ GMAC_RXDESC_0_T word0;
3280+ GMAC_RXDESC_1_T word1;
3281+ GMAC_RXDESC_2_T word2;
3282+ GMAC_RXDESC_3_T word3;
3283+} GMAC_RXDESC_T;
3284+
3285+/*
3286+ * GMAC Hash Engine Enable/Action Register 0 Offset Register
3287+ * GMAC0 offset 0x8070
3288+ * GMAC1 offset 0xC070
3289+ */
3290+typedef union {
3291+ unsigned int bits32;
3292+ struct bit_8070 {
3293+ unsigned int mr0hel : 6; // bit 5:0 match rule 0 hash entry size
3294+ unsigned int mr0_action : 5; // bit 10:6 Matching Rule 0 action offset
3295+ unsigned int reserved0 : 4; // bit 14:11
3296+ unsigned int mr0en : 1; // bit 15 Enable Matching Rule 0
3297+ unsigned int mr1hel : 6; // bit 21:16 match rule 1 hash entry size
3298+ unsigned int mr1_action : 5; // bit 26:22 Matching Rule 1 action offset
3299+ unsigned int timing : 3; // bit 29:27
3300+ unsigned int reserved1 : 1; // bit 30
3301+ unsigned int mr1en : 1; // bit 31 Enable Matching Rule 1
3302+ } bits;
3303+} GMAC_HASH_ENABLE_REG0_T;
3304+
3305+/*
3306+ * GMAC Hash Engine Enable/Action Register 1 Offset Register
3307+ * GMAC0 offset 0x8074
3308+ * GMAC1 offset 0xC074
3309+ */
3310+typedef union {
3311+ unsigned int bits32;
3312+ struct bit_8074 {
3313+ unsigned int mr2hel : 6; // bit 5:0 match rule 2 hash entry size
3314+ unsigned int mr2_action : 5; // bit 10:6 Matching Rule 2 action offset
3315+ unsigned int reserved2 : 4; // bit 14:11
3316+ unsigned int mr2en : 1; // bit 15 Enable Matching Rule 2
3317+ unsigned int mr3hel : 6; // bit 21:16 match rule 3 hash entry size
3318+ unsigned int mr3_action : 5; // bit 26:22 Matching Rule 3 action offset
3319+ unsigned int reserved1 : 4; // bit 30:27
3320+ unsigned int mr3en : 1; // bit 31 Enable Matching Rule 3
3321+ } bits;
3322+} GMAC_HASH_ENABLE_REG1_T;
3323+
3324+/*
3325+ * GMAC Matching Rule Control Register 0
3326+ * GMAC0 offset 0x8078
3327+ * GMAC1 offset 0xC078
3328+ */
3329+typedef union {
3330+ unsigned int bits32;
3331+ struct bit_8078 {
3332+ unsigned int sprx : 8; // bit 7:0 Support Protocol Register 7:0
3333+ unsigned int reserved2 : 4; // bit 11:8
3334+ unsigned int tos_traffic : 1; // bit 12 IPV4 TOS or IPV6 Traffice Class
3335+ unsigned int flow_lable : 1; // bit 13 IPV6 Flow label
3336+ unsigned int ip_hdr_len : 1; // bit 14 IPV4 Header length
3337+ unsigned int ip_version : 1; // bit 15 0: IPV4, 1: IPV6
3338+ unsigned int reserved1 : 3; // bit 18:16
3339+ unsigned int pppoe : 1; // bit 19 PPPoE Session ID enable
3340+ unsigned int vlan : 1; // bit 20 VLAN ID enable
3341+ unsigned int ether_type : 1; // bit 21 Ethernet type enable
3342+ unsigned int sa : 1; // bit 22 MAC SA enable
3343+ unsigned int da : 1; // bit 23 MAC DA enable
3344+ unsigned int priority : 3; // bit 26:24 priority if multi-rules matched
3345+ unsigned int port : 1; // bit 27 PORT ID matching enable
3346+ unsigned int l7 : 1; // bit 28 L7 matching enable
3347+ unsigned int l4 : 1; // bit 29 L4 matching enable
3348+ unsigned int l3 : 1; // bit 30 L3 matching enable
3349+ unsigned int l2 : 1; // bit 31 L2 matching enable
3350+ } bits;
3351+} GMAC_MRxCR0_T;
3352+
3353+#define MR_L2_BIT BIT(31)
3354+#define MR_L3_BIT BIT(30)
3355+#define MR_L4_BIT BIT(29)
3356+#define MR_L7_BIT BIT(28)
3357+#define MR_PORT_BIT BIT(27)
3358+#define MR_PRIORITY_BIT BIT(26)
3359+#define MR_DA_BIT BIT(23)
3360+#define MR_SA_BIT BIT(22)
3361+#define MR_ETHER_TYPE_BIT BIT(21)
3362+#define MR_VLAN_BIT BIT(20)
3363+#define MR_PPPOE_BIT BIT(19)
3364+#define MR_IP_VER_BIT BIT(15)
3365+#define MR_IP_HDR_LEN_BIT BIT(14)
3366+#define MR_FLOW_LABLE_BIT BIT(13)
3367+#define MR_TOS_TRAFFIC_BIT BIT(12)
3368+#define MR_SPR_BIT(x) BIT(x)
3369+#define MR_SPR_BITS 0xff
3370+
3371+/*
3372+ * GMAC Matching Rule Control Register 1
3373+ * GMAC0 offset 0x807C
3374+ * GMAC1 offset 0xC07C
3375+ */
3376+typedef union {
3377+ unsigned int bits32;
3378+ struct bit_807C {
3379+ unsigned int l4_byte0_15 : 16; // bit 15: 0
3380+ unsigned int dip_netmask : 7; // bit 22:16 Dest IP net mask, number of mask bits
3381+ unsigned int dip : 1; // bit 23 Dest IP
3382+ unsigned int sip_netmask : 7; // bit 30:24 Srce IP net mask, number of mask bits
3383+ unsigned int sip : 1; // bit 31 Srce IP
3384+ } bits;
3385+} GMAC_MRxCR1_T;
3386+
3387+/*
3388+ * GMAC Matching Rule Control Register 2
3389+ * GMAC0 offset 0x8080
3390+ * GMAC1 offset 0xC080
3391+ */
3392+typedef union {
3393+ unsigned int bits32;
3394+ struct bit_8080 {
3395+ unsigned int l7_byte0_23 : 24; // bit 23:0
3396+ unsigned int l4_byte16_24 : 8; // bit 31: 24
3397+ } bits;
3398+} GMAC_MRxCR2_T;
3399+
3400+/*
3401+ * GMAC Support registers
3402+ * GMAC0 offset 0x80A8
3403+ * GMAC1 offset 0xC0A8
3404+ */
3405+typedef union {
3406+ unsigned int bits32;
3407+ struct bit_80A8 {
3408+ unsigned int protocol : 8; // bit 7:0 Supported protocol
3409+ unsigned int swap : 3; // bit 10:8 Swap
3410+ unsigned int reserved : 21; // bit 31:11
3411+ } bits;
3412+} GMAC_SPR_T;
3413+
3414+/*
3415+ * GMAC_AHB_WEIGHT registers
3416+ * GMAC0 offset 0x80C8
3417+ * GMAC1 offset 0xC0C8
3418+ */
3419+typedef union {
3420+ unsigned int bits32;
3421+ struct bit_80C8 {
3422+ unsigned int hash_weight : 5; // 4:0
3423+ unsigned int rx_weight : 5; // 9:5
3424+ unsigned int tx_weight : 5; // 14:10
3425+ unsigned int pre_req : 5; // 19:15 Rx Data Pre Request FIFO Threshold
3426+ unsigned int tqDV_threshold : 5; // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
3427+ unsigned int reserved : 7; // 31:25
3428+ } bits;
3429+} GMAC_AHB_WEIGHT_T;
3430+
3431+/*
3432+ * the register structure of GMAC
3433+ */
3434+
3435+/*
3436+ * GMAC RX FLTR
3437+ * GMAC0 Offset 0xA00C
3438+ * GMAC1 Offset 0xE00C
3439+ */
3440+typedef union {
3441+ unsigned int bits32;
3442+ struct bit1_000c {
3443+ unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */
3444+ unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */
3445+ unsigned int broadcast : 1; /* enable receive of broadcast frames */
3446+ unsigned int promiscuous : 1; /* enable receive of all frames */
3447+ unsigned int error : 1; /* enable receive of all error frames */
3448+ unsigned int : 27;
3449+ } bits;
3450+} GMAC_RX_FLTR_T;
3451+
3452+/*
3453+ * GMAC Configuration 0
3454+ * GMAC0 Offset 0xA018
3455+ * GMAC1 Offset 0xE018
3456+ */
3457+typedef union {
3458+ unsigned int bits32;
3459+ struct bit1_0018 {
3460+ unsigned int dis_tx : 1; /* 0: disable transmit */
3461+ unsigned int dis_rx : 1; /* 1: disable receive */
3462+ unsigned int loop_back : 1; /* 2: transmit data loopback enable */
3463+ unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */
3464+ unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */
3465+ unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */
3466+ unsigned int dis_bkoff : 1; /* 11: disable back-off function */
3467+ unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */
3468+ unsigned int sim_test : 1; /* 13: speed up timers in simulation */
3469+ unsigned int rx_fc_en : 1; /* 14: RX flow control enable */
3470+ unsigned int tx_fc_en : 1; /* 15: TX flow control enable */
3471+ unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */
3472+ unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */
3473+ unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */
3474+ unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */
3475+ unsigned int rgmm_edge : 1; // 20
3476+ unsigned int rxc_inv : 1; // 21
3477+ unsigned int ipv6_exthdr_order : 1; // 22
3478+ unsigned int rx_err_detect : 1; // 23
3479+ unsigned int port0_chk_hwq : 1; // 24
3480+ unsigned int port1_chk_hwq : 1; // 25
3481+ unsigned int port0_chk_toeq : 1; // 26
3482+ unsigned int port1_chk_toeq : 1; // 27
3483+ unsigned int port0_chk_classq : 1; // 28
3484+ unsigned int port1_chk_classq : 1; // 29
3485+ unsigned int reserved : 2; // 31
3486+ } bits;
3487+} GMAC_CONFIG0_T;
3488+
3489+/*
3490+ * GMAC Configuration 1
3491+ * GMAC0 Offset 0xA01C
3492+ * GMAC1 Offset 0xE01C
3493+ */
3494+typedef union {
3495+ unsigned int bits32;
3496+ struct bit1_001c {
3497+ unsigned int set_threshold : 8; /* flow control set threshold */
3498+ unsigned int rel_threshold : 8; /* flow control release threshold */
3499+ unsigned int reserved : 16;
3500+ } bits;
3501+} GMAC_CONFIG1_T;
3502+
3503+#define GMAC_FLOWCTRL_SET_MAX 32
3504+#define GMAC_FLOWCTRL_SET_MIN 0
3505+#define GMAC_FLOWCTRL_RELEASE_MAX 32
3506+#define GMAC_FLOWCTRL_RELEASE_MIN 0
3507+
3508+/*
3509+ * GMAC Configuration 2
3510+ * GMAC0 Offset 0xA020
3511+ * GMAC1 Offset 0xE020
3512+ */
3513+typedef union {
3514+ unsigned int bits32;
3515+ struct bit1_0020 {
3516+ unsigned int set_threshold : 16; /* flow control set threshold */
3517+ unsigned int rel_threshold : 16; /* flow control release threshold */
3518+ } bits;
3519+} GMAC_CONFIG2_T;
3520+
3521+/*
3522+ * GMAC Configuration 3
3523+ * GMAC0 Offset 0xA024
3524+ * GMAC1 Offset 0xE024
3525+ */
3526+typedef union {
3527+ unsigned int bits32;
3528+ struct bit1_0024 {
3529+ unsigned int set_threshold : 16; /* flow control set threshold */
3530+ unsigned int rel_threshold : 16; /* flow control release threshold */
3531+ } bits;
3532+} GMAC_CONFIG3_T;
3533+
3534+
3535+/*
3536+ * GMAC STATUS
3537+ * GMAC0 Offset 0xA02C
3538+ * GMAC1 Offset 0xE02C
3539+ */
3540+typedef union {
3541+ unsigned int bits32;
3542+ struct bit1_002c {
3543+ unsigned int link : 1; /* link status */
3544+ unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */
3545+ unsigned int duplex : 1; /* duplex mode */
3546+ unsigned int reserved : 1;
3547+ unsigned int mii_rmii : 2; /* PHY interface type */
3548+ unsigned int : 25;
3549+ } bits;
3550+} GMAC_STATUS_T;
3551+
3552+#define GMAC_SPEED_10 0
3553+#define GMAC_SPEED_100 1
3554+#define GMAC_SPEED_1000 2
3555+
3556+#define GMAC_PHY_MII 0
3557+#define GMAC_PHY_GMII 1
3558+#define GMAC_PHY_RGMII_100_10 2
3559+#define GMAC_PHY_RGMII_1000 3
3560+
3561+/*
3562+ * Queue Header
3563+ * (1) TOE Queue Header
3564+ * (2) Non-TOE Queue Header
3565+ * (3) Interrupt Queue Header
3566+ *
3567+ * memory Layout
3568+ * TOE Queue Header
3569+ * 0x60003000 +---------------------------+ 0x0000
3570+ * | TOE Queue 0 Header |
3571+ * | 8 * 4 Bytes |
3572+ * +---------------------------+ 0x0020
3573+ * | TOE Queue 1 Header |
3574+ * | 8 * 4 Bytes |
3575+ * +---------------------------+ 0x0040
3576+ * | ...... |
3577+ * | |
3578+ * +---------------------------+
3579+ *
3580+ * Non TOE Queue Header
3581+ * 0x60002000 +---------------------------+ 0x0000
3582+ * | Default Queue 0 Header |
3583+ * | 2 * 4 Bytes |
3584+ * +---------------------------+ 0x0008
3585+ * | Default Queue 1 Header |
3586+ * | 2 * 4 Bytes |
3587+ * +---------------------------+ 0x0010
3588+ * | Classification Queue 0 |
3589+ * | 2 * 4 Bytes |
3590+ * +---------------------------+
3591+ * | Classification Queue 1 |
3592+ * | 2 * 4 Bytes |
3593+ * +---------------------------+ (n * 8 + 0x10)
3594+ * | ... |
3595+ * | 2 * 4 Bytes |
3596+ * +---------------------------+ (13 * 8 + 0x10)
3597+ * | Classification Queue 13 |
3598+ * | 2 * 4 Bytes |
3599+ * +---------------------------+ 0x80
3600+ * | Interrupt Queue 0 |
3601+ * | 2 * 4 Bytes |
3602+ * +---------------------------+
3603+ * | Interrupt Queue 1 |
3604+ * | 2 * 4 Bytes |
3605+ * +---------------------------+
3606+ * | Interrupt Queue 2 |
3607+ * | 2 * 4 Bytes |
3608+ * +---------------------------+
3609+ * | Interrupt Queue 3 |
3610+ * | 2 * 4 Bytes |
3611+ * +---------------------------+
3612+ *
3613+ */
3614+#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
3615+#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
3616+#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
3617+#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
3618+#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
3619+#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
3620+#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
3621+/*
3622+ * TOE Queue Header Word 0
3623+ */
3624+typedef union {
3625+ unsigned int bits32;
3626+ unsigned int base_size;
3627+} TOE_QHDR0_T;
3628+
3629+#define TOE_QHDR0_BASE_MASK (~0x0f)
3630+
3631+/*
3632+ * TOE Queue Header Word 1
3633+ */
3634+typedef union {
3635+ unsigned int bits32;
3636+ struct bit_qhdr1 {
3637+ unsigned int rptr : 16; // bit 15:0
3638+ unsigned int wptr : 16; // bit 31:16
3639+ } bits;
3640+} TOE_QHDR1_T;
3641+
3642+/*
3643+ * TOE Queue Header Word 2
3644+ */
3645+typedef union {
3646+ unsigned int bits32;
3647+ struct bit_qhdr2 {
3648+ unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
3649+ unsigned int reserved : 7; // bit 23:17
3650+ unsigned int dack : 1; // bit 24 1: Duplicated ACK
3651+ unsigned int abn : 1; // bit 25 1: Abnormal case Found
3652+ unsigned int tcp_opt : 1; // bit 26 1: Have TCP option
3653+ unsigned int ip_opt : 1; // bit 27 1: have IPV4 option or IPV6 Extension header
3654+ unsigned int sat : 1; // bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
3655+ unsigned int osq : 1; // bit 29 1: out of sequence
3656+ unsigned int ctl : 1; // bit 30 1: have control flag bits (except ack)
3657+ unsigned int usd : 1; // bit 31 0: if no data assembled yet
3658+ } bits;
3659+} TOE_QHDR2_T;
3660+
3661+/*
3662+ * TOE Queue Header Word 3
3663+ */
3664+typedef union {
3665+ unsigned int bits32;
3666+ unsigned int seq_num;
3667+} TOE_QHDR3_T;
3668+
3669+/*
3670+ * TOE Queue Header Word 4
3671+ */
3672+typedef union {
3673+ unsigned int bits32;
3674+ unsigned int ack_num;
3675+} TOE_QHDR4_T;
3676+
3677+/*
3678+ * TOE Queue Header Word 5
3679+ */
3680+typedef union {
3681+ unsigned int bits32;
3682+ struct bit_qhdr5 {
3683+ unsigned int AckCnt : 16; // bit 15:0
3684+ unsigned int SeqCnt : 16; // bit 31:16
3685+ } bits;
3686+} TOE_QHDR5_T;
3687+
3688+/*
3689+ * TOE Queue Header Word 6
3690+ */
3691+typedef union {
3692+ unsigned int bits32;
3693+ struct bit_qhdr6 {
3694+ unsigned int WinSize : 16; // bit 15:0
3695+ unsigned int iq_num : 2; // bit 17:16
3696+ unsigned int MaxPktSize : 14; // bit 31:18
3697+ } bits;
3698+} TOE_QHDR6_T;
3699+
3700+/*
3701+ * TOE Queue Header Word 7
3702+ */
3703+typedef union {
3704+ unsigned int bits32;
3705+ struct bit_qhdr7 {
3706+ unsigned int AckThreshold : 16; // bit 15:0
3707+ unsigned int SeqThreshold : 16; // bit 31:16
3708+ } bits;
3709+} TOE_QHDR7_T;
3710+
3711+/*
3712+ * TOE Queue Header
3713+ */
3714+typedef struct {
3715+ TOE_QHDR0_T word0;
3716+ TOE_QHDR1_T word1;
3717+ TOE_QHDR2_T word2;
3718+ TOE_QHDR3_T word3;
3719+ TOE_QHDR4_T word4;
3720+ TOE_QHDR5_T word5;
3721+ TOE_QHDR6_T word6;
3722+ TOE_QHDR7_T word7;
3723+} TOE_QHDR_T;
3724+
3725+/*
3726+ * NONTOE Queue Header Word 0
3727+ */
3728+typedef union {
3729+ unsigned int bits32;
3730+ unsigned int base_size;
3731+} NONTOE_QHDR0_T;
3732+
3733+#define NONTOE_QHDR0_BASE_MASK (~0x0f)
3734+
3735+/*
3736+ * NONTOE Queue Header Word 1
3737+ */
3738+typedef union {
3739+ unsigned int bits32;
3740+ struct bit_nonqhdr1 {
3741+ unsigned int rptr : 16; // bit 15:0
3742+ unsigned int wptr : 16; // bit 31:16
3743+ } bits;
3744+} NONTOE_QHDR1_T;
3745+
3746+/*
3747+ * Non-TOE Queue Header
3748+ */
3749+typedef struct {
3750+ NONTOE_QHDR0_T word0;
3751+ NONTOE_QHDR1_T word1;
3752+} NONTOE_QHDR_T;
3753+
3754+/*
3755+ * Interrupt Queue Header Word 0
3756+ */
3757+typedef union {
3758+ unsigned int bits32;
3759+ struct bit_intrqhdr0 {
3760+ unsigned int win_size : 16; // bit 15:0 Descriptor Ring Size
3761+ unsigned int wptr : 16; // bit 31:16 Write Pointer where hw stopped
3762+ } bits;
3763+} INTR_QHDR0_T;
3764+
3765+/*
3766+ * Interrupt Queue Header Word 1
3767+ */
3768+typedef union {
3769+ unsigned int bits32;
3770+ struct bit_intrqhdr1 {
3771+ unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
3772+ unsigned int tcp_qid : 8; // bit 24:17 TCP Queue ID
3773+ unsigned int dack : 1; // bit 25 1: Duplicated ACK
3774+ unsigned int abn : 1; // bit 26 1: Abnormal case Found
3775+ unsigned int tcp_opt : 1; // bit 27 1: Have TCP option
3776+ unsigned int ip_opt : 1; // bit 28 1: have IPV4 option or IPV6 Extension header
3777+ unsigned int sat : 1; // bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
3778+ unsigned int osq : 1; // bit 30 1: out of sequence
3779+ unsigned int ctl : 1; // bit 31 1: have control flag bits (except ack)
3780+ } bits;
3781+} INTR_QHDR1_T;
3782+
3783+/*
3784+ * Interrupt Queue Header Word 2
3785+ */
3786+typedef union {
3787+ unsigned int bits32;
3788+ unsigned int seq_num;
3789+} INTR_QHDR2_T;
3790+
3791+/*
3792+ * Interrupt Queue Header Word 3
3793+ */
3794+typedef union {
3795+ unsigned int bits32;
3796+ unsigned int ack_num;
3797+} INTR_QHDR3_T;
3798+
3799+/*
3800+ * Interrupt Queue Header Word 4
3801+ */
3802+typedef union {
3803+ unsigned int bits32;
3804+ struct bit_intrqhdr4 {
3805+ unsigned int AckCnt : 16; // bit 15:0 Ack# change since last ack# intr.
3806+ unsigned int SeqCnt : 16; // bit 31:16 Seq# change since last seq# intr.
3807+ } bits;
3808+} INTR_QHDR4_T;
3809+
3810+/*
3811+ * Interrupt Queue Header
3812+ */
3813+typedef struct {
3814+ INTR_QHDR0_T word0;
3815+ INTR_QHDR1_T word1;
3816+ INTR_QHDR2_T word2;
3817+ INTR_QHDR3_T word3;
3818+ INTR_QHDR4_T word4;
3819+ unsigned int word5;
3820+ unsigned int word6;
3821+ unsigned int word7;
3822+} INTR_QHDR_T;
3823+
3824+/*
3825+ * GMAC private data
3826+ */
3827+typedef struct {
3828+ unsigned int rwptr_reg;
3829+ unsigned int desc_base;
3830+ unsigned int desc_base_dma;
3831+ unsigned short finished_idx;
3832+ struct sk_buff *tx_skb[TOE_GMAC_SWTXQ_DESC_NUM];
3833+} GMAC_SWTXQ_T;
3834+
3835+struct gmac_private {
3836+ struct phy_device *phydev;
3837+ unsigned int port_id;
3838+ unsigned int dma_base_addr;
3839+ unsigned int swtxq_desc_base;
3840+ GMAC_SWTXQ_T swtxq[TOE_SW_TXQ_NUM];
3841+ NONTOE_QHDR_T *default_qhdr;
3842+ unsigned int default_desc_base;
3843+ dma_addr_t default_desc_base_dma;
3844+ dma_addr_t swtxq_desc_base_dma;
3845+ unsigned int flow_control_enable;
3846+ unsigned int intr0_enabled;
3847+ unsigned int intr1_enabled;
3848+ unsigned int intr2_enabled;
3849+ unsigned int intr3_enabled;
3850+ unsigned int intr4_enabled;
3851+ unsigned int intr0_selected;
3852+ unsigned int intr1_selected;
3853+ unsigned int intr2_selected;
3854+ unsigned int intr3_selected;
3855+ unsigned int intr4_selected;
3856+};
3857+
3858+struct toe_private {
3859+ void __iomem *global_base;
3860+ struct net_device *net_dev[2];
3861+ struct device *dev;
3862+ struct work_struct freq_work;
3863+ spinlock_t freeq_lock;
3864+ unsigned int swfq_desc_base;
3865+ unsigned int hwfq_desc_base;
3866+ unsigned int hwfq_buf_base;
3867+ dma_addr_t sw_freeq_desc_base_dma;
3868+ dma_addr_t hw_freeq_desc_base_dma;
3869+ dma_addr_t hwfq_buf_base_dma;
3870+ dma_addr_t hwfq_buf_end_dma;
3871+};
3872+
3873+#define GMAC_PORT0 0
3874+#define GMAC_PORT1 1
3875+
3876+#endif /* _GMAC_SL351x_H */
3877--- /dev/null
3878+++ b/drivers/net/gemini_negmac/Makefile
3879@@ -0,0 +1,3 @@
3880+obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC)+= gemini_negmac.o
3881+
3882+gemini_negmac-objs := gm_gmac.o
3883--- a/drivers/net/Kconfig
3884+++ b/drivers/net/Kconfig
3885@@ -2068,6 +2068,13 @@ config ACENIC_OMIT_TIGON_I
3886 
3887       The safe and default value for this is N.
3888 
3889+config GEMINI_NET_ENGINE_GMAC
3890+ tristate "Gemini Gigabit Ethernet support"
3891+ depends on ARCH_GEMINI
3892+ select PHYLIB
3893+ help
3894+ This driver supports Gemini TOE and NAT dual Gigabit Ethernet.
3895+
3896 config DL2K
3897     tristate "DL2000/TC902x-based Gigabit Ethernet support"
3898     depends on PCI
3899--- a/drivers/net/Makefile
3900+++ b/drivers/net/Makefile
3901@@ -257,6 +257,7 @@ obj-$(CONFIG_MLX4_CORE) += mlx4/
3902 obj-$(CONFIG_ENC28J60) += enc28j60.o
3903 obj-$(CONFIG_ETHOC) += ethoc.o
3904 obj-$(CONFIG_GRETH) += greth.o
3905+obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC) += gemini_negmac/
3906 
3907 obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
3908 
3909--- /dev/null
3910+++ b/drivers/usb/host/ehci-fotg2xx.c
3911@@ -0,0 +1,459 @@
3912+/*
3913+ * EHCI Host Controller driver
3914+ *
3915+ * Copyright (C) 2006 Sony Computer Entertainment Inc.
3916+ * Copyright 2006 Sony Corp.
3917+ *
3918+ * This program is free software; you can redistribute it and/or modify
3919+ * it under the terms of the GNU General Public License as published by
3920+ * the Free Software Foundation; version 2 of the License.
3921+ */
3922+
3923+#include <linux/platform_device.h>
3924+#include <mach/hardware.h>
3925+
3926+#define otg_set(port, bits) writel(readl(hcd->regs + port) | bits, hcd->regs + port)
3927+
3928+#define otg_clear(port, bits) writel(readl(hcd->regs + port) & ~bits, hcd->regs + port)
3929+
3930+#define GLOBAL_ISR 0xC0
3931+#define GLOBAL_ICR 0xC4
3932+
3933+#define HCD_MISC 0x40
3934+
3935+#define OTGC_SCR 0x80
3936+#define OTGC_INT_EN 0x88
3937+
3938+#define GLOBAL_INT_POLARITY (1 << 3)
3939+#define GLOBAL_INT_MASK_HC (1 << 2)
3940+#define GLOBAL_INT_MASK_OTG (1 << 1)
3941+#define GLOBAL_INT_MASK_DEV (1 << 0)
3942+
3943+#define OTGC_SCR_ID (1 << 21)
3944+#define OTGC_SCR_CROLE (1 << 20)
3945+#define OTGC_SCR_VBUS_VLD (1 << 19)
3946+#define OTGC_SCR_A_SRP_RESP_TYPE (1 << 8)
3947+#define OTGC_SCR_A_SRP_DET_EN (1 << 7)
3948+#define OTGC_SCR_A_SET_B_HNP_EN (1 << 6)
3949+#define OTGC_SCR_A_BUS_DROP (1 << 5)
3950+#define OTGC_SCR_A_BUS_REQ (1 << 4)
3951+
3952+#define OTGC_INT_APLGRMV (1 << 12)
3953+#define OTGC_INT_BPLGRMV (1 << 11)
3954+#define OTGC_INT_OVC (1 << 10)
3955+#define OTGC_INT_IDCHG (1 << 9)
3956+#define OTGC_INT_RLCHG (1 << 8)
3957+#define OTGC_INT_AVBUSERR (1 << 5)
3958+#define OTGC_INT_ASRPDET (1 << 4)
3959+#define OTGC_INT_BSRPDN (1 << 0)
3960+
3961+#define OTGC_INT_A_TYPE (OTGC_INT_ASRPDET|OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG|OTGC_INT_APLGRMV)
3962+#define OTGC_INT_B_TYPE (OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG)
3963+
3964+static void fotg2xx_otgc_role_change(struct usb_hcd *hcd);
3965+
3966+static void fotg2xx_otgc_init(struct usb_hcd *hcd)
3967+{
3968+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
3969+ unsigned int reg;
3970+
3971+ reg = __raw_readl(hcd->regs + OTGC_SCR);
3972+ ehci_info(ehci, "role detected: %s, ",
3973+ (reg & OTGC_SCR_CROLE) ? "Peripheral" : "Host");
3974+
3975+ if (reg & OTGC_SCR_ID)
3976+ ehci_info(ehci, "B-Device (may be unsupported!)\n");
3977+ else
3978+ ehci_info(ehci, "A-Device\n");
3979+
3980+ /* Enable the SRP detect */
3981+ reg &= ~OTGC_SCR_A_SRP_RESP_TYPE;
3982+ __raw_writel(reg, hcd->regs + OTGC_SCR);
3983+
3984+ reg = __raw_readl(hcd->regs + OTGC_INT_EN);
3985+ /* clear INT B: bits AVBUSERR | OVC | RLCHG | IDCHG */
3986+ reg &= ~OTGC_INT_B_TYPE;
3987+ /* set INT A: bits ASRPDET | AVBUSERR | OVC | RLCHG | IDCHG | APLGRMV */
3988+ reg |= OTGC_INT_A_TYPE;
3989+ __raw_writel(reg, hcd->regs + OTGC_INT_EN);
3990+
3991+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
3992+ reg &= ~GLOBAL_INT_MASK_OTG;
3993+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
3994+
3995+ /* setup MISC register, fixes timing problems */
3996+ reg = __raw_readl(hcd->regs + HCD_MISC);
3997+ reg |= 0xD;
3998+ __raw_writel(reg, hcd->regs + HCD_MISC);
3999+
4000+ fotg2xx_otgc_role_change(hcd);
4001+}
4002+
4003+static void fotg2xx_otgh_close(struct usb_hcd *hcd)
4004+{
4005+ unsigned int reg;
4006+
4007+ /* <1>.Enable Interrupt Mask */
4008+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
4009+ reg |= GLOBAL_INT_MASK_HC;
4010+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
4011+
4012+ /* <2>.Clear the Interrupt status */
4013+ reg = __raw_readl(hcd->regs + 0x18);
4014+ reg &= 0x0000003F;
4015+ __raw_writel(reg, hcd->regs + 0x14);
4016+}
4017+
4018+static void fotg2xx_otgh_open(struct usb_hcd *hcd)
4019+{
4020+ unsigned int reg;
4021+
4022+ reg = __raw_readl(hcd->regs + OTGC_SCR);
4023+ reg &= ~OTGC_SCR_A_SRP_DET_EN;
4024+ __raw_writel(reg, hcd->regs + OTGC_SCR);
4025+
4026+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
4027+ reg &= ~GLOBAL_INT_MASK_HC;
4028+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
4029+}
4030+
4031+/* change to host role */
4032+static void fotg2xx_otgc_role_change(struct usb_hcd *hcd)
4033+{
4034+
4035+ /* clear A_SET_B_HNP_EN */
4036+ otg_clear(0x80, BIT(6));
4037+
4038+ /*** Enable VBUS driving */
4039+ if (readl(hcd->regs + 0x80) & BIT(19))
4040+ printk(KERN_INFO "VBUS already enabled\n");
4041+ else {
4042+ int cnt = 0;
4043+
4044+ /* clear A_BUS_DROP */
4045+ otg_clear(0x80, BIT(5));
4046+
4047+ /* set A_BUS_REQ */
4048+ otg_set(0x80, BIT(4));
4049+
4050+ /* set global bus reg to VBUS on */
4051+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) | ((BIT(21)|BIT(22))),
4052+ IO_ADDRESS(0x40000000) + 0x30);
4053+
4054+ if (readl(hcd->regs + 0x80) & (1<<19)) {
4055+ printk(KERN_INFO "Waiting for VBus");
4056+ while (!(readl(hcd->regs + 0x80) & (1<<19)) && (cnt < 80)) {
4057+ printk(KERN_CONT ".");
4058+ cnt++;
4059+ }
4060+ printk(KERN_CONT "\n");
4061+ } else
4062+ printk(KERN_INFO "VBUS enabled.\n");
4063+
4064+ mdelay(1);
4065+ }
4066+ fotg2xx_otgh_open(hcd);
4067+}
4068+
4069+static int fotg2xx_ehci_hc_reset(struct usb_hcd *hcd)
4070+{
4071+ int result;
4072+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4073+
4074+ ehci->caps = hcd->regs;
4075+ ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
4076+
4077+ dbg_hcs_params(ehci, "reset");
4078+ dbg_hcc_params(ehci, "reset");
4079+
4080+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
4081+ hcd->has_tt = 1;
4082+
4083+ result = ehci_halt(ehci);
4084+ if (result)
4085+ return result;
4086+
4087+ result = ehci_init(hcd);
4088+ if (result)
4089+ return result;
4090+
4091+ ehci_port_power(ehci, 0);
4092+
4093+ return result;
4094+}
4095+
4096+/*
4097+ * Name: OTGC_INT_ISR
4098+ * Description:This interrupt service routine belongs to the OTG-Controller
4099+ * <1>.Check for ID_Change
4100+ * <2>.Check for RL_Change
4101+ * <3>.Error Detect
4102+ * Input: wINTStatus
4103+ * Output:void
4104+ */
4105+void fotg2xx_int_isr(struct usb_hcd *hcd, u32 wINTStatus)
4106+{
4107+ /* <1>.Check for ID_Change */
4108+ if (wINTStatus&OTGC_INT_IDCHG) {
4109+ if ((readl(hcd->regs + 0x80) & BIT(21)) != 0)
4110+ fotg2xx_otgc_init(hcd); /* Change to B Type */
4111+ else
4112+ fotg2xx_otgc_init(hcd); /* Change to A Type */
4113+
4114+ return;
4115+ }
4116+
4117+ /* <2>.Check for RL_Change */
4118+ if (wINTStatus&OTGC_INT_RLCHG)
4119+ fotg2xx_otgc_role_change(hcd);
4120+
4121+ /* <3>.Error Detect */
4122+ if (wINTStatus&OTGC_INT_AVBUSERR)
4123+ printk(KERN_ERR "VBus error!\n");
4124+
4125+ if (wINTStatus&OTGC_INT_OVC)
4126+ printk(KERN_WARNING "Overcurrent detected!\n");
4127+
4128+ /* <3>.Check for Type-A/Type-B Interrupt */
4129+ if ((readl(hcd->regs + 0x80) & BIT(21)) == 0) { /*For Type-A Interrupt*/
4130+ if (wINTStatus & (OTGC_INT_A_TYPE | OTGC_INT_ASRPDET)) {
4131+ /* <1>.SRP detected => then set global variable */
4132+ printk(KERN_WARNING "SRP detected, but not implemented!\n");
4133+
4134+#if 0
4135+ u32 wTempCounter;
4136+ /* <2>.Turn on the V Bus */
4137+ pFTC_OTG->otg.state = OTG_STATE_A_WAIT_VRISE;
4138+ OTGC_enable_vbus_draw_storlink(1);
4139+ pFTC_OTG->otg.state = OTG_STATE_A_HOST;
4140+ /* <3>.Should waiting for Device-Connect Wait 300ms */
4141+ INFO(pFTC_OTG, ">>> OTG-A Waiting for OTG-B Connect,\n");
4142+ wTempCounter = 0;
4143+ while (mwHost20_PORTSC_ConnectStatus_Rd() == 0) {
4144+ mdelay(1);
4145+ wTempCounter++;
4146+ /* Waiting for 300 ms */
4147+ if (wTempCounter > 300) {
4148+ mdwOTGC_Control_A_SRP_DET_EN_Clr();
4149+ INFO(pFTC_OTG, ">>> OTG-B do not connect under 300 ms...\n");
4150+ break;
4151+ }
4152+ }
4153+ /* <4>.If Connect => issue quick Reset */
4154+ if (mwHost20_PORTSC_ConnectStatus_Rd() > 0) {
4155+ mdelay(300); /* For OPT-A Test */
4156+ OTGH_host_quick_Reset();
4157+ OTGH_Open();
4158+ pFTC_OTG->otg.host->A_Disable_Set_Feature_HNP = 0;
4159+ }
4160+#endif
4161+ }
4162+ } else { /* For Type-B Interrupt */
4163+ BUG();
4164+ }
4165+}
4166+
4167+static irqreturn_t fotg2xx_ehci_irq(int irq, void *devid)
4168+{
4169+ struct usb_hcd *hcd = devid;
4170+ u32 val;
4171+
4172+ /* OTG Interrupt Status Register */
4173+ val = readl(hcd->regs + 0x84);
4174+
4175+ /* OTG stuff */
4176+ if (val) {
4177+ /* supposed to do "INT STS Clr" - XXX */
4178+ writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
4179+
4180+ fotg2xx_int_isr(hcd, val);
4181+
4182+ /* supposed to do "INT STS Clr" - XXX */
4183+ writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
4184+
4185+ return IRQ_HANDLED;
4186+ }
4187+
4188+ if ((readl(hcd->regs + 0x80) & BIT(20)) == 0) { /* Role is HOST */
4189+ if (readl(hcd->regs + 0xC0) & BIT(2)) { /* INT STS HOST */
4190+ /* leave this for ehci irq handler */
4191+ return IRQ_NONE;
4192+ }
4193+ } else
4194+ printk(KERN_WARNING
4195+ "received irq for peripheral - don't know what to do!\n");
4196+
4197+ /* do not call the ehci irq handler */
4198+ return IRQ_HANDLED;
4199+}
4200+
4201+static int fotg2xx_ehci_run(struct usb_hcd *hcd)
4202+{
4203+ int retval;
4204+
4205+ retval = ehci_run(hcd);
4206+
4207+ fotg2xx_otgh_close(hcd);
4208+ fotg2xx_otgc_init(hcd);
4209+
4210+ return retval;
4211+}
4212+
4213+static const struct hc_driver fotg2xx_ehci_hc_driver = {
4214+ .description = hcd_name,
4215+ .product_desc = "FOTG2XX EHCI Host Controller",
4216+ .hcd_priv_size = sizeof(struct ehci_hcd),
4217+ .irq = ehci_irq,
4218+ .flags = HCD_MEMORY | HCD_USB2,
4219+ .reset = fotg2xx_ehci_hc_reset,
4220+ .start = fotg2xx_ehci_run,
4221+ .stop = ehci_stop,
4222+ .shutdown = ehci_shutdown,
4223+ .urb_enqueue = ehci_urb_enqueue,
4224+ .urb_dequeue = ehci_urb_dequeue,
4225+ .endpoint_disable = ehci_endpoint_disable,
4226+ .get_frame_number = ehci_get_frame,
4227+ .hub_status_data = ehci_hub_status_data,
4228+ .hub_control = ehci_hub_control,
4229+#if defined(CONFIG_PM)
4230+ .bus_suspend = ehci_bus_suspend,
4231+ .bus_resume = ehci_bus_resume,
4232+#endif
4233+ .relinquish_port = ehci_relinquish_port,
4234+ .port_handed_over = ehci_port_handed_over,
4235+};
4236+
4237+static int fotg2xx_ehci_probe(struct platform_device *pdev)
4238+{
4239+ const struct hc_driver *driver = &fotg2xx_ehci_hc_driver;
4240+ struct usb_hcd *hcd;
4241+ struct resource *res;
4242+ int irq;
4243+ int retval;
4244+
4245+ pr_debug("initializing FOTG2XX-SOC USB Controller\n");
4246+
4247+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
4248+ if (!res) {
4249+ dev_err(&pdev->dev,
4250+ "Found HC with no IRQ. Check %s setup!\n",
4251+ dev_name(&pdev->dev));
4252+ return -ENODEV;
4253+ }
4254+
4255+ irq = res->start;
4256+
4257+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4258+ if (!hcd) {
4259+ retval = -ENOMEM;
4260+ goto err1;
4261+ }
4262+
4263+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4264+ if (!res) {
4265+ dev_err(&pdev->dev,
4266+ "Found HC with no register addr. Check %s setup!\n",
4267+ dev_name(&pdev->dev));
4268+ retval = -ENODEV;
4269+ goto err2;
4270+ }
4271+
4272+ hcd->rsrc_start = res->start;
4273+ hcd->rsrc_len = res->end - res->start + 1;
4274+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
4275+ driver->description)) {
4276+ dev_dbg(&pdev->dev, "controller already in use\n");
4277+ retval = -EBUSY;
4278+ goto err2;
4279+ }
4280+
4281+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
4282+ if (hcd->regs == NULL) {
4283+ dev_dbg(&pdev->dev, "error mapping memory\n");
4284+ retval = -EFAULT;
4285+ goto err3;
4286+ }
4287+
4288+
4289+ /* set global reg to mini-A host */
4290+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(30)|BIT(29)),
4291+ IO_ADDRESS(0x40000000) + 0x30);
4292+
4293+ /* USB0&USB1 - VBUS off */
4294+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(21)|BIT(22)),
4295+ IO_ADDRESS(0x40000000) + 0x30);
4296+
4297+ if ((readl(hcd->regs) == 0x01000010) &&
4298+ (readl(hcd->regs + 4) == 0x00000001) &&
4299+ (readl(hcd->regs + 8) == 0x00000006)) {
4300+ dev_info(&pdev->dev,
4301+ "Found Faraday OTG 2XX controller (base = 0x%08lX)\n",
4302+ (unsigned long) hcd->rsrc_start);
4303+ } else {
4304+ dev_err(&pdev->dev, "fotg2xx id mismatch: found %d.%d.%d\n",
4305+ readl(hcd->regs + 0x00),
4306+ readl(hcd->regs + 0x04),
4307+ readl(hcd->regs + 0x08));
4308+ retval = -ENODEV;
4309+ goto err4;
4310+ }
4311+
4312+ platform_set_drvdata(pdev, hcd);
4313+
4314+ /* mask interrupts - peripheral, otg, host, hi-active (bits 0,1,2,3) */
4315+ otg_set(0xc4, BIT(3)); /* hi active */
4316+
4317+ otg_set(0xc4, BIT(2)); /* host */
4318+ otg_set(0xc4, BIT(1)); /* otg */
4319+ otg_set(0xc4, BIT(0)); /* peripheral */
4320+
4321+ /* register additional interrupt - here we check otg status */
4322+ if ((request_irq(irq, &fotg2xx_ehci_irq, IRQF_SHARED | IRQF_DISABLED,
4323+ hcd->irq_descr, hcd)) != 0) {
4324+ dev_dbg(&pdev->dev, "error requesting irq %d\n", irq);
4325+ retval = -EFAULT;
4326+ goto err4;
4327+ }
4328+
4329+ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
4330+ if (retval != 0)
4331+ goto err4;
4332+ return retval;
4333+
4334+err4:
4335+ iounmap(hcd->regs);
4336+err3:
4337+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
4338+err2:
4339+ usb_put_hcd(hcd);
4340+err1:
4341+ dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
4342+ return retval;
4343+}
4344+
4345+/* may be called without controller electrically present */
4346+/* may be called with controller, bus, and devices active */
4347+
4348+int fotg2xx_ehci_remove(struct platform_device *pdev)
4349+{
4350+ struct usb_hcd *hcd =
4351+ (struct usb_hcd *)platform_get_drvdata(pdev);
4352+
4353+ usb_remove_hcd(hcd);
4354+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
4355+ iounmap(hcd->regs);
4356+ usb_put_hcd(hcd);
4357+ platform_set_drvdata(pdev, NULL);
4358+
4359+ return 0;
4360+}
4361+
4362+MODULE_ALIAS("platform:ehci-fotg2xx");
4363+
4364+static struct platform_driver fotg2xx_ehci_driver = {
4365+ .probe = fotg2xx_ehci_probe,
4366+ .remove = fotg2xx_ehci_remove,
4367+ .driver = {
4368+ .name = "ehci-fotg2xx",
4369+ },
4370+};
4371--- a/drivers/usb/host/ehci.h
4372+++ b/drivers/usb/host/ehci.h
4373@@ -561,7 +561,12 @@ static inline unsigned int
4374 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
4375 {
4376     if (ehci_is_TDI(ehci)) {
4377+#ifdef CONFIG_ARCH_GEMINI
4378+ portsc = readl(ehci_to_hcd(ehci)->regs + 0x80);
4379+ switch ((portsc>>22)&3) {
4380+#else
4381         switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
4382+#endif
4383         case 0:
4384             return 0;
4385         case 1:
4386--- a/drivers/usb/host/ehci-hcd.c
4387+++ b/drivers/usb/host/ehci-hcd.c
4388@@ -223,9 +223,11 @@ static int ehci_halt (struct ehci_hcd *e
4389     if ((temp & STS_HALT) != 0)
4390         return 0;
4391 
4392+#ifndef CONFIG_ARCH_GEMINI
4393     temp = ehci_readl(ehci, &ehci->regs->command);
4394     temp &= ~CMD_RUN;
4395     ehci_writel(ehci, temp, &ehci->regs->command);
4396+#endif
4397     return handshake (ehci, &ehci->regs->status,
4398               STS_HALT, STS_HALT, 16 * 125);
4399 }
4400@@ -292,8 +294,8 @@ static int ehci_reset (struct ehci_hcd *
4401     if (retval)
4402         return retval;
4403 
4404- if (ehci_is_TDI(ehci))
4405- tdi_reset (ehci);
4406+// if (ehci_is_TDI(ehci))
4407+// tdi_reset (ehci);
4408 
4409     if (ehci->debug)
4410         dbgp_external_startup();
4411@@ -427,12 +429,13 @@ static void ehci_silence_controller(stru
4412 {
4413     ehci_halt(ehci);
4414     ehci_turn_off_all_ports(ehci);
4415-
4416+#ifndef CONFIG_ARCH_GEMINI
4417     /* make BIOS/etc use companion controller during reboot */
4418     ehci_writel(ehci, 0, &ehci->regs->configured_flag);
4419 
4420     /* unblock posted writes */
4421     ehci_readl(ehci, &ehci->regs->configured_flag);
4422+#endif
4423 }
4424 
4425 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
4426@@ -712,7 +715,9 @@ static int ehci_run (struct usb_hcd *hcd
4427     // Philips, Intel, and maybe others need CMD_RUN before the
4428     // root hub will detect new devices (why?); NEC doesn't
4429     ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
4430+#ifndef CONFIG_ARCH_GEMINI
4431     ehci->command |= CMD_RUN;
4432+#endif
4433     ehci_writel(ehci, ehci->command, &ehci->regs->command);
4434     dbg_cmd (ehci, "init", ehci->command);
4435 
4436@@ -732,9 +737,11 @@ static int ehci_run (struct usb_hcd *hcd
4437      */
4438     down_write(&ehci_cf_port_reset_rwsem);
4439     hcd->state = HC_STATE_RUNNING;
4440+#ifndef CONFIG_ARCH_GEMINI
4441     ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
4442     ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
4443     msleep(5);
4444+#endif
4445     up_write(&ehci_cf_port_reset_rwsem);
4446     ehci->last_periodic_enable = ktime_get_real();
4447 
4448@@ -827,9 +834,10 @@ static irqreturn_t ehci_irq (struct usb_
4449         pcd_status = status;
4450 
4451         /* resume root hub? */
4452+#ifndef CONFIG_ARCH_GEMINI
4453         if (!(cmd & CMD_RUN))
4454             usb_hcd_resume_root_hub(hcd);
4455-
4456+#endif
4457         /* get per-port change detect bits */
4458         if (ehci->has_ppcd)
4459             ppcd = status >> 16;
4460@@ -871,7 +879,9 @@ static irqreturn_t ehci_irq (struct usb_
4461         ehci_halt(ehci);
4462 dead:
4463         ehci_reset(ehci);
4464+#ifndef CONFIG_ARCH_GEMINI
4465         ehci_writel(ehci, 0, &ehci->regs->configured_flag);
4466+#endif
4467         /* generic layer kills/unlinks all urbs, then
4468          * uses ehci_stop to clean up the rest
4469          */
4470@@ -1169,6 +1179,11 @@ MODULE_LICENSE ("GPL");
4471 #define PCI_DRIVER ehci_pci_driver
4472 #endif
4473 
4474+#ifdef CONFIG_ARCH_GEMINI
4475+#include "ehci-fotg2xx.c"
4476+#define PLATFORM_DRIVER fotg2xx_ehci_driver
4477+#endif
4478+
4479 #ifdef CONFIG_USB_EHCI_FSL
4480 #include "ehci-fsl.c"
4481 #define PLATFORM_DRIVER ehci_fsl_driver
4482--- a/drivers/usb/host/ehci-hub.c
4483+++ b/drivers/usb/host/ehci-hub.c
4484@@ -929,6 +929,12 @@ static int ehci_hub_control (
4485             /* see what we found out */
4486             temp = check_reset_complete (ehci, wIndex, status_reg,
4487                     ehci_readl(ehci, status_reg));
4488+#ifdef CONFIG_ARCH_GEMINI
4489+ /* restart schedule */
4490+ ehci_writel(ehci, ehci_readl(ehci, &ehci->regs->command) | CMD_RUN, &ehci->regs->command);
4491+
4492+// hcd->state = HC_STATE_RUNNING;
4493+#endif
4494         }
4495 
4496         if (!(temp & (PORT_RESUME|PORT_RESET)))
4497--- a/drivers/usb/Kconfig
4498+++ b/drivers/usb/Kconfig
4499@@ -66,6 +66,7 @@ config USB_ARCH_HAS_EHCI
4500     default y if ARCH_AT91SAM9G45
4501     default y if ARCH_MXC
4502     default y if ARCH_OMAP3
4503+ default y if ARCH_GEMINI
4504     default PCI
4505 
4506 # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
4507--- /dev/null
4508+++ b/drivers/watchdog/gemini_wdt.c
4509@@ -0,0 +1,368 @@
4510+/*
4511+ * Watchdog driver for Cortina Systems Gemini SoC
4512+ *
4513+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4514+ *
4515+ * This program is free software; you can redistribute it and/or modify
4516+ * it under the terms of the GNU General Public License version 2 as
4517+ * published by the Free Software Foundation.
4518+ */
4519+
4520+#include <linux/kernel.h>
4521+#include <linux/init.h>
4522+#include <linux/io.h>
4523+#include <linux/fs.h>
4524+#include <linux/uaccess.h>
4525+#include <linux/miscdevice.h>
4526+#include <linux/platform_device.h>
4527+#include <linux/watchdog.h>
4528+#include <linux/slab.h>
4529+
4530+#define GEMINI_WDCOUNTER 0x0
4531+#define GEMINI_WDLOAD 0x4
4532+#define GEMINI_WDRESTART 0x8
4533+
4534+#define WDRESTART_MAGIC 0x5AB9
4535+
4536+#define GEMINI_WDCR 0xC
4537+
4538+#define WDCR_CLOCK_5MHZ (1 << 4)
4539+#define WDCR_SYS_RST (1 << 1)
4540+#define WDCR_ENABLE (1 << 0)
4541+
4542+#define WDT_CLOCK 5000000 /* 5 MHz */
4543+#define WDT_DEFAULT_TIMEOUT 13
4544+#define WDT_MAX_TIMEOUT (0xFFFFFFFF / WDT_CLOCK)
4545+
4546+/* status bits */
4547+#define WDT_ACTIVE 0
4548+#define WDT_OK_TO_CLOSE 1
4549+
4550+static unsigned int timeout = WDT_DEFAULT_TIMEOUT;
4551+static int nowayout = WATCHDOG_NOWAYOUT;
4552+
4553+static DEFINE_SPINLOCK(gemini_wdt_lock);
4554+
4555+static struct platform_device *gemini_wdt_dev;
4556+
4557+struct gemini_wdt_struct {
4558+ struct resource *res;
4559+ struct device *dev;
4560+ void __iomem *base;
4561+ unsigned long status;
4562+};
4563+
4564+static struct watchdog_info gemini_wdt_info = {
4565+ .identity = "Gemini watchdog",
4566+ .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
4567+ WDIOF_SETTIMEOUT,
4568+};
4569+
4570+/* Disable the watchdog. */
4571+static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt)
4572+{
4573+ spin_lock(&gemini_wdt_lock);
4574+
4575+ __raw_writel(0, gemini_wdt->base + GEMINI_WDCR);
4576+
4577+ clear_bit(WDT_ACTIVE, &gemini_wdt->status);
4578+
4579+ spin_unlock(&gemini_wdt_lock);
4580+}
4581+
4582+/* Service the watchdog */
4583+static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt)
4584+{
4585+ __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART);
4586+}
4587+
4588+/* Enable and reset the watchdog. */
4589+static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt)
4590+{
4591+ spin_lock(&gemini_wdt_lock);
4592+
4593+ __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD);
4594+
4595+ gemini_wdt_service(gemini_wdt);
4596+
4597+ /* set clock before enabling */
4598+ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
4599+ gemini_wdt->base + GEMINI_WDCR);
4600+
4601+ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
4602+ gemini_wdt->base + GEMINI_WDCR);
4603+
4604+ set_bit(WDT_ACTIVE, &gemini_wdt->status);
4605+
4606+ spin_unlock(&gemini_wdt_lock);
4607+}
4608+
4609+/* Watchdog device is opened, and watchdog starts running. */
4610+static int gemini_wdt_open(struct inode *inode, struct file *file)
4611+{
4612+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev);
4613+
4614+ if (test_bit(WDT_ACTIVE, &gemini_wdt->status))
4615+ return -EBUSY;
4616+
4617+ file->private_data = gemini_wdt;
4618+
4619+ gemini_wdt_start(gemini_wdt);
4620+
4621+ return nonseekable_open(inode, file);
4622+}
4623+
4624+/* Close the watchdog device. */
4625+static int gemini_wdt_close(struct inode *inode, struct file *file)
4626+{
4627+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
4628+
4629+ /* Disable the watchdog if possible */
4630+ if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status))
4631+ gemini_wdt_stop(gemini_wdt);
4632+ else
4633+ dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n");
4634+
4635+ return 0;
4636+}
4637+
4638+/* Handle commands from user-space. */
4639+static int gemini_wdt_ioctl(struct inode *inode, struct file *file,
4640+ unsigned int cmd, unsigned long arg)
4641+{
4642+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
4643+
4644+ int value;
4645+
4646+ switch (cmd) {
4647+ case WDIOC_KEEPALIVE:
4648+ gemini_wdt_service(gemini_wdt);
4649+ return 0;
4650+
4651+ case WDIOC_GETSUPPORT:
4652+ return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info,
4653+ sizeof(gemini_wdt_info)) ? -EFAULT : 0;
4654+
4655+ case WDIOC_SETTIMEOUT:
4656+ if (get_user(value, (int *)arg))
4657+ return -EFAULT;
4658+
4659+ if ((value < 1) || (value > WDT_MAX_TIMEOUT))
4660+ return -EINVAL;
4661+
4662+ timeout = value;
4663+
4664+ /* restart wdt to use new timeout */
4665+ gemini_wdt_stop(gemini_wdt);
4666+ gemini_wdt_start(gemini_wdt);
4667+
4668+ /* Fall through */
4669+ case WDIOC_GETTIMEOUT:
4670+ return put_user(timeout, (int *)arg);
4671+
4672+ case WDIOC_GETTIMELEFT:
4673+ value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER);
4674+ return put_user(value / WDT_CLOCK, (int *)arg);
4675+
4676+ default:
4677+ return -ENOTTY;
4678+ }
4679+}
4680+
4681+/* Refresh the watchdog whenever device is written to. */
4682+static ssize_t gemini_wdt_write(struct file *file, const char *data,
4683+ size_t len, loff_t *ppos)
4684+{
4685+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
4686+
4687+ if (len) {
4688+ if (!nowayout) {
4689+ size_t i;
4690+
4691+ clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status);
4692+ for (i = 0; i != len; i++) {
4693+ char c;
4694+
4695+ if (get_user(c, data + i))
4696+ return -EFAULT;
4697+ if (c == 'V')
4698+ set_bit(WDT_OK_TO_CLOSE,
4699+ &gemini_wdt->status);
4700+ }
4701+ }
4702+ gemini_wdt_service(gemini_wdt);
4703+ }
4704+
4705+ return len;
4706+}
4707+
4708+static const struct file_operations gemini_wdt_fops = {
4709+ .owner = THIS_MODULE,
4710+ .llseek = no_llseek,
4711+ .open = gemini_wdt_open,
4712+ .release = gemini_wdt_close,
4713+ .write = gemini_wdt_write,
4714+};
4715+
4716+static struct miscdevice gemini_wdt_miscdev = {
4717+ .minor = WATCHDOG_MINOR,
4718+ .name = "watchdog",
4719+ .fops = &gemini_wdt_fops,
4720+};
4721+
4722+static void gemini_wdt_shutdown(struct platform_device *pdev)
4723+{
4724+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
4725+
4726+ gemini_wdt_stop(gemini_wdt);
4727+}
4728+
4729+static int __init gemini_wdt_probe(struct platform_device *pdev)
4730+{
4731+ int ret;
4732+ int res_size;
4733+ struct resource *res;
4734+ void __iomem *base;
4735+ struct gemini_wdt_struct *gemini_wdt;
4736+
4737+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4738+ if (!res) {
4739+ dev_err(&pdev->dev, "can't get device resources\n");
4740+ return -ENODEV;
4741+ }
4742+
4743+ res_size = resource_size(res);
4744+ if (!request_mem_region(res->start, res_size, res->name)) {
4745+ dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
4746+ res_size, res->start);
4747+ return -ENOMEM;
4748+ }
4749+
4750+ base = ioremap(res->start, res_size);
4751+ if (!base) {
4752+ dev_err(&pdev->dev, "ioremap failed\n");
4753+ ret = -EIO;
4754+ goto fail0;
4755+ }
4756+
4757+ gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL);
4758+ if (!gemini_wdt) {
4759+ dev_err(&pdev->dev, "can't allocate interface\n");
4760+ ret = -ENOMEM;
4761+ goto fail1;
4762+ }
4763+
4764+ /* Setup gemini_wdt driver structure */
4765+ gemini_wdt->base = base;
4766+ gemini_wdt->res = res;
4767+
4768+ /* Set up platform driver data */
4769+ platform_set_drvdata(pdev, gemini_wdt);
4770+ gemini_wdt_dev = pdev;
4771+
4772+ if (gemini_wdt_miscdev.parent) {
4773+ ret = -EBUSY;
4774+ goto fail2;
4775+ }
4776+
4777+ gemini_wdt_miscdev.parent = &pdev->dev;
4778+
4779+ ret = misc_register(&gemini_wdt_miscdev);
4780+ if (ret)
4781+ goto fail2;
4782+
4783+ return 0;
4784+
4785+fail2:
4786+ platform_set_drvdata(pdev, NULL);
4787+ kfree(gemini_wdt);
4788+fail1:
4789+ iounmap(base);
4790+fail0:
4791+ release_mem_region(res->start, res_size);
4792+
4793+ return ret;
4794+}
4795+
4796+static int __exit gemini_wdt_remove(struct platform_device *pdev)
4797+{
4798+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
4799+
4800+ platform_set_drvdata(pdev, NULL);
4801+ misc_deregister(&gemini_wdt_miscdev);
4802+ gemini_wdt_dev = NULL;
4803+ iounmap(gemini_wdt->base);
4804+ release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res));
4805+
4806+ kfree(gemini_wdt);
4807+
4808+ return 0;
4809+}
4810+
4811+#ifdef CONFIG_PM
4812+static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message)
4813+{
4814+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
4815+ unsigned int reg;
4816+
4817+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
4818+ reg &= ~(WDCR_WDENABLE);
4819+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
4820+
4821+ return 0;
4822+}
4823+
4824+static int gemini_wdt_resume(struct platform_device *pdev)
4825+{
4826+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
4827+ unsigned int reg;
4828+
4829+ if (gemini_wdt->status) {
4830+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
4831+ reg |= WDCR_WDENABLE;
4832+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
4833+ }
4834+
4835+ return 0;
4836+}
4837+#else
4838+#define gemini_wdt_suspend NULL
4839+#define gemini_wdt_resume NULL
4840+#endif
4841+
4842+static struct platform_driver gemini_wdt_driver = {
4843+ .probe = gemini_wdt_probe,
4844+ .remove = __exit_p(gemini_wdt_remove),
4845+ .shutdown = gemini_wdt_shutdown,
4846+ .suspend = gemini_wdt_suspend,
4847+ .resume = gemini_wdt_resume,
4848+ .driver = {
4849+ .name = "gemini-wdt",
4850+ .owner = THIS_MODULE,
4851+ },
4852+};
4853+
4854+static int __init gemini_wdt_init(void)
4855+{
4856+ return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe);
4857+}
4858+
4859+static void __exit gemini_wdt_exit(void)
4860+{
4861+ platform_driver_unregister(&gemini_wdt_driver);
4862+}
4863+
4864+module_init(gemini_wdt_init);
4865+module_exit(gemini_wdt_exit);
4866+
4867+module_param(timeout, uint, 0);
4868+MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
4869+
4870+module_param(nowayout, int, 0);
4871+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
4872+
4873+MODULE_AUTHOR("Paulius Zaleckas");
4874+MODULE_DESCRIPTION("Watchdog driver for Gemini");
4875+MODULE_LICENSE("GPL");
4876+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
4877+MODULE_ALIAS("platform:gemini-wdt");
4878--- a/drivers/watchdog/Kconfig
4879+++ b/drivers/watchdog/Kconfig
4880@@ -118,6 +118,16 @@ config 977_WATCHDOG
4881 
4882       Not sure? It's safe to say N.
4883 
4884+config GEMINI_WATCHDOG
4885+ tristate "Gemini watchdog"
4886+ depends on ARCH_GEMINI
4887+ help
4888+ Say Y here if to include support for the watchdog timer
4889+ embedded in the Cortina Systems Gemini family of devices.
4890+
4891+ To compile this driver as a module, choose M here: the
4892+ module will be called gemini_wdt.
4893+
4894 config IXP2000_WATCHDOG
4895     tristate "IXP2000 Watchdog"
4896     depends on ARCH_IXP2000
4897--- a/drivers/watchdog/Makefile
4898+++ b/drivers/watchdog/Makefile
4899@@ -32,6 +32,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.
4900 obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o
4901 obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
4902 obj-$(CONFIG_977_WATCHDOG) += wdt977.o
4903+obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
4904 obj-$(CONFIG_IXP2000_WATCHDOG) += ixp2000_wdt.o
4905 obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
4906 obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
4907--- a/include/linux/usb/ehci_def.h
4908+++ b/include/linux/usb/ehci_def.h
4909@@ -105,9 +105,9 @@ struct ehci_regs {
4910     u32 frame_list; /* points to periodic list */
4911     /* ASYNCLISTADDR: offset 0x18 */
4912     u32 async_next; /* address of next async queue head */
4913-
4914+#ifndef CONFIG_ARCH_GEMINI
4915     u32 reserved[9];
4916-
4917+#endif
4918     /* CONFIGFLAG: offset 0x40 */
4919     u32 configured_flag;
4920 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
4921--- a/arch/arm/mm/Kconfig
4922+++ b/arch/arm/mm/Kconfig
4923@@ -806,6 +806,7 @@ config CACHE_XSC3L2
4924 
4925 config ARM_L1_CACHE_SHIFT
4926     int
4927+ default 4 if CPU_FA526
4928     default 6 if ARM_L1_CACHE_SHIFT_6
4929     default 5
4930 
4931--- a/arch/arm/lib/copy_page.S
4932+++ b/arch/arm/lib/copy_page.S
4933@@ -17,7 +17,7 @@
4934 #define COPY_COUNT (PAGE_SZ / (2 * L1_CACHE_BYTES) PLD( -1 ))
4935 
4936         .text
4937- .align 5
4938+ .align L1_CACHE_SHIFT
4939 /*
4940  * StrongARM optimised copy_page routine
4941  * now 1.78bytes/cycle, was 1.60 bytes/cycle (50MHz bus -> 89MB/s)
4942

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