| 1 | /* |
| 2 | * ar8216.h: AR8216 switch driver |
| 3 | * |
| 4 | * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef __AR8216_H |
| 18 | #define __AR8216_H |
| 19 | |
| 20 | #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) |
| 21 | |
| 22 | #define AR8216_PORT_CPU 0 |
| 23 | #define AR8216_NUM_PORTS 6 |
| 24 | #define AR8216_NUM_VLANS 16 |
| 25 | #define AR8316_NUM_VLANS 4096 |
| 26 | |
| 27 | /* Atheros specific MII registers */ |
| 28 | #define MII_ATH_DBG_ADDR 0x1d |
| 29 | #define MII_ATH_DBG_DATA 0x1e |
| 30 | |
| 31 | #define AR8216_REG_CTRL 0x0000 |
| 32 | #define AR8216_CTRL_REVISION BITS(0, 8) |
| 33 | #define AR8216_CTRL_REVISION_S 0 |
| 34 | #define AR8216_CTRL_VERSION BITS(8, 8) |
| 35 | #define AR8216_CTRL_VERSION_S 8 |
| 36 | #define AR8216_CTRL_RESET BIT(31) |
| 37 | |
| 38 | #define AR8216_REG_FLOOD_MASK 0x002C |
| 39 | #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6) |
| 40 | #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6) |
| 41 | |
| 42 | #define AR8216_REG_GLOBAL_CTRL 0x0030 |
| 43 | #define AR8216_GCTRL_MTU BITS(0, 11) |
| 44 | #define AR8236_GCTRL_MTU BITS(0, 14) |
| 45 | #define AR8316_GCTRL_MTU BITS(0, 14) |
| 46 | |
| 47 | #define AR8216_REG_VTU 0x0040 |
| 48 | #define AR8216_VTU_OP BITS(0, 3) |
| 49 | #define AR8216_VTU_OP_NOOP 0x0 |
| 50 | #define AR8216_VTU_OP_FLUSH 0x1 |
| 51 | #define AR8216_VTU_OP_LOAD 0x2 |
| 52 | #define AR8216_VTU_OP_PURGE 0x3 |
| 53 | #define AR8216_VTU_OP_REMOVE_PORT 0x4 |
| 54 | #define AR8216_VTU_ACTIVE BIT(3) |
| 55 | #define AR8216_VTU_FULL BIT(4) |
| 56 | #define AR8216_VTU_PORT BITS(8, 4) |
| 57 | #define AR8216_VTU_PORT_S 8 |
| 58 | #define AR8216_VTU_VID BITS(16, 12) |
| 59 | #define AR8216_VTU_VID_S 16 |
| 60 | #define AR8216_VTU_PRIO BITS(28, 3) |
| 61 | #define AR8216_VTU_PRIO_S 28 |
| 62 | #define AR8216_VTU_PRIO_EN BIT(31) |
| 63 | |
| 64 | #define AR8216_REG_VTU_DATA 0x0044 |
| 65 | #define AR8216_VTUDATA_MEMBER BITS(0, 10) |
| 66 | #define AR8236_VTUDATA_MEMBER BITS(0, 7) |
| 67 | #define AR8216_VTUDATA_VALID BIT(11) |
| 68 | |
| 69 | #define AR8216_REG_ATU 0x0050 |
| 70 | #define AR8216_ATU_OP BITS(0, 3) |
| 71 | #define AR8216_ATU_OP_NOOP 0x0 |
| 72 | #define AR8216_ATU_OP_FLUSH 0x1 |
| 73 | #define AR8216_ATU_OP_LOAD 0x2 |
| 74 | #define AR8216_ATU_OP_PURGE 0x3 |
| 75 | #define AR8216_ATU_OP_FLUSH_LOCKED 0x4 |
| 76 | #define AR8216_ATU_OP_FLUSH_UNICAST 0x5 |
| 77 | #define AR8216_ATU_OP_GET_NEXT 0x6 |
| 78 | #define AR8216_ATU_ACTIVE BIT(3) |
| 79 | #define AR8216_ATU_PORT_NUM BITS(8, 4) |
| 80 | #define AR8216_ATU_FULL_VIO BIT(12) |
| 81 | #define AR8216_ATU_ADDR4 BITS(16, 8) |
| 82 | #define AR8216_ATU_ADDR5 BITS(24, 8) |
| 83 | |
| 84 | #define AR8216_REG_ATU_DATA 0x0054 |
| 85 | #define AR8216_ATU_ADDR3 BITS(0, 8) |
| 86 | #define AR8216_ATU_ADDR2 BITS(8, 8) |
| 87 | #define AR8216_ATU_ADDR1 BITS(16, 8) |
| 88 | #define AR8216_ATU_ADDR0 BITS(24, 8) |
| 89 | |
| 90 | #define AR8216_REG_ATU_CTRL 0x005C |
| 91 | #define AR8216_ATU_CTRL_AGE_EN BIT(17) |
| 92 | #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) |
| 93 | #define AR8216_ATU_CTRL_AGE_TIME_S 0 |
| 94 | |
| 95 | #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1)) |
| 96 | #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000) |
| 97 | #define AR8216_PORT_STATUS_SPEED BITS(0,2) |
| 98 | #define AR8216_PORT_STATUS_SPEED_S 0 |
| 99 | #define AR8216_PORT_STATUS_TXMAC BIT(2) |
| 100 | #define AR8216_PORT_STATUS_RXMAC BIT(3) |
| 101 | #define AR8216_PORT_STATUS_TXFLOW BIT(4) |
| 102 | #define AR8216_PORT_STATUS_RXFLOW BIT(5) |
| 103 | #define AR8216_PORT_STATUS_DUPLEX BIT(6) |
| 104 | #define AR8216_PORT_STATUS_LINK_UP BIT(8) |
| 105 | #define AR8216_PORT_STATUS_LINK_AUTO BIT(9) |
| 106 | #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10) |
| 107 | |
| 108 | #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004) |
| 109 | |
| 110 | /* port forwarding state */ |
| 111 | #define AR8216_PORT_CTRL_STATE BITS(0, 3) |
| 112 | #define AR8216_PORT_CTRL_STATE_S 0 |
| 113 | |
| 114 | #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7) |
| 115 | |
| 116 | /* egress 802.1q mode */ |
| 117 | #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2) |
| 118 | #define AR8216_PORT_CTRL_VLAN_MODE_S 8 |
| 119 | |
| 120 | #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10) |
| 121 | #define AR8216_PORT_CTRL_HEADER BIT(11) |
| 122 | #define AR8216_PORT_CTRL_MAC_LOOP BIT(12) |
| 123 | #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13) |
| 124 | #define AR8216_PORT_CTRL_LEARN BIT(14) |
| 125 | #define AR8216_PORT_CTRL_MIRROR_TX BIT(16) |
| 126 | #define AR8216_PORT_CTRL_MIRROR_RX BIT(17) |
| 127 | |
| 128 | #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008) |
| 129 | |
| 130 | #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12) |
| 131 | #define AR8216_PORT_VLAN_DEFAULT_ID_S 0 |
| 132 | |
| 133 | #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9) |
| 134 | #define AR8216_PORT_VLAN_DEST_PORTS_S 16 |
| 135 | |
| 136 | /* bit0 added to the priority field of egress frames */ |
| 137 | #define AR8216_PORT_VLAN_TX_PRIO BIT(27) |
| 138 | |
| 139 | /* port default priority */ |
| 140 | #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2) |
| 141 | #define AR8216_PORT_VLAN_PRIORITY_S 28 |
| 142 | |
| 143 | /* ingress 802.1q mode */ |
| 144 | #define AR8216_PORT_VLAN_MODE BITS(30, 2) |
| 145 | #define AR8216_PORT_VLAN_MODE_S 30 |
| 146 | |
| 147 | #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c) |
| 148 | #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010) |
| 149 | |
| 150 | |
| 151 | #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008) |
| 152 | #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12) |
| 153 | #define AR8236_PORT_VLAN_DEFAULT_ID_S 16 |
| 154 | #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3) |
| 155 | #define AR8236_PORT_VLAN_PRIORITY_S 28 |
| 156 | |
| 157 | #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c) |
| 158 | #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7) |
| 159 | #define AR8236_PORT_VLAN2_MEMBER_S 16 |
| 160 | #define AR8236_PORT_VLAN2_TX_PRIO BIT(23) |
| 161 | #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2) |
| 162 | #define AR8236_PORT_VLAN2_VLAN_MODE_S 30 |
| 163 | |
| 164 | /* port speed */ |
| 165 | enum { |
| 166 | AR8216_PORT_SPEED_10M = 0, |
| 167 | AR8216_PORT_SPEED_100M = 1, |
| 168 | AR8216_PORT_SPEED_1000M = 2, |
| 169 | AR8216_PORT_SPEED_ERR = 3, |
| 170 | }; |
| 171 | |
| 172 | /* ingress 802.1q mode */ |
| 173 | enum { |
| 174 | AR8216_IN_PORT_ONLY = 0, |
| 175 | AR8216_IN_PORT_FALLBACK = 1, |
| 176 | AR8216_IN_VLAN_ONLY = 2, |
| 177 | AR8216_IN_SECURE = 3 |
| 178 | }; |
| 179 | |
| 180 | /* egress 802.1q mode */ |
| 181 | enum { |
| 182 | AR8216_OUT_KEEP = 0, |
| 183 | AR8216_OUT_STRIP_VLAN = 1, |
| 184 | AR8216_OUT_ADD_VLAN = 2 |
| 185 | }; |
| 186 | |
| 187 | /* port forwarding state */ |
| 188 | enum { |
| 189 | AR8216_PORT_STATE_DISABLED = 0, |
| 190 | AR8216_PORT_STATE_BLOCK = 1, |
| 191 | AR8216_PORT_STATE_LISTEN = 2, |
| 192 | AR8216_PORT_STATE_LEARN = 3, |
| 193 | AR8216_PORT_STATE_FORWARD = 4 |
| 194 | }; |
| 195 | |
| 196 | /* device */ |
| 197 | enum { |
| 198 | UNKNOWN = 0, |
| 199 | AR8216 = 8216, |
| 200 | AR8236 = 8236, |
| 201 | AR8316 = 8316, |
| 202 | }; |
| 203 | |
| 204 | #endif |
| 205 | |
