Root/target/linux/generic/files/drivers/pwm/atmel-pwm.c

1/*
2 * drivers/pwm/atmel-pwm.c
3 *
4 * Copyright (C) 2010 Bill Gatliff <bgat@billgatliff.com>
5 * Copyright (C) 2007 David Brownell
6 *
7 * This program is free software; you may redistribute and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
19 * USA
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/clk.h>
25#include <linux/err.h>
26#include <linux/io.h>
27#include <linux/interrupt.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30#include <linux/pwm/pwm.h>
31
32enum {
33    /* registers common to the PWMC peripheral */
34    PWMC_MR = 0,
35    PWMC_ENA = 4,
36    PWMC_DIS = 8,
37    PWMC_SR = 0xc,
38    PWMC_IER = 0x10,
39    PWMC_IDR = 0x14,
40    PWMC_IMR = 0x18,
41    PWMC_ISR = 0x1c,
42
43    /* registers per each PWMC channel */
44    PWMC_CMR = 0,
45    PWMC_CDTY = 4,
46    PWMC_CPRD = 8,
47    PWMC_CCNT = 0xc,
48    PWMC_CUPD = 0x10,
49
50    /* how to find each channel */
51    PWMC_CHAN_BASE = 0x200,
52    PWMC_CHAN_STRIDE = 0x20,
53
54    /* CMR bits of interest */
55    PWMC_CMR_CPD = 10,
56    PWMC_CMR_CPOL = 9,
57    PWMC_CMR_CALG = 8,
58    PWMC_CMR_CPRE_MASK = 0xf,
59};
60
61struct atmel_pwm {
62    struct pwm_device pwm;
63    spinlock_t lock;
64    void __iomem *iobase;
65    struct clk *clk;
66    u32 *sync_mask;
67    int irq;
68    u32 ccnt_mask;
69};
70
71static inline struct atmel_pwm *to_atmel_pwm(const struct pwm_channel *p)
72{
73    return container_of(p->pwm, struct atmel_pwm, pwm);
74}
75
76static inline void
77pwmc_writel(const struct atmel_pwm *p,
78        unsigned offset, u32 val)
79{
80    __raw_writel(val, p->iobase + offset);
81}
82
83static inline u32
84pwmc_readl(const struct atmel_pwm *p,
85       unsigned offset)
86{
87    return __raw_readl(p->iobase + offset);
88}
89
90static inline void
91pwmc_chan_writel(const struct pwm_channel *p,
92         u32 offset, u32 val)
93{
94    const struct atmel_pwm *ap = to_atmel_pwm(p);
95
96    if (PWMC_CMR == offset)
97        val &= ((1 << PWMC_CMR_CPD)
98            | (1 << PWMC_CMR_CPOL)
99            | (1 << PWMC_CMR_CALG)
100            | (PWMC_CMR_CPRE_MASK));
101    else
102        val &= ap->ccnt_mask;
103
104    pwmc_writel(ap, offset + PWMC_CHAN_BASE
105            + (p->chan * PWMC_CHAN_STRIDE), val);
106}
107
108static inline u32
109pwmc_chan_readl(const struct pwm_channel *p,
110        u32 offset)
111{
112    const struct atmel_pwm *ap = to_atmel_pwm(p);
113
114    return pwmc_readl(ap, offset + PWMC_CHAN_BASE
115              + (p->chan * PWMC_CHAN_STRIDE));
116}
117
118static inline int
119__atmel_pwm_is_on(struct pwm_channel *p)
120{
121    struct atmel_pwm *ap = to_atmel_pwm(p);
122    return (pwmc_readl(ap, PWMC_SR) & (1 << p->chan)) ? 1 : 0;
123}
124
125static inline void
126__atmel_pwm_unsynchronize(struct pwm_channel *p,
127              struct pwm_channel *to_p)
128{
129    const struct atmel_pwm *ap = to_atmel_pwm(p);
130    int wchan;
131
132    if (to_p) {
133        ap->sync_mask[p->chan] &= ~(1 << to_p->chan);
134        ap->sync_mask[to_p->chan] &= ~(1 << p->chan);
135        goto done;
136    }
137
138    ap->sync_mask[p->chan] = 0;
139    for (wchan = 0; wchan < ap->pwm.nchan; wchan++)
140        ap->sync_mask[wchan] &= ~(1 << p->chan);
141done:
142    dev_dbg(p->pwm->dev, "sync_mask %x\n", ap->sync_mask[p->chan]);
143}
144
145static inline void
146__atmel_pwm_synchronize(struct pwm_channel *p,
147            struct pwm_channel *to_p)
148{
149    const struct atmel_pwm *ap = to_atmel_pwm(p);
150
151    if (!to_p)
152        return;
153
154    ap->sync_mask[p->chan] |= (1 << to_p->chan);
155    ap->sync_mask[to_p->chan] |= (1 << p->chan);
156
157    dev_dbg(p->pwm->dev, "sync_mask %x\n", ap->sync_mask[p->chan]);
158}
159
160static inline void
161__atmel_pwm_stop(struct pwm_channel *p)
162{
163    struct atmel_pwm *ap = to_atmel_pwm(p);
164    u32 chid = 1 << p->chan;
165
166    pwmc_writel(ap, PWMC_DIS, ap->sync_mask[p->chan] | chid);
167}
168
169static inline void
170__atmel_pwm_start(struct pwm_channel *p)
171{
172    struct atmel_pwm *ap = to_atmel_pwm(p);
173    u32 chid = 1 << p->chan;
174
175    pwmc_writel(ap, PWMC_ENA, ap->sync_mask[p->chan] | chid);
176}
177
178static int
179atmel_pwm_synchronize(struct pwm_channel *p,
180              struct pwm_channel *to_p)
181{
182    unsigned long flags;
183    spin_lock_irqsave(&p->lock, flags);
184    __atmel_pwm_synchronize(p, to_p);
185    spin_unlock_irqrestore(&p->lock, flags);
186    return 0;
187}
188
189static int
190atmel_pwm_unsynchronize(struct pwm_channel *p,
191            struct pwm_channel *from_p)
192{
193    unsigned long flags;
194    spin_lock_irqsave(&p->lock, flags);
195    __atmel_pwm_unsynchronize(p, from_p);
196    spin_unlock_irqrestore(&p->lock, flags);
197    return 0;
198}
199
200static inline int
201__atmel_pwm_config_polarity(struct pwm_channel *p,
202                struct pwm_channel_config *c)
203{
204    u32 cmr = pwmc_chan_readl(p, PWMC_CMR);
205
206    if (c->polarity)
207        cmr &= ~BIT(PWMC_CMR_CPOL);
208    else
209        cmr |= BIT(PWMC_CMR_CPOL);
210    pwmc_chan_writel(p, PWMC_CMR, cmr);
211    p->active_high = c->polarity ? 1 : 0;
212
213    dev_dbg(p->pwm->dev, "polarity %d\n", c->polarity);
214    return 0;
215}
216
217static inline int
218__atmel_pwm_config_duty_ticks(struct pwm_channel *p,
219                  struct pwm_channel_config *c)
220{
221    u32 cmr, cprd, cpre, cdty;
222
223    cmr = pwmc_chan_readl(p, PWMC_CMR);
224    cprd = pwmc_chan_readl(p, PWMC_CPRD);
225
226    cpre = cmr & PWMC_CMR_CPRE_MASK;
227    cmr &= ~BIT(PWMC_CMR_CPD);
228
229    cdty = cprd - (c->duty_ticks >> cpre);
230
231    p->duty_ticks = c->duty_ticks;
232
233    if (__atmel_pwm_is_on(p)) {
234        pwmc_chan_writel(p, PWMC_CMR, cmr);
235        pwmc_chan_writel(p, PWMC_CUPD, cdty);
236    } else
237        pwmc_chan_writel(p, PWMC_CDTY, cdty);
238
239    dev_dbg(p->pwm->dev, "duty_ticks = %lu cprd = %x"
240        " cdty = %x cpre = %x\n", p->duty_ticks,
241        cprd, cdty, cpre);
242
243    return 0;
244}
245
246static inline int
247__atmel_pwm_config_period_ticks(struct pwm_channel *p,
248                struct pwm_channel_config *c)
249{
250    u32 cmr, cprd, cpre;
251
252    cpre = fls(c->period_ticks);
253    if (cpre < 16)
254        cpre = 0;
255    else {
256        cpre -= 15;
257        if (cpre > 10)
258            return -EINVAL;
259    }
260
261    cmr = pwmc_chan_readl(p, PWMC_CMR);
262    cmr &= ~PWMC_CMR_CPRE_MASK;
263    cmr |= cpre;
264
265    cprd = c->period_ticks >> cpre;
266
267    pwmc_chan_writel(p, PWMC_CMR, cmr);
268    pwmc_chan_writel(p, PWMC_CPRD, cprd);
269    p->period_ticks = c->period_ticks;
270
271    dev_dbg(p->pwm->dev, "period_ticks = %lu cprd = %x cpre = %x\n",
272         p->period_ticks, cprd, cpre);
273
274    return 0;
275}
276
277static int
278atmel_pwm_config_nosleep(struct pwm_channel *p,
279             struct pwm_channel_config *c)
280{
281    int ret = 0;
282    unsigned long flags;
283
284    spin_lock_irqsave(&p->lock, flags);
285
286    switch (c->config_mask) {
287
288    case PWM_CONFIG_DUTY_TICKS:
289        __atmel_pwm_config_duty_ticks(p, c);
290        break;
291
292    case PWM_CONFIG_STOP:
293        __atmel_pwm_stop(p);
294        break;
295
296    case PWM_CONFIG_START:
297        __atmel_pwm_start(p);
298        break;
299
300    case PWM_CONFIG_POLARITY:
301        __atmel_pwm_config_polarity(p, c);
302        break;
303
304    default:
305        ret = -EINVAL;
306        break;
307    }
308
309    spin_unlock_irqrestore(&p->lock, flags);
310    return ret;
311}
312
313static int
314atmel_pwm_stop_sync(struct pwm_channel *p)
315{
316    struct atmel_pwm *ap = container_of(p->pwm, struct atmel_pwm, pwm);
317    int ret;
318    int was_on = __atmel_pwm_is_on(p);
319
320    if (was_on) {
321        do {
322            init_completion(&p->complete);
323            set_bit(FLAG_STOP, &p->flags);
324            pwmc_writel(ap, PWMC_IER, 1 << p->chan);
325
326            dev_dbg(p->pwm->dev, "waiting on stop_sync completion...\n");
327
328            ret = wait_for_completion_interruptible(&p->complete);
329
330            dev_dbg(p->pwm->dev, "stop_sync complete (%d)\n", ret);
331
332            if (ret)
333                return ret;
334        } while (p->flags & BIT(FLAG_STOP));
335    }
336
337    return was_on;
338}
339
340static int
341atmel_pwm_config(struct pwm_channel *p,
342         struct pwm_channel_config *c)
343{
344    int was_on = 0;
345
346    if (p->pwm->config_nosleep) {
347        if (!p->pwm->config_nosleep(p, c))
348            return 0;
349    }
350
351    might_sleep();
352
353    dev_dbg(p->pwm->dev, "config_mask %x\n", c->config_mask);
354
355    was_on = atmel_pwm_stop_sync(p);
356    if (was_on < 0)
357        return was_on;
358
359    if (c->config_mask & PWM_CONFIG_PERIOD_TICKS) {
360        __atmel_pwm_config_period_ticks(p, c);
361        if (!(c->config_mask & PWM_CONFIG_DUTY_TICKS)) {
362            struct pwm_channel_config d = {
363                .config_mask = PWM_CONFIG_DUTY_TICKS,
364                .duty_ticks = p->duty_ticks,
365            };
366            __atmel_pwm_config_duty_ticks(p, &d);
367        }
368    }
369
370    if (c->config_mask & PWM_CONFIG_DUTY_TICKS)
371        __atmel_pwm_config_duty_ticks(p, c);
372
373    if (c->config_mask & PWM_CONFIG_POLARITY)
374        __atmel_pwm_config_polarity(p, c);
375
376    if ((c->config_mask & PWM_CONFIG_START)
377        || (was_on && !(c->config_mask & PWM_CONFIG_STOP)))
378        __atmel_pwm_start(p);
379
380    return 0;
381}
382
383static void
384__atmel_pwm_set_callback(struct pwm_channel *p,
385             pwm_callback_t callback)
386{
387    struct atmel_pwm *ap = container_of(p->pwm, struct atmel_pwm, pwm);
388
389    p->callback = callback;
390    pwmc_writel(ap, p->callback ? PWMC_IER : PWMC_IDR, 1 << p->chan);
391}
392
393static int
394atmel_pwm_set_callback(struct pwm_channel *p,
395               pwm_callback_t callback)
396{
397    struct atmel_pwm *ap = to_atmel_pwm(p);
398    unsigned long flags;
399
400    spin_lock_irqsave(&ap->lock, flags);
401    __atmel_pwm_set_callback(p, callback);
402    spin_unlock_irqrestore(&ap->lock, flags);
403
404    return 0;
405}
406
407static int
408atmel_pwm_request(struct pwm_channel *p)
409{
410    struct atmel_pwm *ap = to_atmel_pwm(p);
411    unsigned long flags;
412
413    spin_lock_irqsave(&p->lock, flags);
414    clk_enable(ap->clk);
415    p->tick_hz = clk_get_rate(ap->clk);
416    __atmel_pwm_unsynchronize(p, NULL);
417    __atmel_pwm_stop(p);
418    spin_unlock_irqrestore(&p->lock, flags);
419
420    return 0;
421}
422
423static void
424atmel_pwm_free(struct pwm_channel *p)
425{
426    struct atmel_pwm *ap = to_atmel_pwm(p);
427    clk_disable(ap->clk);
428}
429
430static irqreturn_t
431atmel_pwmc_irq(int irq, void *data)
432{
433    struct atmel_pwm *ap = data;
434    struct pwm_channel *p;
435    u32 isr;
436    int chid;
437    unsigned long flags;
438
439    spin_lock_irqsave(&ap->lock, flags);
440
441    isr = pwmc_readl(ap, PWMC_ISR);
442    for (chid = 0; isr; chid++, isr >>= 1) {
443        p = &ap->pwm.channels[chid];
444        if (isr & 1) {
445            if (p->callback)
446                p->callback(p);
447            if (p->flags & BIT(FLAG_STOP)) {
448                __atmel_pwm_stop(p);
449                clear_bit(FLAG_STOP, &p->flags);
450            }
451            complete_all(&p->complete);
452        }
453    }
454
455    spin_unlock_irqrestore(&ap->lock, flags);
456
457    return IRQ_HANDLED;
458}
459
460static int __devinit
461atmel_pwmc_probe(struct platform_device *pdev)
462{
463    struct atmel_pwm *ap;
464    struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
465    int ret = 0;
466
467    ap = kzalloc(sizeof(*ap), GFP_KERNEL);
468    if (!ap) {
469        ret = -ENOMEM;
470        goto err_atmel_pwm_alloc;
471    }
472
473    spin_lock_init(&ap->lock);
474    platform_set_drvdata(pdev, ap);
475
476    ap->pwm.dev = &pdev->dev;
477    ap->pwm.bus_id = dev_name(&pdev->dev);
478
479    ap->pwm.nchan = 4; /* TODO: true only for SAM9263 and AP7000 */
480    ap->ccnt_mask = 0xffffUL; /* TODO: true only for SAM9263 */
481
482    ap->sync_mask = kzalloc(ap->pwm.nchan * sizeof(u32), GFP_KERNEL);
483    if (!ap->sync_mask) {
484        ret = -ENOMEM;
485        goto err_alloc_sync_masks;
486    }
487
488    ap->pwm.owner = THIS_MODULE;
489    ap->pwm.request = atmel_pwm_request;
490    ap->pwm.free = atmel_pwm_free;
491    ap->pwm.config_nosleep = atmel_pwm_config_nosleep;
492    ap->pwm.config = atmel_pwm_config;
493    ap->pwm.synchronize = atmel_pwm_synchronize;
494    ap->pwm.unsynchronize = atmel_pwm_unsynchronize;
495    ap->pwm.set_callback = atmel_pwm_set_callback;
496
497    ap->clk = clk_get(&pdev->dev, "pwm_clk");
498    if (PTR_ERR(ap->clk)) {
499        ret = -ENODEV;
500        goto err_clk_get;
501    }
502
503    ap->iobase = ioremap_nocache(r->start, r->end - r->start + 1);
504    if (!ap->iobase) {
505        ret = -ENODEV;
506        goto err_ioremap;
507    }
508
509    clk_enable(ap->clk);
510    pwmc_writel(ap, PWMC_DIS, -1);
511    pwmc_writel(ap, PWMC_IDR, -1);
512    clk_disable(ap->clk);
513
514    ap->irq = platform_get_irq(pdev, 0);
515    if (ap->irq != -ENXIO) {
516        ret = request_irq(ap->irq, atmel_pwmc_irq, 0,
517                  ap->pwm.bus_id, ap);
518        if (ret)
519            goto err_request_irq;
520    }
521
522    ret = pwm_register(&ap->pwm);
523    if (ret)
524        goto err_pwm_register;
525
526    return 0;
527
528err_pwm_register:
529    if (ap->irq != -ENXIO)
530        free_irq(ap->irq, ap);
531err_request_irq:
532    iounmap(ap->iobase);
533err_ioremap:
534    clk_put(ap->clk);
535err_clk_get:
536    platform_set_drvdata(pdev, NULL);
537err_alloc_sync_masks:
538    kfree(ap);
539err_atmel_pwm_alloc:
540    return ret;
541}
542
543static int __devexit
544atmel_pwmc_remove(struct platform_device *pdev)
545{
546    struct atmel_pwm *ap = platform_get_drvdata(pdev);
547    int ret;
548
549    /* TODO: what can we do if this fails? */
550    ret = pwm_unregister(&ap->pwm);
551
552    clk_enable(ap->clk);
553    pwmc_writel(ap, PWMC_IDR, -1);
554    pwmc_writel(ap, PWMC_DIS, -1);
555    clk_disable(ap->clk);
556
557    if (ap->irq != -ENXIO)
558        free_irq(ap->irq, ap);
559
560    clk_put(ap->clk);
561    iounmap(ap->iobase);
562
563    kfree(ap);
564
565    return 0;
566}
567
568static struct platform_driver atmel_pwm_driver = {
569    .driver = {
570        .name = "atmel_pwmc",
571        .owner = THIS_MODULE,
572    },
573    .probe = atmel_pwmc_probe,
574    .remove = __devexit_p(atmel_pwmc_remove),
575};
576
577static int __init atmel_pwm_init(void)
578{
579    return platform_driver_register(&atmel_pwm_driver);
580}
581module_init(atmel_pwm_init);
582
583static void __exit atmel_pwm_exit(void)
584{
585    platform_driver_unregister(&atmel_pwm_driver);
586}
587module_exit(atmel_pwm_exit);
588
589MODULE_AUTHOR("Bill Gatliff <bgat@billgatliff.com>");
590MODULE_DESCRIPTION("Driver for Atmel PWMC peripheral");
591MODULE_LICENSE("GPL");
592MODULE_ALIAS("platform:atmel_pwmc");
593

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