Root/target/linux/lantiq/patches-2.6.32/0003-MIPS-Lantiq-Add-PCI-controller-support.patch

1From 08127ed36bad367903591bbf0f244179683ccb28 Mon Sep 17 00:00:00 2001
2From: John Crispin <blogic@openwrt.org>
3Date: Wed, 30 Mar 2011 09:27:49 +0200
4Subject: [PATCH 03/13] MIPS: Lantiq: Add PCI controller support.
5
6The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds
7the driver that allows us to use the EBU as a PCI controller. In order for
8PCI to work the EBU is set to endianess swap all the data. In addition we
9need to make use of SWAP_IO_SPACE for device->host DMA to work.
10
11The clock of the PCI works in several modes (internal/external). If this
12is not configured correctly the SoC will hang.
13
14Signed-off-by: John Crispin <blogic@openwrt.org>
15Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
16Cc: linux-mips@linux-mips.org
17Patchwork: https://patchwork.linux-mips.org/patch/2250/
18Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
19---
20 .../mips/include/asm/mach-lantiq/lantiq_platform.h | 46 +++
21 arch/mips/pci/Makefile | 1 +
22 arch/mips/pci/ops-lantiq.c | 116 ++++++++
23 arch/mips/pci/pci-lantiq.c | 297 ++++++++++++++++++++
24 arch/mips/pci/pci-lantiq.h | 18 ++
25 5 files changed, 478 insertions(+), 0 deletions(-)
26 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_platform.h
27 create mode 100644 arch/mips/pci/ops-lantiq.c
28 create mode 100644 arch/mips/pci/pci-lantiq.c
29 create mode 100644 arch/mips/pci/pci-lantiq.h
30
31diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
32new file mode 100644
33index 0000000..1f1dba6
34--- /dev/null
35+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
36@@ -0,0 +1,46 @@
37+/*
38+ * This program is free software; you can redistribute it and/or modify it
39+ * under the terms of the GNU General Public License version 2 as published
40+ * by the Free Software Foundation.
41+ *
42+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
43+ */
44+
45+#ifndef _LANTIQ_PLATFORM_H__
46+#define _LANTIQ_PLATFORM_H__
47+
48+#include <linux/mtd/partitions.h>
49+
50+/* struct used to pass info to the pci core */
51+enum {
52+ PCI_CLOCK_INT = 0,
53+ PCI_CLOCK_EXT
54+};
55+
56+#define PCI_EXIN0 0x0001
57+#define PCI_EXIN1 0x0002
58+#define PCI_EXIN2 0x0004
59+#define PCI_EXIN3 0x0008
60+#define PCI_EXIN4 0x0010
61+#define PCI_EXIN5 0x0020
62+#define PCI_EXIN_MAX 6
63+
64+#define PCI_GNT1 0x0040
65+#define PCI_GNT2 0x0080
66+#define PCI_GNT3 0x0100
67+#define PCI_GNT4 0x0200
68+
69+#define PCI_REQ1 0x0400
70+#define PCI_REQ2 0x0800
71+#define PCI_REQ3 0x1000
72+#define PCI_REQ4 0x2000
73+#define PCI_REQ_SHIFT 10
74+#define PCI_REQ_MASK 0xf
75+
76+struct ltq_pci_data {
77+ int clock;
78+ int gpio;
79+ int irq[16];
80+};
81+
82+#endif
83diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
84index f0d5329..4df8799 100644
85--- a/arch/mips/pci/Makefile
86+++ b/arch/mips/pci/Makefile
87@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
88 obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
89 obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
90 obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
91+obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o
92 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
93 obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
94 obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
95diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
96new file mode 100644
97index 0000000..1f2afb5
98--- /dev/null
99+++ b/arch/mips/pci/ops-lantiq.c
100@@ -0,0 +1,116 @@
101+/*
102+ * This program is free software; you can redistribute it and/or modify it
103+ * under the terms of the GNU General Public License version 2 as published
104+ * by the Free Software Foundation.
105+ *
106+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
107+ */
108+
109+#include <linux/types.h>
110+#include <linux/pci.h>
111+#include <linux/kernel.h>
112+#include <linux/init.h>
113+#include <linux/delay.h>
114+#include <linux/mm.h>
115+#include <asm/addrspace.h>
116+#include <linux/vmalloc.h>
117+
118+#include <lantiq_soc.h>
119+
120+#include "pci-lantiq.h"
121+
122+#define LTQ_PCI_CFG_BUSNUM_SHF 16
123+#define LTQ_PCI_CFG_DEVNUM_SHF 11
124+#define LTQ_PCI_CFG_FUNNUM_SHF 8
125+
126+#define PCI_ACCESS_READ 0
127+#define PCI_ACCESS_WRITE 1
128+
129+static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
130+ unsigned int devfn, unsigned int where, u32 *data)
131+{
132+ unsigned long cfg_base;
133+ unsigned long flags;
134+ u32 temp;
135+
136+ /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
137+ SoC itself */
138+ if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
139+ || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
140+ return 1;
141+
142+ spin_lock_irqsave(&ebu_lock, flags);
143+
144+ cfg_base = (unsigned long) ltq_pci_mapped_cfg;
145+ cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
146+ LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
147+
148+ /* Perform access */
149+ if (access_type == PCI_ACCESS_WRITE) {
150+ ltq_w32(swab32(*data), ((u32 *)cfg_base));
151+ } else {
152+ *data = ltq_r32(((u32 *)(cfg_base)));
153+ *data = swab32(*data);
154+ }
155+ wmb();
156+
157+ /* clean possible Master abort */
158+ cfg_base = (unsigned long) ltq_pci_mapped_cfg;
159+ cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
160+ temp = ltq_r32(((u32 *)(cfg_base)));
161+ temp = swab32(temp);
162+ cfg_base = (unsigned long) ltq_pci_mapped_cfg;
163+ cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
164+ ltq_w32(temp, ((u32 *)cfg_base));
165+
166+ spin_unlock_irqrestore(&ebu_lock, flags);
167+
168+ if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
169+ return 1;
170+
171+ return 0;
172+}
173+
174+int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
175+ int where, int size, u32 *val)
176+{
177+ u32 data = 0;
178+
179+ if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
180+ return PCIBIOS_DEVICE_NOT_FOUND;
181+
182+ if (size == 1)
183+ *val = (data >> ((where & 3) << 3)) & 0xff;
184+ else if (size == 2)
185+ *val = (data >> ((where & 3) << 3)) & 0xffff;
186+ else
187+ *val = data;
188+
189+ return PCIBIOS_SUCCESSFUL;
190+}
191+
192+int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
193+ int where, int size, u32 val)
194+{
195+ u32 data = 0;
196+
197+ if (size == 4) {
198+ data = val;
199+ } else {
200+ if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
201+ devfn, where, &data))
202+ return PCIBIOS_DEVICE_NOT_FOUND;
203+
204+ if (size == 1)
205+ data = (data & ~(0xff << ((where & 3) << 3))) |
206+ (val << ((where & 3) << 3));
207+ else if (size == 2)
208+ data = (data & ~(0xffff << ((where & 3) << 3))) |
209+ (val << ((where & 3) << 3));
210+ }
211+
212+ if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
213+ return PCIBIOS_DEVICE_NOT_FOUND;
214+
215+ return PCIBIOS_SUCCESSFUL;
216+}
217diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
218new file mode 100644
219index 0000000..603d749
220--- /dev/null
221+++ b/arch/mips/pci/pci-lantiq.c
222@@ -0,0 +1,297 @@
223+/*
224+ * This program is free software; you can redistribute it and/or modify it
225+ * under the terms of the GNU General Public License version 2 as published
226+ * by the Free Software Foundation.
227+ *
228+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
229+ */
230+
231+#include <linux/types.h>
232+#include <linux/pci.h>
233+#include <linux/kernel.h>
234+#include <linux/init.h>
235+#include <linux/delay.h>
236+#include <linux/mm.h>
237+#include <linux/vmalloc.h>
238+#include <linux/platform_device.h>
239+
240+#include <asm/pci.h>
241+#include <asm/gpio.h>
242+#include <asm/addrspace.h>
243+
244+#include <lantiq_soc.h>
245+#include <lantiq_irq.h>
246+#include <lantiq_platform.h>
247+
248+#include "pci-lantiq.h"
249+
250+#define LTQ_PCI_CFG_BASE 0x17000000
251+#define LTQ_PCI_CFG_SIZE 0x00008000
252+#define LTQ_PCI_MEM_BASE 0x18000000
253+#define LTQ_PCI_MEM_SIZE 0x02000000
254+#define LTQ_PCI_IO_BASE 0x1AE00000
255+#define LTQ_PCI_IO_SIZE 0x00200000
256+
257+#define PCI_CR_FCI_ADDR_MAP0 0x00C0
258+#define PCI_CR_FCI_ADDR_MAP1 0x00C4
259+#define PCI_CR_FCI_ADDR_MAP2 0x00C8
260+#define PCI_CR_FCI_ADDR_MAP3 0x00CC
261+#define PCI_CR_FCI_ADDR_MAP4 0x00D0
262+#define PCI_CR_FCI_ADDR_MAP5 0x00D4
263+#define PCI_CR_FCI_ADDR_MAP6 0x00D8
264+#define PCI_CR_FCI_ADDR_MAP7 0x00DC
265+#define PCI_CR_CLK_CTRL 0x0000
266+#define PCI_CR_PCI_MOD 0x0030
267+#define PCI_CR_PC_ARB 0x0080
268+#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
269+#define PCI_CR_BAR11MASK 0x0044
270+#define PCI_CR_BAR12MASK 0x0048
271+#define PCI_CR_BAR13MASK 0x004C
272+#define PCI_CS_BASE_ADDR1 0x0010
273+#define PCI_CR_PCI_ADDR_MAP11 0x0064
274+#define PCI_CR_FCI_BURST_LENGTH 0x00E8
275+#define PCI_CR_PCI_EOI 0x002C
276+#define PCI_CS_STS_CMD 0x0004
277+
278+#define PCI_MASTER0_REQ_MASK_2BITS 8
279+#define PCI_MASTER1_REQ_MASK_2BITS 10
280+#define PCI_MASTER2_REQ_MASK_2BITS 12
281+#define INTERNAL_ARB_ENABLE_BIT 0
282+
283+#define LTQ_CGU_IFCCR 0x0018
284+#define LTQ_CGU_PCICR 0x0034
285+
286+#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
287+#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
288+
289+#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
290+#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
291+
292+struct ltq_pci_gpio_map {
293+ int pin;
294+ int alt0;
295+ int alt1;
296+ int dir;
297+ char *name;
298+};
299+
300+/* the pci core can make use of the following gpios */
301+static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
302+ { 0, 1, 0, 0, "pci-exin0" },
303+ { 1, 1, 0, 0, "pci-exin1" },
304+ { 2, 1, 0, 0, "pci-exin2" },
305+ { 39, 1, 0, 0, "pci-exin3" },
306+ { 10, 1, 0, 0, "pci-exin4" },
307+ { 9, 1, 0, 0, "pci-exin5" },
308+ { 30, 1, 0, 1, "pci-gnt1" },
309+ { 23, 1, 0, 1, "pci-gnt2" },
310+ { 19, 1, 0, 1, "pci-gnt3" },
311+ { 38, 1, 0, 1, "pci-gnt4" },
312+ { 29, 1, 0, 0, "pci-req1" },
313+ { 31, 1, 0, 0, "pci-req2" },
314+ { 3, 1, 0, 0, "pci-req3" },
315+ { 37, 1, 0, 0, "pci-req4" },
316+};
317+
318+__iomem void *ltq_pci_mapped_cfg;
319+static __iomem void *ltq_pci_membase;
320+
321+int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
322+
323+/* Since the PCI REQ pins can be reused for other functionality, make it
324+ possible to exclude those from interpretation by the PCI controller */
325+static int ltq_pci_req_mask = 0xf;
326+
327+static int *ltq_pci_irq_map;
328+
329+struct pci_ops ltq_pci_ops = {
330+ .read = ltq_pci_read_config_dword,
331+ .write = ltq_pci_write_config_dword
332+};
333+
334+static struct resource pci_io_resource = {
335+ .name = "pci io space",
336+ .start = LTQ_PCI_IO_BASE,
337+ .end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1,
338+ .flags = IORESOURCE_IO
339+};
340+
341+static struct resource pci_mem_resource = {
342+ .name = "pci memory space",
343+ .start = LTQ_PCI_MEM_BASE,
344+ .end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1,
345+ .flags = IORESOURCE_MEM
346+};
347+
348+static struct pci_controller ltq_pci_controller = {
349+ .pci_ops = &ltq_pci_ops,
350+ .mem_resource = &pci_mem_resource,
351+ .mem_offset = 0x00000000UL,
352+ .io_resource = &pci_io_resource,
353+ .io_offset = 0x00000000UL,
354+};
355+
356+int pcibios_plat_dev_init(struct pci_dev *dev)
357+{
358+ if (ltqpci_plat_dev_init)
359+ return ltqpci_plat_dev_init(dev);
360+
361+ return 0;
362+}
363+
364+static u32 ltq_calc_bar11mask(void)
365+{
366+ u32 mem, bar11mask;
367+
368+ /* BAR11MASK value depends on available memory on system. */
369+ mem = num_physpages * PAGE_SIZE;
370+ bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
371+
372+ return bar11mask;
373+}
374+
375+static void ltq_pci_setup_gpio(int gpio)
376+{
377+ int i;
378+ for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
379+ if (gpio & (1 << i)) {
380+ ltq_gpio_request(ltq_pci_gpio_map[i].pin,
381+ ltq_pci_gpio_map[i].alt0,
382+ ltq_pci_gpio_map[i].alt1,
383+ ltq_pci_gpio_map[i].dir,
384+ ltq_pci_gpio_map[i].name);
385+ }
386+ }
387+ ltq_gpio_request(21, 0, 0, 1, "pci-reset");
388+ ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
389+}
390+
391+static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
392+{
393+ u32 temp_buffer;
394+
395+ /* set clock to 33Mhz */
396+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
397+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
398+
399+ /* external or internal clock ? */
400+ if (conf->clock) {
401+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16),
402+ LTQ_CGU_IFCCR);
403+ ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR);
404+ } else {
405+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16),
406+ LTQ_CGU_IFCCR);
407+ ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR);
408+ }
409+
410+ /* setup pci clock and gpis used by pci */
411+ ltq_pci_setup_gpio(conf->gpio);
412+
413+ /* enable auto-switching between PCI and EBU */
414+ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
415+
416+ /* busy, i.e. configuration is not done, PCI access has to be retried */
417+ ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
418+ wmb();
419+ /* BUS Master/IO/MEM access */
420+ ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
421+
422+ /* enable external 2 PCI masters */
423+ temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
424+ temp_buffer &= (~(ltq_pci_req_mask << 16));
425+ /* enable internal arbiter */
426+ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
427+ /* enable internal PCI master reqest */
428+ temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
429+
430+ /* enable EBU request */
431+ temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
432+
433+ /* enable all external masters request */
434+ temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
435+ ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
436+ wmb();
437+
438+ /* setup BAR memory regions */
439+ ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
440+ ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
441+ ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
442+ ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
443+ ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
444+ ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
445+ ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
446+ ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
447+ ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
448+ ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
449+ ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
450+ ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
451+ /* both TX and RX endian swap are enabled */
452+ ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
453+ wmb();
454+ ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
455+ PCI_CR_BAR12MASK);
456+ ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
457+ PCI_CR_BAR13MASK);
458+ /*use 8 dw burst length */
459+ ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
460+ ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
461+ wmb();
462+
463+ /* setup irq line */
464+ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
465+ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
466+
467+ /* toggle reset pin */
468+ __gpio_set_value(21, 0);
469+ wmb();
470+ mdelay(1);
471+ __gpio_set_value(21, 1);
472+ return 0;
473+}
474+
475+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
476+{
477+ if (ltq_pci_irq_map[slot])
478+ return ltq_pci_irq_map[slot];
479+ printk(KERN_ERR "ltq_pci: trying to map irq for unknown slot %d\n",
480+ slot);
481+
482+ return 0;
483+}
484+
485+static int __devinit ltq_pci_probe(struct platform_device *pdev)
486+{
487+ struct ltq_pci_data *ltq_pci_data =
488+ (struct ltq_pci_data *) pdev->dev.platform_data;
489+ pci_probe_only = 0;
490+ ltq_pci_irq_map = ltq_pci_data->irq;
491+ ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
492+ ltq_pci_mapped_cfg =
493+ ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
494+ ltq_pci_controller.io_map_base =
495+ (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
496+ ltq_pci_startup(ltq_pci_data);
497+ register_pci_controller(&ltq_pci_controller);
498+
499+ return 0;
500+}
501+
502+static struct platform_driver
503+ltq_pci_driver = {
504+ .probe = ltq_pci_probe,
505+ .driver = {
506+ .name = "ltq_pci",
507+ .owner = THIS_MODULE,
508+ },
509+};
510+
511+int __init pcibios_init(void)
512+{
513+ int ret = platform_driver_register(&ltq_pci_driver);
514+ if (ret)
515+ printk(KERN_INFO "ltq_pci: Error registering platfom driver!");
516+ return ret;
517+}
518+
519+arch_initcall(pcibios_init);
520diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h
521new file mode 100644
522index 0000000..66bf6cd
523--- /dev/null
524+++ b/arch/mips/pci/pci-lantiq.h
525@@ -0,0 +1,18 @@
526+/*
527+ * This program is free software; you can redistribute it and/or modify it
528+ * under the terms of the GNU General Public License version 2 as published
529+ * by the Free Software Foundation.
530+ *
531+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
532+ */
533+
534+#ifndef _LTQ_PCI_H__
535+#define _LTQ_PCI_H__
536+
537+extern __iomem void *ltq_pci_mapped_cfg;
538+extern int ltq_pci_read_config_dword(struct pci_bus *bus,
539+ unsigned int devfn, int where, int size, u32 *val);
540+extern int ltq_pci_write_config_dword(struct pci_bus *bus,
541+ unsigned int devfn, int where, int size, u32 val);
542+
543+#endif
544--
5451.7.2.3
546
547

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