| 1 | --- a/arch/mips/Makefile |
| 2 | +++ b/arch/mips/Makefile |
| 3 | @@ -179,6 +179,16 @@ |
| 4 | # |
| 5 | |
| 6 | # |
| 7 | +# Lantiq |
| 8 | +# |
| 9 | + |
| 10 | +core-$(CONFIG_LANTIQ) += arch/mips/lantiq/ |
| 11 | +cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq |
| 12 | +load-$(CONFIG_LANTIQ) = 0xffffffff80002000 |
| 13 | +cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway |
| 14 | +cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon |
| 15 | + |
| 16 | +# |
| 17 | # Texas Instruments AR7 |
| 18 | # |
| 19 | core-$(CONFIG_AR7) += arch/mips/ar7/ |
| 20 | --- a/include/linux/compiler.h |
| 21 | +++ b/include/linux/compiler.h |
| 22 | @@ -144,6 +144,11 @@ |
| 23 | # define barrier() __memory_barrier() |
| 24 | #endif |
| 25 | |
| 26 | +/* Unreachable code */ |
| 27 | +#ifndef unreachable |
| 28 | +# define unreachable() do { } while (1) |
| 29 | +#endif |
| 30 | + |
| 31 | #ifndef RELOC_HIDE |
| 32 | # define RELOC_HIDE(ptr, off) \ |
| 33 | ({ unsigned long __ptr; \ |
| 34 | --- /dev/null |
| 35 | +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h |
| 36 | @@ -0,0 +1,40 @@ |
| 37 | +/* |
| 38 | + * This program is free software; you can redistribute it and/or modify it |
| 39 | + * under the terms of the GNU General Public License version 2 as published |
| 40 | + * by the Free Software Foundation. |
| 41 | + * |
| 42 | + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> |
| 43 | + */ |
| 44 | + |
| 45 | +#ifndef _LTQ_FALCON_H__ |
| 46 | +#define _LTQ_FALCON_H__ |
| 47 | + |
| 48 | +#ifdef CONFIG_SOC_FALCON |
| 49 | + |
| 50 | +#include <lantiq.h> |
| 51 | + |
| 52 | +/* Chip IDs */ |
| 53 | +#define SOC_ID_FALCON 0x01B8 |
| 54 | + |
| 55 | +/* SoC Types */ |
| 56 | +#define SOC_TYPE_FALCON 0x01 |
| 57 | + |
| 58 | +/* ASC0/1 - serial port */ |
| 59 | +#define LTQ_ASC0_BASE_ADDR 0x1E100C00 |
| 60 | +#define LTQ_ASC1_BASE_ADDR 0x1E100B00 |
| 61 | +#define LTQ_ASC_SIZE 0x100 |
| 62 | + |
| 63 | +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) |
| 64 | +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) |
| 65 | +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) |
| 66 | + |
| 67 | +/* ICU - interrupt control unit */ |
| 68 | +#define LTQ_ICU_BASE_ADDR 0x1F880200 |
| 69 | +#define LTQ_ICU_SIZE 0x100 |
| 70 | + |
| 71 | +/* WDT */ |
| 72 | +#define LTQ_WDT_BASE_ADDR 0x1F8803F0 |
| 73 | +#define LTQ_WDT_SIZE 0x10 |
| 74 | + |
| 75 | +#endif /* CONFIG_SOC_FALCON */ |
| 76 | +#endif /* _LTQ_XWAY_H__ */ |
| 77 | |
