Root/target/linux/lantiq/patches/0013-MIPS-lantiq-adds-FALC-ON-spi-driver.patch

1From 2bd534c30688bcb3f70f1816fbcff813fc746103 Mon Sep 17 00:00:00 2001
2From: John Crispin <blogic@openwrt.org>
3Date: Sat, 27 Aug 2011 18:12:26 +0200
4Subject: [PATCH 13/24] MIPS: lantiq: adds FALC-ON spi driver
5
6The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is
7designed for serial flash access.
8
9Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
10Signed-off-by: John Crispin <blogic@openwrt.org>
11---
12 arch/mips/lantiq/falcon/devices.c | 12 +-
13 arch/mips/lantiq/falcon/devices.h | 4 +
14 arch/mips/lantiq/falcon/mach-easy98000.c | 27 ++
15 drivers/spi/Kconfig | 4 +
16 drivers/spi/Makefile | 1 +
17 drivers/spi/spi-falcon.c | 477 ++++++++++++++++++++++++++++++
18 6 files changed, 523 insertions(+), 2 deletions(-)
19 create mode 100644 drivers/spi/spi-falcon.c
20
21--- a/arch/mips/lantiq/falcon/devices.c
22+++ b/arch/mips/lantiq/falcon/devices.c
23@@ -129,7 +129,7 @@ falcon_register_gpio_extra(void)
24 
25 /* i2c */
26 static struct resource falcon_i2c_resources[] = {
27- MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
28+ MEM_RES("i2c", LTQ_I2C_BASE_ADDR, LTQ_I2C_SIZE),
29     IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
30     IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
31     IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
32@@ -140,10 +140,18 @@ void __init falcon_register_i2c(void)
33 {
34     platform_device_register_simple("i2c-falcon", 0,
35     falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
36- sys1_hw_activate(ACTS_I2C_ACT);
37+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_I2C_ACT);
38 }
39 
40-void __init falcon_register_crypto(void)
41+/* spi flash */
42+static struct platform_device ltq_spi = {
43+ .name = "falcon_spi",
44+ .num_resources = 0,
45+};
46+
47+void __init
48+falcon_register_spi_flash(struct spi_board_info *data)
49 {
50- platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
51+ spi_register_board_info(data, 1);
52+ platform_device_register(&ltq_spi);
53 }
54--- a/arch/mips/lantiq/falcon/devices.h
55+++ b/arch/mips/lantiq/falcon/devices.h
56@@ -11,11 +11,15 @@
57 #ifndef _FALCON_DEVICES_H__
58 #define _FALCON_DEVICES_H__
59 
60+#include <linux/spi/spi.h>
61+#include <linux/spi/flash.h>
62+
63 #include "../devices.h"
64 
65 extern void falcon_register_nand(void);
66 extern void falcon_register_gpio(void);
67 extern void falcon_register_gpio_extra(void);
68 extern void falcon_register_i2c(void);
69+extern void falcon_register_spi_flash(struct spi_board_info *data);
70 
71 #endif
72--- a/arch/mips/lantiq/falcon/mach-easy98000.c
73+++ b/arch/mips/lantiq/falcon/mach-easy98000.c
74@@ -40,6 +40,21 @@ struct physmap_flash_data easy98000_nor_
75     .parts = easy98000_nor_partitions,
76 };
77 
78+static struct flash_platform_data easy98000_spi_flash_platform_data = {
79+ .name = "sflash",
80+ .parts = easy98000_nor_partitions,
81+ .nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
82+};
83+
84+static struct spi_board_info easy98000_spi_flash_data __initdata = {
85+ .modalias = "m25p80",
86+ .bus_num = 0,
87+ .chip_select = 0,
88+ .max_speed_hz = 10 * 1000 * 1000,
89+ .mode = SPI_MODE_3,
90+ .platform_data = &easy98000_spi_flash_platform_data
91+};
92+
93 /* setup gpio based spi bus/device for access to the eeprom on the board */
94 #define SPI_GPIO_MRST 102
95 #define SPI_GPIO_MTSR 103
96@@ -93,6 +108,13 @@ easy98000_init(void)
97 }
98 
99 static void __init
100+easy98000sf_init(void)
101+{
102+ easy98000_init_common();
103+ falcon_register_spi_flash(&easy98000_spi_flash_data);
104+}
105+
106+static void __init
107 easy98000nand_init(void)
108 {
109     easy98000_init_common();
110@@ -104,6 +126,11 @@ MIPS_MACHINE(LANTIQ_MACH_EASY98000,
111             "EASY98000 Eval Board",
112             easy98000_init);
113 
114+MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
115+ "EASY98000SF",
116+ "EASY98000 Eval Board (Serial Flash)",
117+ easy98000sf_init);
118+
119 MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
120             "EASY98000NAND",
121             "EASY98000 Eval Board (NAND Flash)",
122--- a/drivers/spi/Kconfig
123+++ b/drivers/spi/Kconfig
124@@ -189,6 +189,10 @@ config SPI_MPC52xx
125       This drivers supports the MPC52xx SPI controller in master SPI
126       mode.
127 
128+config SPI_FALCON
129+ tristate "Falcon SPI controller support"
130+ depends on SOC_FALCON
131+
132 config SPI_MPC52xx_PSC
133     tristate "Freescale MPC52xx PSC SPI controller"
134     depends on PPC_MPC52xx && EXPERIMENTAL
135--- a/drivers/spi/Makefile
136+++ b/drivers/spi/Makefile
137@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmi
138 obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
139 spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
140 obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
141+obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
142 obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
143 obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
144 obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
145--- /dev/null
146+++ b/drivers/spi/spi-falcon.c
147@@ -0,0 +1,477 @@
148+/*
149+ * This program is free software; you can redistribute it and/or modify it
150+ * under the terms of the GNU General Public License version 2 as published
151+ * by the Free Software Foundation.
152+ *
153+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
154+ */
155+
156+#include <linux/module.h>
157+#include <linux/device.h>
158+#include <linux/platform_device.h>
159+#include <linux/spi/spi.h>
160+#include <linux/delay.h>
161+#include <linux/workqueue.h>
162+
163+#include <lantiq_soc.h>
164+
165+#define DRV_NAME "falcon_spi"
166+
167+#define FALCON_SPI_XFER_BEGIN (1 << 0)
168+#define FALCON_SPI_XFER_END (1 << 1)
169+
170+/* Bus Read Configuration Register0 */
171+#define LTQ_BUSRCON0 0x00000010
172+/* Bus Write Configuration Register0 */
173+#define LTQ_BUSWCON0 0x00000018
174+/* Serial Flash Configuration Register */
175+#define LTQ_SFCON 0x00000080
176+/* Serial Flash Time Register */
177+#define LTQ_SFTIME 0x00000084
178+/* Serial Flash Status Register */
179+#define LTQ_SFSTAT 0x00000088
180+/* Serial Flash Command Register */
181+#define LTQ_SFCMD 0x0000008C
182+/* Serial Flash Address Register */
183+#define LTQ_SFADDR 0x00000090
184+/* Serial Flash Data Register */
185+#define LTQ_SFDATA 0x00000094
186+/* Serial Flash I/O Control Register */
187+#define LTQ_SFIO 0x00000098
188+/* EBU Clock Control Register */
189+#define LTQ_EBUCC 0x000000C4
190+
191+/* Dummy Phase Length */
192+#define SFCMD_DUMLEN_OFFSET 16
193+#define SFCMD_DUMLEN_MASK 0x000F0000
194+/* Chip Select */
195+#define SFCMD_CS_OFFSET 24
196+#define SFCMD_CS_MASK 0x07000000
197+/* field offset */
198+#define SFCMD_ALEN_OFFSET 20
199+#define SFCMD_ALEN_MASK 0x00700000
200+/* SCK Rise-edge Position */
201+#define SFTIME_SCKR_POS_OFFSET 8
202+#define SFTIME_SCKR_POS_MASK 0x00000F00
203+/* SCK Period */
204+#define SFTIME_SCK_PER_OFFSET 0
205+#define SFTIME_SCK_PER_MASK 0x0000000F
206+/* SCK Fall-edge Position */
207+#define SFTIME_SCKF_POS_OFFSET 12
208+#define SFTIME_SCKF_POS_MASK 0x0000F000
209+/* Device Size */
210+#define SFCON_DEV_SIZE_A23_0 0x03000000
211+#define SFCON_DEV_SIZE_MASK 0x0F000000
212+/* Read Data Position */
213+#define SFTIME_RD_POS_MASK 0x000F0000
214+/* Data Output */
215+#define SFIO_UNUSED_WD_MASK 0x0000000F
216+/* Command Opcode mask */
217+#define SFCMD_OPC_MASK 0x000000FF
218+/* dlen bytes of data to write */
219+#define SFCMD_DIR_WRITE 0x00000100
220+/* Data Length offset */
221+#define SFCMD_DLEN_OFFSET 9
222+/* Command Error */
223+#define SFSTAT_CMD_ERR 0x20000000
224+/* Access Command Pending */
225+#define SFSTAT_CMD_PEND 0x00400000
226+/* Frequency set to 100MHz. */
227+#define EBUCC_EBUDIV_SELF100 0x00000001
228+/* Serial Flash */
229+#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
230+/* 8-bit multiplexed */
231+#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
232+/* Serial Flash */
233+#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
234+/* Chip Select after opcode */
235+#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
236+
237+struct falcon_spi {
238+ u32 sfcmd; /* for caching of opcode, direction, ... */
239+ struct spi_master *master;
240+};
241+
242+int
243+falcon_spi_xfer(struct spi_device *spi,
244+ struct spi_transfer *t,
245+ unsigned long flags)
246+{
247+ struct device *dev = &spi->dev;
248+ struct falcon_spi *priv = spi_master_get_devdata(spi->master);
249+ const u8 *txp = t->tx_buf;
250+ u8 *rxp = t->rx_buf;
251+ unsigned int bytelen = ((8 * t->len + 7) / 8);
252+ unsigned int len, alen, dumlen;
253+ u32 val;
254+ enum {
255+ state_init,
256+ state_command_prepare,
257+ state_write,
258+ state_read,
259+ state_disable_cs,
260+ state_end
261+ } state = state_init;
262+
263+ do {
264+ switch (state) {
265+ case state_init: /* detect phase of upper layer sequence */
266+ {
267+ /* initial write ? */
268+ if (flags & FALCON_SPI_XFER_BEGIN) {
269+ if (!txp) {
270+ dev_err(dev,
271+ "BEGIN without tx data!\n");
272+ return -1;
273+ }
274+ /*
275+ * Prepare the parts of the sfcmd register,
276+ * which should not
277+ * change during a sequence!
278+ * Only exception are the length fields,
279+ * especially alen and dumlen.
280+ */
281+
282+ priv->sfcmd = ((spi->chip_select
283+ << SFCMD_CS_OFFSET)
284+ & SFCMD_CS_MASK);
285+ priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
286+ priv->sfcmd |= *txp;
287+ txp++;
288+ bytelen--;
289+ if (bytelen) {
290+ /* more data:
291+ * maybe address and/or dummy */
292+ state = state_command_prepare;
293+ break;
294+ } else {
295+ dev_dbg(dev, "write cmd %02X\n",
296+ priv->sfcmd & SFCMD_OPC_MASK);
297+ }
298+ }
299+ /* continued write ? */
300+ if (txp && bytelen) {
301+ state = state_write;
302+ break;
303+ }
304+ /* read data? */
305+ if (rxp && bytelen) {
306+ state = state_read;
307+ break;
308+ }
309+ /* end of sequence? */
310+ if (flags & FALCON_SPI_XFER_END)
311+ state = state_disable_cs;
312+ else
313+ state = state_end;
314+ break;
315+ }
316+ case state_command_prepare: /* collect tx data for
317+ address and dummy phase */
318+ {
319+ /* txp is valid, already checked */
320+ val = 0;
321+ alen = 0;
322+ dumlen = 0;
323+ while (bytelen > 0) {
324+ if (alen < 3) {
325+ val = (val<<8)|(*txp++);
326+ alen++;
327+ } else if ((dumlen < 15) && (*txp == 0)) {
328+ /*
329+ * assume dummy bytes are set to 0
330+ * from upper layer
331+ */
332+ dumlen++;
333+ txp++;
334+ } else
335+ break;
336+ bytelen--;
337+ }
338+ priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
339+ priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
340+ (dumlen << SFCMD_DUMLEN_OFFSET);
341+ if (alen > 0)
342+ ltq_ebu_w32(val, LTQ_SFADDR);
343+
344+ dev_dbg(dev, "write cmd %02X, alen=%d "
345+ "(addr=%06X) dumlen=%d\n",
346+ priv->sfcmd & SFCMD_OPC_MASK,
347+ alen, val, dumlen);
348+
349+ if (bytelen > 0) {
350+ /* continue with write */
351+ state = state_write;
352+ } else if (flags & FALCON_SPI_XFER_END) {
353+ /* end of sequence? */
354+ state = state_disable_cs;
355+ } else {
356+ /* go to end and expect another
357+ * call (read or write) */
358+ state = state_end;
359+ }
360+ break;
361+ }
362+ case state_write:
363+ {
364+ /* txp still valid */
365+ priv->sfcmd |= SFCMD_DIR_WRITE;
366+ len = 0;
367+ val = 0;
368+ do {
369+ if (bytelen--)
370+ val |= (*txp++) << (8 * len++);
371+ if ((flags & FALCON_SPI_XFER_END)
372+ && (bytelen == 0)) {
373+ priv->sfcmd &=
374+ ~SFCMD_KEEP_CS_KEEP_SELECTED;
375+ }
376+ if ((len == 4) || (bytelen == 0)) {
377+ ltq_ebu_w32(val, LTQ_SFDATA);
378+ ltq_ebu_w32(priv->sfcmd
379+ | (len<<SFCMD_DLEN_OFFSET),
380+ LTQ_SFCMD);
381+ len = 0;
382+ val = 0;
383+ priv->sfcmd &= ~(SFCMD_ALEN_MASK
384+ | SFCMD_DUMLEN_MASK);
385+ }
386+ } while (bytelen);
387+ state = state_end;
388+ break;
389+ }
390+ case state_read:
391+ {
392+ /* read data */
393+ priv->sfcmd &= ~SFCMD_DIR_WRITE;
394+ do {
395+ if ((flags & FALCON_SPI_XFER_END)
396+ && (bytelen <= 4)) {
397+ priv->sfcmd &=
398+ ~SFCMD_KEEP_CS_KEEP_SELECTED;
399+ }
400+ len = (bytelen > 4) ? 4 : bytelen;
401+ bytelen -= len;
402+ ltq_ebu_w32(priv->sfcmd
403+ |(len<<SFCMD_DLEN_OFFSET), LTQ_SFCMD);
404+ priv->sfcmd &= ~(SFCMD_ALEN_MASK
405+ | SFCMD_DUMLEN_MASK);
406+ do {
407+ val = ltq_ebu_r32(LTQ_SFSTAT);
408+ if (val & SFSTAT_CMD_ERR) {
409+ /* reset error status */
410+ dev_err(dev, "SFSTAT: CMD_ERR "
411+ "(%x)\n", val);
412+ ltq_ebu_w32(SFSTAT_CMD_ERR,
413+ LTQ_SFSTAT);
414+ return -1;
415+ }
416+ } while (val & SFSTAT_CMD_PEND);
417+ val = ltq_ebu_r32(LTQ_SFDATA);
418+ do {
419+ *rxp = (val & 0xFF);
420+ rxp++;
421+ val >>= 8;
422+ len--;
423+ } while (len);
424+ } while (bytelen);
425+ state = state_end;
426+ break;
427+ }
428+ case state_disable_cs:
429+ {
430+ priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
431+ ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
432+ LTQ_SFCMD);
433+ val = ltq_ebu_r32(LTQ_SFSTAT);
434+ if (val & SFSTAT_CMD_ERR) {
435+ /* reset error status */
436+ dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
437+ ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT);
438+ return -1;
439+ }
440+ state = state_end;
441+ break;
442+ }
443+ case state_end:
444+ break;
445+ }
446+ } while (state != state_end);
447+
448+ return 0;
449+}
450+
451+static int
452+falcon_spi_setup(struct spi_device *spi)
453+{
454+ struct device *dev = &spi->dev;
455+ const u32 ebuclk = CLOCK_100M;
456+ unsigned int i;
457+ unsigned long flags;
458+
459+ dev_dbg(dev, "setup\n");
460+
461+ if (spi->master->bus_num > 0 || spi->chip_select > 0)
462+ return -ENODEV;
463+
464+ spin_lock_irqsave(&ebu_lock, flags);
465+
466+ if (ebuclk < spi->max_speed_hz) {
467+ /* set EBU clock to 100 MHz */
468+ ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC);
469+ i = 1; /* divider */
470+ } else {
471+ /* set EBU clock to 50 MHz */
472+ ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC);
473+
474+ /* search for suitable divider */
475+ for (i = 1; i < 7; i++) {
476+ if (ebuclk / i <= spi->max_speed_hz)
477+ break;
478+ }
479+ }
480+
481+ /* setup period of serial clock */
482+ ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
483+ | SFTIME_SCKR_POS_MASK
484+ | SFTIME_SCK_PER_MASK,
485+ (i << SFTIME_SCKR_POS_OFFSET)
486+ | (i << (SFTIME_SCK_PER_OFFSET + 1)),
487+ LTQ_SFTIME);
488+
489+ /* set some bits of unused_wd, to not trigger HOLD/WP
490+ * signals on non QUAD flashes */
491+ ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO);
492+
493+ ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
494+ LTQ_BUSRCON0);
495+ ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0);
496+ /* set address wrap around to maximum for 24-bit addresses */
497+ ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON);
498+
499+ spin_unlock_irqrestore(&ebu_lock, flags);
500+
501+ return 0;
502+}
503+
504+static int
505+falcon_spi_transfer(struct spi_device *spi, struct spi_message *m)
506+{
507+ struct falcon_spi *priv = spi_master_get_devdata(spi->master);
508+ struct spi_transfer *t;
509+ unsigned long spi_flags;
510+ unsigned long flags;
511+ int ret = 0;
512+
513+ priv->sfcmd = 0;
514+ m->actual_length = 0;
515+
516+ spi_flags = FALCON_SPI_XFER_BEGIN;
517+ list_for_each_entry(t, &m->transfers, transfer_list) {
518+ if (list_is_last(&t->transfer_list, &m->transfers))
519+ spi_flags |= FALCON_SPI_XFER_END;
520+
521+ spin_lock_irqsave(&ebu_lock, flags);
522+ ret = falcon_spi_xfer(spi, t, spi_flags);
523+ spin_unlock_irqrestore(&ebu_lock, flags);
524+
525+ if (ret)
526+ break;
527+
528+ m->actual_length += t->len;
529+
530+ if (t->delay_usecs || t->cs_change)
531+ BUG();
532+
533+ spi_flags = 0;
534+ }
535+
536+ m->status = ret;
537+ m->complete(m->context);
538+
539+ return 0;
540+}
541+
542+static void
543+falcon_spi_cleanup(struct spi_device *spi)
544+{
545+ struct device *dev = &spi->dev;
546+
547+ dev_dbg(dev, "cleanup\n");
548+}
549+
550+static int __devinit
551+falcon_spi_probe(struct platform_device *pdev)
552+{
553+ struct device *dev = &pdev->dev;
554+ struct falcon_spi *priv;
555+ struct spi_master *master;
556+ int ret;
557+
558+ dev_dbg(dev, "probing\n");
559+
560+ master = spi_alloc_master(&pdev->dev, sizeof(*priv));
561+ if (!master) {
562+ dev_err(dev, "no memory for spi_master\n");
563+ return -ENOMEM;
564+ }
565+
566+ priv = spi_master_get_devdata(master);
567+ priv->master = master;
568+
569+ master->mode_bits = SPI_MODE_3;
570+ master->num_chipselect = 1;
571+ master->bus_num = 0;
572+
573+ master->setup = falcon_spi_setup;
574+ master->transfer = falcon_spi_transfer;
575+ master->cleanup = falcon_spi_cleanup;
576+
577+ platform_set_drvdata(pdev, priv);
578+
579+ ret = spi_register_master(master);
580+ if (ret)
581+ spi_master_put(master);
582+
583+ return ret;
584+}
585+
586+static int __devexit
587+falcon_spi_remove(struct platform_device *pdev)
588+{
589+ struct device *dev = &pdev->dev;
590+ struct falcon_spi *priv = platform_get_drvdata(pdev);
591+
592+ dev_dbg(dev, "removed\n");
593+
594+ spi_unregister_master(priv->master);
595+
596+ return 0;
597+}
598+
599+static struct platform_driver falcon_spi_driver = {
600+ .probe = falcon_spi_probe,
601+ .remove = __devexit_p(falcon_spi_remove),
602+ .driver = {
603+ .name = DRV_NAME,
604+ .owner = THIS_MODULE
605+ }
606+};
607+
608+static int __init
609+falcon_spi_init(void)
610+{
611+ return platform_driver_register(&falcon_spi_driver);
612+}
613+
614+static void __exit
615+falcon_spi_exit(void)
616+{
617+ platform_driver_unregister(&falcon_spi_driver);
618+}
619+
620+module_init(falcon_spi_init);
621+module_exit(falcon_spi_exit);
622+
623+MODULE_LICENSE("GPL");
624+MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");
625--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
626+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
627@@ -48,6 +48,10 @@
628 
629 #define LTQ_EBU_MODCON 0x000C
630 
631+/* I2C */
632+#define LTQ_I2C_BASE_ADDR 0x1E200000
633+#define LTQ_I2C_SIZE 0x00010000
634+
635 /* GPIO */
636 #define LTQ_GPIO0_BASE_ADDR 0x1D810000
637 #define LTQ_GPIO0_SIZE 0x0080
638@@ -92,6 +96,7 @@
639 
640 /* Activation Status Register */
641 #define ACTS_ASC1_ACT 0x00000800
642+#define ACTS_I2C_ACT 0x00004000
643 #define ACTS_P0 0x00010000
644 #define ACTS_P1 0x00010000
645 #define ACTS_P2 0x00020000
646

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive