Root/target/linux/lantiq/patches/0017-MIPS-lantiq-adds-GPTU-driver.patch

1From 45dbb232686978816e8148753e12f27caa2b2eb3 Mon Sep 17 00:00:00 2001
2From: John Crispin <blogic@openwrt.org>
3Date: Thu, 29 Sep 2011 17:16:38 +0200
4Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
5
6---
7 arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++
8 arch/mips/lantiq/xway/Makefile | 2 +-
9 arch/mips/lantiq/xway/timer.c | 830 ++++++++++++++++++++++
10 3 files changed, 986 insertions(+), 1 deletions(-)
11 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
12 create mode 100644 arch/mips/lantiq/xway/timer.c
13
14--- /dev/null
15+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
16@@ -0,0 +1,155 @@
17+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
18+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
19+
20+
21+/******************************************************************************
22+ Copyright (c) 2002, Infineon Technologies. All rights reserved.
23+
24+ No Warranty
25+ Because the program is licensed free of charge, there is no warranty for
26+ the program, to the extent permitted by applicable law. Except when
27+ otherwise stated in writing the copyright holders and/or other parties
28+ provide the program "as is" without warranty of any kind, either
29+ expressed or implied, including, but not limited to, the implied
30+ warranties of merchantability and fitness for a particular purpose. The
31+ entire risk as to the quality and performance of the program is with
32+ you. should the program prove defective, you assume the cost of all
33+ necessary servicing, repair or correction.
34+
35+ In no event unless required by applicable law or agreed to in writing
36+ will any copyright holder, or any other party who may modify and/or
37+ redistribute the program as permitted above, be liable to you for
38+ damages, including any general, special, incidental or consequential
39+ damages arising out of the use or inability to use the program
40+ (including but not limited to loss of data or data being rendered
41+ inaccurate or losses sustained by you or third parties or a failure of
42+ the program to operate with any other programs), even if such holder or
43+ other party has been advised of the possibility of such damages.
44+******************************************************************************/
45+
46+
47+/*
48+ * ####################################
49+ * Definition
50+ * ####################################
51+ */
52+
53+/*
54+ * Available Timer/Counter Index
55+ */
56+#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
57+#define TIMER_ANY 0x00
58+#define TIMER1A TIMER(1, 0)
59+#define TIMER1B TIMER(1, 1)
60+#define TIMER2A TIMER(2, 0)
61+#define TIMER2B TIMER(2, 1)
62+#define TIMER3A TIMER(3, 0)
63+#define TIMER3B TIMER(3, 1)
64+
65+/*
66+ * Flag of Timer/Counter
67+ * These flags specify the way in which timer is configured.
68+ */
69+/* Bit size of timer/counter. */
70+#define TIMER_FLAG_16BIT 0x0000
71+#define TIMER_FLAG_32BIT 0x0001
72+/* Switch between timer and counter. */
73+#define TIMER_FLAG_TIMER 0x0000
74+#define TIMER_FLAG_COUNTER 0x0002
75+/* Stop or continue when overflowing/underflowing. */
76+#define TIMER_FLAG_ONCE 0x0000
77+#define TIMER_FLAG_CYCLIC 0x0004
78+/* Count up or counter down. */
79+#define TIMER_FLAG_UP 0x0000
80+#define TIMER_FLAG_DOWN 0x0008
81+/* Count on specific level or edge. */
82+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
83+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
84+#define TIMER_FLAG_RISE_EDGE 0x0010
85+#define TIMER_FLAG_FALL_EDGE 0x0020
86+#define TIMER_FLAG_ANY_EDGE 0x0030
87+/* Signal is syncronous to module clock or not. */
88+#define TIMER_FLAG_UNSYNC 0x0000
89+#define TIMER_FLAG_SYNC 0x0080
90+/* Different interrupt handle type. */
91+#define TIMER_FLAG_NO_HANDLE 0x0000
92+#if defined(__KERNEL__)
93+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
94+#endif // defined(__KERNEL__)
95+#define TIMER_FLAG_SIGNAL 0x0300
96+/* Internal clock source or external clock source */
97+#define TIMER_FLAG_INT_SRC 0x0000
98+#define TIMER_FLAG_EXT_SRC 0x1000
99+
100+
101+/*
102+ * ioctl Command
103+ */
104+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
105+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
106+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
107+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
108+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
109+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
110+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
111+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
112+
113+/*
114+ * Data Type Used to Call ioctl
115+ */
116+struct gptu_ioctl_param {
117+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
118+ * GPTU_SET_COUNTER, this field is ID of expected *
119+ * timer/counter. If it's zero, a timer/counter would *
120+ * be dynamically allocated and ID would be stored in *
121+ * this field. *
122+ * In command GPTU_GET_COUNT_VALUE, this field is *
123+ * ignored. *
124+ * In other command, this field is ID of timer/counter *
125+ * allocated. */
126+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
127+ * GPTU_SET_COUNTER, this field contains flags to *
128+ * specify how to configure timer/counter. *
129+ * In command GPTU_START_TIMER, zero indicate start *
130+ * and non-zero indicate resume timer/counter. *
131+ * In other command, this field is ignored. */
132+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
133+ * init/reload value. *
134+ * In command GPTU_SET_TIMER, this field contains *
135+ * frequency (0.001Hz) of timer. *
136+ * In command GPTU_GET_COUNT_VALUE, current count *
137+ * value would be stored in this field. *
138+ * In command GPTU_CALCULATE_DIVIDER, this field *
139+ * contains frequency wanted, and after calculation, *
140+ * divider would be stored in this field to overwrite *
141+ * the frequency. *
142+ * In other command, this field is ignored. */
143+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
144+ * if signal is required, this field contains process *
145+ * ID to which signal would be sent. *
146+ * In other command, this field is ignored. */
147+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
148+ * if signal is required, this field contains signal *
149+ * number which would be sent. *
150+ * In other command, this field is ignored. */
151+};
152+
153+/*
154+ * ####################################
155+ * Data Type
156+ * ####################################
157+ */
158+typedef void (*timer_callback)(unsigned long arg);
159+
160+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
161+extern int lq_free_timer(unsigned int);
162+extern int lq_start_timer(unsigned int, int);
163+extern int lq_stop_timer(unsigned int);
164+extern int lq_reset_counter_flags(u32 timer, u32 flags);
165+extern int lq_get_count_value(unsigned int, unsigned long *);
166+extern u32 lq_cal_divider(unsigned long);
167+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
168+extern int lq_set_counter(unsigned int timer, unsigned int flag,
169+ u32 reload, unsigned long arg1, unsigned long arg2);
170+
171+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
172--- a/arch/mips/lantiq/xway/Makefile
173+++ b/arch/mips/lantiq/xway/Makefile
174@@ -1,4 +1,4 @@
175-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o
176+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o timer.o
177 
178 obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
179 obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
180--- /dev/null
181+++ b/arch/mips/lantiq/xway/timer.c
182@@ -0,0 +1,830 @@
183+#include <linux/kernel.h>
184+#include <linux/module.h>
185+#include <linux/version.h>
186+#include <linux/types.h>
187+#include <linux/fs.h>
188+#include <linux/miscdevice.h>
189+#include <linux/init.h>
190+#include <linux/uaccess.h>
191+#include <linux/unistd.h>
192+#include <linux/errno.h>
193+#include <linux/interrupt.h>
194+#include <linux/sched.h>
195+
196+#include <asm/irq.h>
197+#include <asm/div64.h>
198+
199+#include <lantiq_soc.h>
200+#include <lantiq_irq.h>
201+#include <lantiq_timer.h>
202+
203+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
204+
205+#ifdef TIMER1A
206+#define FIRST_TIMER TIMER1A
207+#else
208+#define FIRST_TIMER 2
209+#endif
210+
211+/*
212+ * GPTC divider is set or not.
213+ */
214+#define GPTU_CLC_RMC_IS_SET 0
215+
216+/*
217+ * Timer Interrupt (IRQ)
218+ */
219+/* Must be adjusted when ICU driver is available */
220+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
221+
222+/*
223+ * Bits Operation
224+ */
225+#define GET_BITS(x, msb, lsb) \
226+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
227+#define SET_BITS(x, msb, lsb, value) \
228+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
229+ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
230+
231+/*
232+ * GPTU Register Mapping
233+ */
234+#define LQ_GPTU (KSEG1 + 0x1E100A00)
235+#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
236+#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
237+#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
238+#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
239+#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
240+#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
241+#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
242+#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
243+#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
244+
245+/*
246+ * Clock Control Register
247+ */
248+#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
249+#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
250+#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
251+#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
252+#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
253+#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
254+#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
255+
256+#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
257+#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
258+#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
259+#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
260+#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
261+#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
262+#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
263+
264+/*
265+ * ID Register
266+ */
267+#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
268+#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
269+#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
270+
271+/*
272+ * Control Register of Timer/Counter nX
273+ * n is the index of block (1 based index)
274+ * X is either A or B
275+ */
276+#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
277+#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
278+#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
279+#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
280+#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
281+#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
282+#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
283+#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
284+#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
285+#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
286+
287+#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
288+#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
289+#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
290+#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
291+#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
292+#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
293+#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
294+#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
295+#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
296+
297+#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
298+#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
299+#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
300+
301+#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
302+#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
303+
304+#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
305+#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
306+#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
307+#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
308+#define TIMER_FLAG_NONE_EDGE 0x0000
309+#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
310+#define TIMER_FLAG_REAL 0x0000
311+#define TIMER_FLAG_INVERT 0x0040
312+#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
313+#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
314+#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
315+#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
316+#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
317+#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
318+
319+struct timer_dev_timer {
320+ unsigned int f_irq_on;
321+ unsigned int irq;
322+ unsigned int flag;
323+ unsigned long arg1;
324+ unsigned long arg2;
325+};
326+
327+struct timer_dev {
328+ struct mutex gptu_mutex;
329+ unsigned int number_of_timers;
330+ unsigned int occupation;
331+ unsigned int f_gptu_on;
332+ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
333+};
334+
335+unsigned int ltq_get_fpi_bus_clock(int fpi);
336+
337+static long gptu_ioctl(struct file *, unsigned int, unsigned long);
338+static int gptu_open(struct inode *, struct file *);
339+static int gptu_release(struct inode *, struct file *);
340+
341+static struct file_operations gptu_fops = {
342+ .owner = THIS_MODULE,
343+ .unlocked_ioctl = gptu_ioctl,
344+ .open = gptu_open,
345+ .release = gptu_release
346+};
347+
348+static struct miscdevice gptu_miscdev = {
349+ .minor = MISC_DYNAMIC_MINOR,
350+ .name = "gptu",
351+ .fops = &gptu_fops,
352+};
353+
354+static struct timer_dev timer_dev;
355+
356+static irqreturn_t timer_irq_handler(int irq, void *p)
357+{
358+ unsigned int timer;
359+ unsigned int flag;
360+ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
361+
362+ timer = irq - TIMER_INTERRUPT;
363+ if (timer < timer_dev.number_of_timers
364+ && dev_timer == &timer_dev.timer[timer]) {
365+ /* Clear interrupt. */
366+ ltq_w32(1 << timer, LQ_GPTU_IRNCR);
367+
368+ /* Call user hanler or signal. */
369+ flag = dev_timer->flag;
370+ if (!(timer & 0x01)
371+ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
372+ /* 16-bit timer or timer A of 32-bit timer */
373+ switch (TIMER_FLAG_MASK_HANDLE(flag)) {
374+ case TIMER_FLAG_CALLBACK_IN_IRQ:
375+ case TIMER_FLAG_CALLBACK_IN_HB:
376+ if (dev_timer->arg1)
377+ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
378+ break;
379+ case TIMER_FLAG_SIGNAL:
380+ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
381+ break;
382+ }
383+ }
384+ }
385+ return IRQ_HANDLED;
386+}
387+
388+static inline void lq_enable_gptu(void)
389+{
390+ ltq_pmu_enable(PMU_GPT);
391+
392+ /* Set divider as 1, disable write protection for SPEN, enable module. */
393+ *LQ_GPTU_CLC =
394+ GPTU_CLC_SMC_SET(0x00) |
395+ GPTU_CLC_RMC_SET(0x01) |
396+ GPTU_CLC_FSOE_SET(0) |
397+ GPTU_CLC_SBWE_SET(1) |
398+ GPTU_CLC_EDIS_SET(0) |
399+ GPTU_CLC_SPEN_SET(0) |
400+ GPTU_CLC_DISR_SET(0);
401+}
402+
403+static inline void lq_disable_gptu(void)
404+{
405+ ltq_w32(0x00, LQ_GPTU_IRNEN);
406+ ltq_w32(0xfff, LQ_GPTU_IRNCR);
407+
408+ /* Set divider as 0, enable write protection for SPEN, disable module. */
409+ *LQ_GPTU_CLC =
410+ GPTU_CLC_SMC_SET(0x00) |
411+ GPTU_CLC_RMC_SET(0x00) |
412+ GPTU_CLC_FSOE_SET(0) |
413+ GPTU_CLC_SBWE_SET(0) |
414+ GPTU_CLC_EDIS_SET(0) |
415+ GPTU_CLC_SPEN_SET(0) |
416+ GPTU_CLC_DISR_SET(1);
417+
418+ ltq_pmu_disable(PMU_GPT);
419+}
420+
421+int lq_request_timer(unsigned int timer, unsigned int flag,
422+ unsigned long value, unsigned long arg1, unsigned long arg2)
423+{
424+ int ret = 0;
425+ unsigned int con_reg, irnen_reg;
426+ int n, X;
427+
428+ if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
429+ return -EINVAL;
430+
431+ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
432+ timer, flag, value);
433+
434+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
435+ value &= 0xFFFF;
436+ else
437+ timer &= ~0x01;
438+
439+ mutex_lock(&timer_dev.gptu_mutex);
440+
441+ /*
442+ * Allocate timer.
443+ */
444+ if (timer < FIRST_TIMER) {
445+ unsigned int mask;
446+ unsigned int shift;
447+ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
448+ unsigned int offset = TIMER2A;
449+
450+ /*
451+ * Pick up a free timer.
452+ */
453+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
454+ mask = 1 << offset;
455+ shift = 1;
456+ } else {
457+ mask = 3 << offset;
458+ shift = 2;
459+ }
460+ for (timer = offset;
461+ timer < offset + timer_dev.number_of_timers;
462+ timer += shift, mask <<= shift)
463+ if (!(timer_dev.occupation & mask)) {
464+ timer_dev.occupation |= mask;
465+ break;
466+ }
467+ if (timer >= offset + timer_dev.number_of_timers) {
468+ printk("failed![%d]\n", __LINE__);
469+ mutex_unlock(&timer_dev.gptu_mutex);
470+ return -EINVAL;
471+ } else
472+ ret = timer;
473+ } else {
474+ register unsigned int mask;
475+
476+ /*
477+ * Check if the requested timer is free.
478+ */
479+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
480+ if ((timer_dev.occupation & mask)) {
481+ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
482+ __LINE__, mask, timer_dev.occupation);
483+ mutex_unlock(&timer_dev.gptu_mutex);
484+ return -EBUSY;
485+ } else {
486+ timer_dev.occupation |= mask;
487+ ret = 0;
488+ }
489+ }
490+
491+ /*
492+ * Prepare control register value.
493+ */
494+ switch (TIMER_FLAG_MASK_EDGE(flag)) {
495+ default:
496+ case TIMER_FLAG_NONE_EDGE:
497+ con_reg = GPTU_CON_EDGE_SET(0x00);
498+ break;
499+ case TIMER_FLAG_RISE_EDGE:
500+ con_reg = GPTU_CON_EDGE_SET(0x01);
501+ break;
502+ case TIMER_FLAG_FALL_EDGE:
503+ con_reg = GPTU_CON_EDGE_SET(0x02);
504+ break;
505+ case TIMER_FLAG_ANY_EDGE:
506+ con_reg = GPTU_CON_EDGE_SET(0x03);
507+ break;
508+ }
509+ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
510+ con_reg |=
511+ TIMER_FLAG_MASK_SRC(flag) ==
512+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
513+ GPTU_CON_SRC_EXT_SET(0);
514+ else
515+ con_reg |=
516+ TIMER_FLAG_MASK_SRC(flag) ==
517+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
518+ GPTU_CON_SRC_EG_SET(0);
519+ con_reg |=
520+ TIMER_FLAG_MASK_SYNC(flag) ==
521+ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
522+ GPTU_CON_SYNC_SET(1);
523+ con_reg |=
524+ TIMER_FLAG_MASK_INVERT(flag) ==
525+ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
526+ con_reg |=
527+ TIMER_FLAG_MASK_SIZE(flag) ==
528+ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
529+ GPTU_CON_EXT_SET(1);
530+ con_reg |=
531+ TIMER_FLAG_MASK_STOP(flag) ==
532+ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
533+ con_reg |=
534+ TIMER_FLAG_MASK_TYPE(flag) ==
535+ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
536+ GPTU_CON_CNT_SET(1);
537+ con_reg |=
538+ TIMER_FLAG_MASK_DIR(flag) ==
539+ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
540+
541+ /*
542+ * Fill up running data.
543+ */
544+ timer_dev.timer[timer - FIRST_TIMER].flag = flag;
545+ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
546+ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
547+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
548+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
549+
550+ /*
551+ * Enable GPTU module.
552+ */
553+ if (!timer_dev.f_gptu_on) {
554+ lq_enable_gptu();
555+ timer_dev.f_gptu_on = 1;
556+ }
557+
558+ /*
559+ * Enable IRQ.
560+ */
561+ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
562+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
563+ timer_dev.timer[timer - FIRST_TIMER].arg1 =
564+ (unsigned long) find_task_by_vpid((int) arg1);
565+
566+ irnen_reg = 1 << (timer - FIRST_TIMER);
567+
568+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
569+ || (TIMER_FLAG_MASK_HANDLE(flag) ==
570+ TIMER_FLAG_CALLBACK_IN_IRQ
571+ && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
572+ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
573+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
574+ }
575+ } else
576+ irnen_reg = 0;
577+
578+ /*
579+ * Write config register, reload value and enable interrupt.
580+ */
581+ n = timer >> 1;
582+ X = timer & 0x01;
583+ *LQ_GPTU_CON(n, X) = con_reg;
584+ *LQ_GPTU_RELOAD(n, X) = value;
585+ /* printk("reload value = %d\n", (u32)value); */
586+ *LQ_GPTU_IRNEN |= irnen_reg;
587+
588+ mutex_unlock(&timer_dev.gptu_mutex);
589+ printk("successful!\n");
590+ return ret;
591+}
592+EXPORT_SYMBOL(lq_request_timer);
593+
594+int lq_free_timer(unsigned int timer)
595+{
596+ unsigned int flag;
597+ unsigned int mask;
598+ int n, X;
599+
600+ if (!timer_dev.f_gptu_on)
601+ return -EINVAL;
602+
603+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
604+ return -EINVAL;
605+
606+ mutex_lock(&timer_dev.gptu_mutex);
607+
608+ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
609+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
610+ timer &= ~0x01;
611+
612+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
613+ if (((timer_dev.occupation & mask) ^ mask)) {
614+ mutex_unlock(&timer_dev.gptu_mutex);
615+ return -EINVAL;
616+ }
617+
618+ n = timer >> 1;
619+ X = timer & 0x01;
620+
621+ if (GPTU_CON_EN(n, X))
622+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
623+
624+ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
625+ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
626+
627+ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
628+ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
629+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
630+ }
631+
632+ timer_dev.occupation &= ~mask;
633+ if (!timer_dev.occupation && timer_dev.f_gptu_on) {
634+ lq_disable_gptu();
635+ timer_dev.f_gptu_on = 0;
636+ }
637+
638+ mutex_unlock(&timer_dev.gptu_mutex);
639+
640+ return 0;
641+}
642+EXPORT_SYMBOL(lq_free_timer);
643+
644+int lq_start_timer(unsigned int timer, int is_resume)
645+{
646+ unsigned int flag;
647+ unsigned int mask;
648+ int n, X;
649+
650+ if (!timer_dev.f_gptu_on)
651+ return -EINVAL;
652+
653+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
654+ return -EINVAL;
655+
656+ mutex_lock(&timer_dev.gptu_mutex);
657+
658+ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
659+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
660+ timer &= ~0x01;
661+
662+ mask = (TIMER_FLAG_MASK_SIZE(flag) ==
663+ TIMER_FLAG_16BIT ? 1 : 3) << timer;
664+ if (((timer_dev.occupation & mask) ^ mask)) {
665+ mutex_unlock(&timer_dev.gptu_mutex);
666+ return -EINVAL;
667+ }
668+
669+ n = timer >> 1;
670+ X = timer & 0x01;
671+
672+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
673+
674+ mutex_unlock(&timer_dev.gptu_mutex);
675+
676+ return 0;
677+}
678+EXPORT_SYMBOL(lq_start_timer);
679+
680+int lq_stop_timer(unsigned int timer)
681+{
682+ unsigned int flag;
683+ unsigned int mask;
684+ int n, X;
685+
686+ if (!timer_dev.f_gptu_on)
687+ return -EINVAL;
688+
689+ if (timer < FIRST_TIMER
690+ || timer >= FIRST_TIMER + timer_dev.number_of_timers)
691+ return -EINVAL;
692+
693+ mutex_lock(&timer_dev.gptu_mutex);
694+
695+ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
696+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
697+ timer &= ~0x01;
698+
699+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
700+ if (((timer_dev.occupation & mask) ^ mask)) {
701+ mutex_unlock(&timer_dev.gptu_mutex);
702+ return -EINVAL;
703+ }
704+
705+ n = timer >> 1;
706+ X = timer & 0x01;
707+
708+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
709+
710+ mutex_unlock(&timer_dev.gptu_mutex);
711+
712+ return 0;
713+}
714+EXPORT_SYMBOL(lq_stop_timer);
715+
716+int lq_reset_counter_flags(u32 timer, u32 flags)
717+{
718+ unsigned int oflag;
719+ unsigned int mask, con_reg;
720+ int n, X;
721+
722+ if (!timer_dev.f_gptu_on)
723+ return -EINVAL;
724+
725+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
726+ return -EINVAL;
727+
728+ mutex_lock(&timer_dev.gptu_mutex);
729+
730+ oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
731+ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
732+ timer &= ~0x01;
733+
734+ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
735+ if (((timer_dev.occupation & mask) ^ mask)) {
736+ mutex_unlock(&timer_dev.gptu_mutex);
737+ return -EINVAL;
738+ }
739+
740+ switch (TIMER_FLAG_MASK_EDGE(flags)) {
741+ default:
742+ case TIMER_FLAG_NONE_EDGE:
743+ con_reg = GPTU_CON_EDGE_SET(0x00);
744+ break;
745+ case TIMER_FLAG_RISE_EDGE:
746+ con_reg = GPTU_CON_EDGE_SET(0x01);
747+ break;
748+ case TIMER_FLAG_FALL_EDGE:
749+ con_reg = GPTU_CON_EDGE_SET(0x02);
750+ break;
751+ case TIMER_FLAG_ANY_EDGE:
752+ con_reg = GPTU_CON_EDGE_SET(0x03);
753+ break;
754+ }
755+ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
756+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
757+ else
758+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
759+ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
760+ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
761+ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
762+ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
763+ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
764+ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
765+
766+ timer_dev.timer[timer - FIRST_TIMER].flag = flags;
767+ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
768+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
769+
770+ n = timer >> 1;
771+ X = timer & 0x01;
772+
773+ *LQ_GPTU_CON(n, X) = con_reg;
774+ smp_wmb();
775+ printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
776+ mutex_unlock(&timer_dev.gptu_mutex);
777+ return 0;
778+}
779+EXPORT_SYMBOL(lq_reset_counter_flags);
780+
781+int lq_get_count_value(unsigned int timer, unsigned long *value)
782+{
783+ unsigned int flag;
784+ unsigned int mask;
785+ int n, X;
786+
787+ if (!timer_dev.f_gptu_on)
788+ return -EINVAL;
789+
790+ if (timer < FIRST_TIMER
791+ || timer >= FIRST_TIMER + timer_dev.number_of_timers)
792+ return -EINVAL;
793+
794+ mutex_lock(&timer_dev.gptu_mutex);
795+
796+ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
797+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
798+ timer &= ~0x01;
799+
800+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
801+ if (((timer_dev.occupation & mask) ^ mask)) {
802+ mutex_unlock(&timer_dev.gptu_mutex);
803+ return -EINVAL;
804+ }
805+
806+ n = timer >> 1;
807+ X = timer & 0x01;
808+
809+ *value = *LQ_GPTU_COUNT(n, X);
810+
811+ mutex_unlock(&timer_dev.gptu_mutex);
812+
813+ return 0;
814+}
815+EXPORT_SYMBOL(lq_get_count_value);
816+
817+u32 lq_cal_divider(unsigned long freq)
818+{
819+ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
820+ u32 clock_divider = 1;
821+ module_freq = fpi * 1000;
822+ do_div(module_freq, clock_divider * freq);
823+ return module_freq;
824+}
825+EXPORT_SYMBOL(lq_cal_divider);
826+
827+int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
828+ int is_ext_src, unsigned int handle_flag, unsigned long arg1,
829+ unsigned long arg2)
830+{
831+ unsigned long divider;
832+ unsigned int flag;
833+
834+ divider = lq_cal_divider(freq);
835+ if (divider == 0)
836+ return -EINVAL;
837+ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
838+ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
839+ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
840+ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
841+ | TIMER_FLAG_MASK_HANDLE(handle_flag);
842+
843+ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
844+ timer, freq, divider);
845+ return lq_request_timer(timer, flag, divider, arg1, arg2);
846+}
847+EXPORT_SYMBOL(lq_set_timer);
848+
849+int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
850+ unsigned long arg1, unsigned long arg2)
851+{
852+ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
853+ return lq_request_timer(timer, flag, reload, arg1, arg2);
854+}
855+EXPORT_SYMBOL(lq_set_counter);
856+
857+static long gptu_ioctl(struct file *file, unsigned int cmd,
858+ unsigned long arg)
859+{
860+ int ret;
861+ struct gptu_ioctl_param param;
862+
863+ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
864+ return -EFAULT;
865+ copy_from_user(&param, (void *) arg, sizeof(param));
866+
867+ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
868+ || GPTU_SET_COUNTER) && param.timer < 2)
869+ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
870+ && !access_ok(VERIFY_WRITE, arg,
871+ sizeof(struct gptu_ioctl_param)))
872+ return -EFAULT;
873+
874+ switch (cmd) {
875+ case GPTU_REQUEST_TIMER:
876+ ret = lq_request_timer(param.timer, param.flag, param.value,
877+ (unsigned long) param.pid,
878+ (unsigned long) param.sig);
879+ if (ret > 0) {
880+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
881+ timer, &ret, sizeof(&ret));
882+ ret = 0;
883+ }
884+ break;
885+ case GPTU_FREE_TIMER:
886+ ret = lq_free_timer(param.timer);
887+ break;
888+ case GPTU_START_TIMER:
889+ ret = lq_start_timer(param.timer, param.flag);
890+ break;
891+ case GPTU_STOP_TIMER:
892+ ret = lq_stop_timer(param.timer);
893+ break;
894+ case GPTU_GET_COUNT_VALUE:
895+ ret = lq_get_count_value(param.timer, &param.value);
896+ if (!ret)
897+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
898+ value, &param.value,
899+ sizeof(param.value));
900+ break;
901+ case GPTU_CALCULATE_DIVIDER:
902+ param.value = lq_cal_divider(param.value);
903+ if (param.value == 0)
904+ ret = -EINVAL;
905+ else {
906+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
907+ value, &param.value,
908+ sizeof(param.value));
909+ ret = 0;
910+ }
911+ break;
912+ case GPTU_SET_TIMER:
913+ ret = lq_set_timer(param.timer, param.value,
914+ TIMER_FLAG_MASK_STOP(param.flag) !=
915+ TIMER_FLAG_ONCE ? 1 : 0,
916+ TIMER_FLAG_MASK_SRC(param.flag) ==
917+ TIMER_FLAG_EXT_SRC ? 1 : 0,
918+ TIMER_FLAG_MASK_HANDLE(param.flag) ==
919+ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
920+ TIMER_FLAG_NO_HANDLE,
921+ (unsigned long) param.pid,
922+ (unsigned long) param.sig);
923+ if (ret > 0) {
924+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
925+ timer, &ret, sizeof(&ret));
926+ ret = 0;
927+ }
928+ break;
929+ case GPTU_SET_COUNTER:
930+ lq_set_counter(param.timer, param.flag, param.value, 0, 0);
931+ if (ret > 0) {
932+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
933+ timer, &ret, sizeof(&ret));
934+ ret = 0;
935+ }
936+ break;
937+ default:
938+ ret = -ENOTTY;
939+ }
940+
941+ return ret;
942+}
943+
944+static int gptu_open(struct inode *inode, struct file *file)
945+{
946+ return 0;
947+}
948+
949+static int gptu_release(struct inode *inode, struct file *file)
950+{
951+ return 0;
952+}
953+
954+int __init lq_gptu_init(void)
955+{
956+ int ret;
957+ unsigned int i;
958+
959+ ltq_w32(0, LQ_GPTU_IRNEN);
960+ ltq_w32(0xfff, LQ_GPTU_IRNCR);
961+
962+ memset(&timer_dev, 0, sizeof(timer_dev));
963+ mutex_init(&timer_dev.gptu_mutex);
964+
965+ lq_enable_gptu();
966+ timer_dev.number_of_timers = GPTU_ID_CFG * 2;
967+ lq_disable_gptu();
968+ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
969+ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
970+ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
971+
972+ ret = misc_register(&gptu_miscdev);
973+ if (ret) {
974+ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
975+ return ret;
976+ } else {
977+ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
978+ }
979+
980+ for (i = 0; i < timer_dev.number_of_timers; i++) {
981+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
982+ if (ret) {
983+ for (; i >= 0; i--)
984+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
985+ misc_deregister(&gptu_miscdev);
986+ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
987+ return ret;
988+ } else {
989+ timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
990+ disable_irq(timer_dev.timer[i].irq);
991+ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
992+ }
993+ }
994+
995+ return 0;
996+}
997+
998+void __exit lq_gptu_exit(void)
999+{
1000+ unsigned int i;
1001+
1002+ for (i = 0; i < timer_dev.number_of_timers; i++) {
1003+ if (timer_dev.timer[i].f_irq_on)
1004+ disable_irq(timer_dev.timer[i].irq);
1005+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1006+ }
1007+ lq_disable_gptu();
1008+ misc_deregister(&gptu_miscdev);
1009+}
1010+
1011+module_init(lq_gptu_init);
1012+module_exit(lq_gptu_exit);
1013

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