Root/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd.h

1/* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
3 * $Revision: 1.3 $
4 * $Date: 2008-12-15 06:51:32 $
5 * $Change: 1064918 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33#ifndef DWC_DEVICE_ONLY
34#ifndef __DWC_HCD_H__
35#define __DWC_HCD_H__
36
37#include <linux/list.h>
38#include <linux/usb.h>
39#include <linux/usb/hcd.h>
40
41struct dwc_otg_device;
42
43#include "dwc_otg_cil.h"
44
45/**
46 * @file
47 *
48 * This file contains the structures, constants, and interfaces for
49 * the Host Contoller Driver (HCD).
50 *
51 * The Host Controller Driver (HCD) is responsible for translating requests
52 * from the USB Driver into the appropriate actions on the DWC_otg controller.
53 * It isolates the USBD from the specifics of the controller by providing an
54 * API to the USBD.
55 */
56
57/**
58 * Phases for control transfers.
59 */
60typedef enum dwc_otg_control_phase {
61    DWC_OTG_CONTROL_SETUP,
62    DWC_OTG_CONTROL_DATA,
63    DWC_OTG_CONTROL_STATUS
64} dwc_otg_control_phase_e;
65
66/** Transaction types. */
67typedef enum dwc_otg_transaction_type {
68    DWC_OTG_TRANSACTION_NONE,
69    DWC_OTG_TRANSACTION_PERIODIC,
70    DWC_OTG_TRANSACTION_NON_PERIODIC,
71    DWC_OTG_TRANSACTION_ALL
72} dwc_otg_transaction_type_e;
73
74/**
75 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
76 * interrupt, or isochronous transfer. A single QTD is created for each URB
77 * (of one of these types) submitted to the HCD. The transfer associated with
78 * a QTD may require one or multiple transactions.
79 *
80 * A QTD is linked to a Queue Head, which is entered in either the
81 * non-periodic or periodic schedule for execution. When a QTD is chosen for
82 * execution, some or all of its transactions may be executed. After
83 * execution, the state of the QTD is updated. The QTD may be retired if all
84 * its transactions are complete or if an error occurred. Otherwise, it
85 * remains in the schedule so more transactions can be executed later.
86 */
87typedef struct dwc_otg_qtd {
88    /**
89     * Determines the PID of the next data packet for the data phase of
90     * control transfers. Ignored for other transfer types.<br>
91     * One of the following values:
92     * - DWC_OTG_HC_PID_DATA0
93     * - DWC_OTG_HC_PID_DATA1
94     */
95    uint8_t data_toggle;
96
97    /** Current phase for control transfers (Setup, Data, or Status). */
98    dwc_otg_control_phase_e control_phase;
99
100    /** Keep track of the current split type
101     * for FS/LS endpoints on a HS Hub */
102    uint8_t complete_split;
103
104    /** How many bytes transferred during SSPLIT OUT */
105    uint32_t ssplit_out_xfer_count;
106
107    /**
108     * Holds the number of bus errors that have occurred for a transaction
109     * within this transfer.
110     */
111    uint8_t error_count;
112
113    /**
114     * Index of the next frame descriptor for an isochronous transfer. A
115     * frame descriptor describes the buffer position and length of the
116     * data to be transferred in the next scheduled (micro)frame of an
117     * isochronous transfer. It also holds status for that transaction.
118     * The frame index starts at 0.
119     */
120    int isoc_frame_index;
121
122    /** Position of the ISOC split on full/low speed */
123    uint8_t isoc_split_pos;
124
125    /** Position of the ISOC split in the buffer for the current frame */
126    uint16_t isoc_split_offset;
127
128    /** URB for this transfer */
129    struct urb *urb;
130
131    /** This list of QTDs */
132    struct list_head qtd_list_entry;
133
134} dwc_otg_qtd_t;
135
136/**
137 * A Queue Head (QH) holds the static characteristics of an endpoint and
138 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
139 * be entered in either the non-periodic or periodic schedule.
140 */
141typedef struct dwc_otg_qh {
142    /**
143     * Endpoint type.
144     * One of the following values:
145     * - USB_ENDPOINT_XFER_CONTROL
146     * - USB_ENDPOINT_XFER_ISOC
147     * - USB_ENDPOINT_XFER_BULK
148     * - USB_ENDPOINT_XFER_INT
149     */
150    uint8_t ep_type;
151    uint8_t ep_is_in;
152
153    /** wMaxPacketSize Field of Endpoint Descriptor. */
154    uint16_t maxp;
155
156    /**
157     * Determines the PID of the next data packet for non-control
158     * transfers. Ignored for control transfers.<br>
159     * One of the following values:
160     * - DWC_OTG_HC_PID_DATA0
161     * - DWC_OTG_HC_PID_DATA1
162     */
163    uint8_t data_toggle;
164
165    /** Ping state if 1. */
166    uint8_t ping_state;
167
168    /**
169     * List of QTDs for this QH.
170     */
171    struct list_head qtd_list;
172
173    /** Host channel currently processing transfers for this QH. */
174    dwc_hc_t *channel;
175
176    /** QTD currently assigned to a host channel for this QH. */
177    dwc_otg_qtd_t *qtd_in_process;
178
179    /** Full/low speed endpoint on high-speed hub requires split. */
180    uint8_t do_split;
181
182    /** @name Periodic schedule information */
183    /** @{ */
184
185    /** Bandwidth in microseconds per (micro)frame. */
186    uint8_t usecs;
187
188    /** Interval between transfers in (micro)frames. */
189    uint16_t interval;
190
191    /**
192     * (micro)frame to initialize a periodic transfer. The transfer
193     * executes in the following (micro)frame.
194     */
195    uint16_t sched_frame;
196
197    /** (micro)frame at which last start split was initialized. */
198    uint16_t start_split_frame;
199
200    /** @} */
201
202    /** Entry for QH in either the periodic or non-periodic schedule. */
203    struct list_head qh_list_entry;
204
205    /* For non-dword aligned buffer support */
206    uint8_t *dw_align_buf;
207    dma_addr_t dw_align_buf_dma;
208} dwc_otg_qh_t;
209
210/**
211 * This structure holds the state of the HCD, including the non-periodic and
212 * periodic schedules.
213 */
214typedef struct dwc_otg_hcd {
215    /** The DWC otg device pointer */
216    struct dwc_otg_device *otg_dev;
217
218    /** DWC OTG Core Interface Layer */
219    dwc_otg_core_if_t *core_if;
220
221    /** Internal DWC HCD Flags */
222    volatile union dwc_otg_hcd_internal_flags {
223        uint32_t d32;
224        struct {
225            unsigned port_connect_status_change : 1;
226            unsigned port_connect_status : 1;
227            unsigned port_reset_change : 1;
228            unsigned port_enable_change : 1;
229            unsigned port_suspend_change : 1;
230            unsigned port_over_current_change : 1;
231            unsigned reserved : 27;
232        } b;
233    } flags;
234
235    /**
236     * Inactive items in the non-periodic schedule. This is a list of
237     * Queue Heads. Transfers associated with these Queue Heads are not
238     * currently assigned to a host channel.
239     */
240    struct list_head non_periodic_sched_inactive;
241
242    /**
243     * Active items in the non-periodic schedule. This is a list of
244     * Queue Heads. Transfers associated with these Queue Heads are
245     * currently assigned to a host channel.
246     */
247    struct list_head non_periodic_sched_active;
248
249    /**
250     * Pointer to the next Queue Head to process in the active
251     * non-periodic schedule.
252     */
253    struct list_head *non_periodic_qh_ptr;
254
255    /**
256     * Inactive items in the periodic schedule. This is a list of QHs for
257     * periodic transfers that are _not_ scheduled for the next frame.
258     * Each QH in the list has an interval counter that determines when it
259     * needs to be scheduled for execution. This scheduling mechanism
260     * allows only a simple calculation for periodic bandwidth used (i.e.
261     * must assume that all periodic transfers may need to execute in the
262     * same frame). However, it greatly simplifies scheduling and should
263     * be sufficient for the vast majority of OTG hosts, which need to
264     * connect to a small number of peripherals at one time.
265     *
266     * Items move from this list to periodic_sched_ready when the QH
267     * interval counter is 0 at SOF.
268     */
269    struct list_head periodic_sched_inactive;
270
271    /**
272     * List of periodic QHs that are ready for execution in the next
273     * frame, but have not yet been assigned to host channels.
274     *
275     * Items move from this list to periodic_sched_assigned as host
276     * channels become available during the current frame.
277     */
278    struct list_head periodic_sched_ready;
279
280    /**
281     * List of periodic QHs to be executed in the next frame that are
282     * assigned to host channels.
283     *
284     * Items move from this list to periodic_sched_queued as the
285     * transactions for the QH are queued to the DWC_otg controller.
286     */
287    struct list_head periodic_sched_assigned;
288
289    /**
290     * List of periodic QHs that have been queued for execution.
291     *
292     * Items move from this list to either periodic_sched_inactive or
293     * periodic_sched_ready when the channel associated with the transfer
294     * is released. If the interval for the QH is 1, the item moves to
295     * periodic_sched_ready because it must be rescheduled for the next
296     * frame. Otherwise, the item moves to periodic_sched_inactive.
297     */
298    struct list_head periodic_sched_queued;
299
300    /**
301     * Total bandwidth claimed so far for periodic transfers. This value
302     * is in microseconds per (micro)frame. The assumption is that all
303     * periodic transfers may occur in the same (micro)frame.
304     */
305    uint16_t periodic_usecs;
306
307    /**
308     * Frame number read from the core at SOF. The value ranges from 0 to
309     * DWC_HFNUM_MAX_FRNUM.
310     */
311    uint16_t frame_number;
312
313    /**
314     * Free host channels in the controller. This is a list of
315     * dwc_hc_t items.
316     */
317    struct list_head free_hc_list;
318
319    /**
320     * Number of host channels assigned to periodic transfers. Currently
321     * assuming that there is a dedicated host channel for each periodic
322     * transaction and at least one host channel available for
323     * non-periodic transactions.
324     */
325    int periodic_channels;
326
327    /**
328     * Number of host channels assigned to non-periodic transfers.
329     */
330    int non_periodic_channels;
331
332    /**
333     * Array of pointers to the host channel descriptors. Allows accessing
334     * a host channel descriptor given the host channel number. This is
335     * useful in interrupt handlers.
336     */
337    dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
338
339    /**
340     * Buffer to use for any data received during the status phase of a
341     * control transfer. Normally no data is transferred during the status
342     * phase. This buffer is used as a bit bucket.
343     */
344    uint8_t *status_buf;
345
346    /**
347     * DMA address for status_buf.
348     */
349    dma_addr_t status_buf_dma;
350#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
351
352    /**
353     * Structure to allow starting the HCD in a non-interrupt context
354     * during an OTG role change.
355     */
356#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
357    struct work_struct start_work;
358#else
359    struct delayed_work start_work;
360#endif
361
362    /**
363     * Connection timer. An OTG host must display a message if the device
364     * does not connect. Started when the VBus power is turned on via
365     * sysfs attribute "buspower".
366     */
367    struct timer_list conn_timer;
368
369    /* Tasket to do a reset */
370    struct tasklet_struct *reset_tasklet;
371
372    /* */
373    spinlock_t lock;
374
375#ifdef DEBUG
376    uint32_t frrem_samples;
377    uint64_t frrem_accum;
378
379    uint32_t hfnum_7_samples_a;
380    uint64_t hfnum_7_frrem_accum_a;
381    uint32_t hfnum_0_samples_a;
382    uint64_t hfnum_0_frrem_accum_a;
383    uint32_t hfnum_other_samples_a;
384    uint64_t hfnum_other_frrem_accum_a;
385
386    uint32_t hfnum_7_samples_b;
387    uint64_t hfnum_7_frrem_accum_b;
388    uint32_t hfnum_0_samples_b;
389    uint64_t hfnum_0_frrem_accum_b;
390    uint32_t hfnum_other_samples_b;
391    uint64_t hfnum_other_frrem_accum_b;
392#endif
393} dwc_otg_hcd_t;
394
395/** Gets the dwc_otg_hcd from a struct usb_hcd */
396static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
397{
398    return (dwc_otg_hcd_t *)(hcd->hcd_priv);
399}
400
401/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
402static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
403{
404    return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
405}
406
407/** @name HCD Create/Destroy Functions */
408/** @{ */
409extern int dwc_otg_hcd_init(struct device *dev);
410extern void dwc_otg_hcd_remove(struct device *dev);
411/** @} */
412
413/** @name Linux HC Driver API Functions */
414/** @{ */
415
416extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
417extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
418extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
419extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
420extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
421                   struct urb *urb,
422#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
423                   int mem_flags
424#else
425                   gfp_t mem_flags
426#endif
427                  );
428extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
429#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
430#endif
431                   struct urb *urb, int status);
432extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
433                     struct usb_host_endpoint *ep);
434extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd
435#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
436                   , struct pt_regs *regs
437#endif
438                  );
439extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
440                       char *buf);
441extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
442                   u16 typeReq,
443                   u16 wValue,
444                   u16 wIndex,
445                   char *buf,
446                   u16 wLength);
447
448/** @} */
449
450/** @name Transaction Execution Functions */
451/** @{ */
452extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd);
453extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
454                       dwc_otg_transaction_type_e tr_type);
455extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb,
456                     int status);
457/** @} */
458
459/** @name Interrupt Handler Functions */
460/** @{ */
461extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd);
462extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd);
463extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd);
464extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
465extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
466extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd);
467extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd);
468extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd);
469extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd);
470extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd);
471extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num);
472extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd);
473extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd);
474/** @} */
475
476
477/** @name Schedule Queue Functions */
478/** @{ */
479
480/* Implemented in dwc_otg_hcd_queue.c */
481extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
482extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
483extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
484extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
485extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
486extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit);
487
488/** Remove and free a QH */
489static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd,
490                          dwc_otg_qh_t *qh)
491{
492    dwc_otg_hcd_qh_remove(hcd, qh);
493    dwc_otg_hcd_qh_free(hcd, qh);
494}
495
496/** Allocates memory for a QH structure.
497 * @return Returns the memory allocate or NULL on error. */
498static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
499{
500    return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL);
501}
502
503extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb);
504extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb);
505extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
506
507/** Allocates memory for a QTD structure.
508 * @return Returns the memory allocate or NULL on error. */
509static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
510{
511    return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL);
512}
513
514/** Frees the memory for a QTD structure. QTD should already be removed from
515 * list.
516 * @param[in] qtd QTD to free.*/
517static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd)
518{
519    kfree(qtd);
520}
521
522/** Removes a QTD from list.
523 * @param[in] hcd HCD instance.
524 * @param[in] qtd QTD to remove from list. */
525static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
526{
527    unsigned long flags;
528    SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
529    list_del(&qtd->qtd_list_entry);
530    SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
531}
532
533/** Remove and free a QTD */
534static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
535{
536    dwc_otg_hcd_qtd_remove(hcd, qtd);
537    dwc_otg_hcd_qtd_free(qtd);
538}
539
540/** @} */
541
542
543/** @name Internal Functions */
544/** @{ */
545dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb);
546void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd);
547void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd);
548/** @} */
549
550/** Gets the usb_host_endpoint associated with an URB. */
551static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
552{
553    struct usb_device *dev = urb->dev;
554    int ep_num = usb_pipeendpoint(urb->pipe);
555
556    if (usb_pipein(urb->pipe))
557        return dev->ep_in[ep_num];
558    else
559        return dev->ep_out[ep_num];
560}
561
562/**
563 * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
564 * qualified with its direction (possible 32 endpoints per device).
565 */
566#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
567                             ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
568
569/** Gets the QH that contains the list_head */
570#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
571
572/** Gets the QTD that contains the list_head */
573#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
574
575/** Check if QH is non-periodic */
576#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
577                     (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
578
579/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
580#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
581
582/** Packet size for any kind of endpoint descriptor */
583#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
584
585/**
586 * Returns true if _frame1 is less than or equal to _frame2. The comparison is
587 * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
588 * frame number when the max frame number is reached.
589 */
590static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
591{
592    return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
593        (DWC_HFNUM_MAX_FRNUM >> 1);
594}
595
596/**
597 * Returns true if _frame1 is greater than _frame2. The comparison is done
598 * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
599 * number when the max frame number is reached.
600 */
601static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
602{
603    return (frame1 != frame2) &&
604        (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
605         (DWC_HFNUM_MAX_FRNUM >> 1));
606}
607
608/**
609 * Increments _frame by the amount specified by _inc. The addition is done
610 * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
611 */
612static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
613{
614    return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
615}
616
617static inline uint16_t dwc_full_frame_num(uint16_t frame)
618{
619    return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
620}
621
622static inline uint16_t dwc_micro_frame_num(uint16_t frame)
623{
624    return frame & 0x7;
625}
626
627#ifdef DEBUG
628/**
629 * Macro to sample the remaining PHY clocks left in the current frame. This
630 * may be used during debugging to determine the average time it takes to
631 * execute sections of code. There are two possible sample points, "a" and
632 * "b", so the _letter argument must be one of these values.
633 *
634 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
635 * example, "cat /sys/devices/lm0/hcd_frrem".
636 */
637#define dwc_sample_frrem(_hcd, _qh, _letter) \
638{ \
639    hfnum_data_t hfnum; \
640    dwc_otg_qtd_t *qtd; \
641    qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
642    if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
643        hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
644        switch (hfnum.b.frnum & 0x7) { \
645        case 7: \
646            _hcd->hfnum_7_samples_##_letter++; \
647            _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
648            break; \
649        case 0: \
650            _hcd->hfnum_0_samples_##_letter++; \
651            _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
652            break; \
653        default: \
654            _hcd->hfnum_other_samples_##_letter++; \
655            _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
656            break; \
657        } \
658    } \
659}
660#else
661#define dwc_sample_frrem(_hcd, _qh, _letter)
662#endif
663#endif
664#endif /* DWC_DEVICE_ONLY */
665

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