| 1 | /* |
| 2 | * AR6K Driver layer event handling (i.e. interrupts, message polling) |
| 3 | * |
| 4 | * Copyright (c) 2007 Atheros Communications Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation; |
| 11 | * |
| 12 | * Software distributed under the License is distributed on an "AS |
| 13 | * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 14 | * implied. See the License for the specific language governing |
| 15 | * rights and limitations under the License. |
| 16 | * |
| 17 | * |
| 18 | * |
| 19 | */ |
| 20 | #include "a_config.h" |
| 21 | #include "athdefs.h" |
| 22 | #include "a_types.h" |
| 23 | #include "AR6Khwreg.h" |
| 24 | #include "a_osapi.h" |
| 25 | #include "a_debug.h" |
| 26 | #include "hif.h" |
| 27 | #include "htc_packet.h" |
| 28 | #include "ar6k.h" |
| 29 | |
| 30 | extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket); |
| 31 | extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev); |
| 32 | |
| 33 | static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev); |
| 34 | |
| 35 | #define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */ |
| 36 | |
| 37 | /* completion routine for ALL HIF layer async I/O */ |
| 38 | A_STATUS DevRWCompletionHandler(void *context, A_STATUS status) |
| 39 | { |
| 40 | HTC_PACKET *pPacket = (HTC_PACKET *)context; |
| 41 | |
| 42 | COMPLETE_HTC_PACKET(pPacket,status); |
| 43 | |
| 44 | return A_OK; |
| 45 | } |
| 46 | |
| 47 | /* mailbox recv message polling */ |
| 48 | A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, |
| 49 | A_UINT32 *pLookAhead, |
| 50 | int TimeoutMS) |
| 51 | { |
| 52 | A_STATUS status = A_OK; |
| 53 | int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS; |
| 54 | |
| 55 | AR_DEBUG_ASSERT(timeout > 0); |
| 56 | |
| 57 | AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n")); |
| 58 | |
| 59 | while (TRUE) { |
| 60 | |
| 61 | if (pDev->GetPendingEventsFunc != NULL) |
| 62 | { |
| 63 | |
| 64 | HIF_PENDING_EVENTS_INFO events; |
| 65 | |
| 66 | /* the HIF layer uses a special mechanism to get events, do this |
| 67 | * synchronously */ |
| 68 | status = pDev->GetPendingEventsFunc(pDev->HIFDevice, |
| 69 | &events, |
| 70 | NULL); |
| 71 | if (A_FAILED(status)) |
| 72 | { |
| 73 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n")); |
| 74 | break; |
| 75 | } |
| 76 | |
| 77 | if (events.Events & HIF_RECV_MSG_AVAIL) |
| 78 | { |
| 79 | /* there is a message available, the lookahead should be valid now */ |
| 80 | *pLookAhead = events.LookAhead; |
| 81 | |
| 82 | break; |
| 83 | } |
| 84 | } |
| 85 | else |
| 86 | { |
| 87 | |
| 88 | /* this is the standard HIF way.... */ |
| 89 | /* load the register table */ |
| 90 | status = HIFReadWrite(pDev->HIFDevice, |
| 91 | HOST_INT_STATUS_ADDRESS, |
| 92 | (A_UINT8 *)&pDev->IrqProcRegisters, |
| 93 | AR6K_IRQ_PROC_REGS_SIZE, |
| 94 | HIF_RD_SYNC_BYTE_INC, |
| 95 | NULL); |
| 96 | |
| 97 | if (A_FAILED(status)) |
| 98 | { |
| 99 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n")); |
| 100 | break; |
| 101 | } |
| 102 | |
| 103 | /* check for MBOX data and valid lookahead */ |
| 104 | if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) |
| 105 | { |
| 106 | if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) |
| 107 | { |
| 108 | /* mailbox has a message and the look ahead is valid */ |
| 109 | *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; |
| 110 | break; |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | } |
| 115 | |
| 116 | timeout--; |
| 117 | |
| 118 | if (timeout <= 0) |
| 119 | { |
| 120 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n")); |
| 121 | status = A_ERROR; |
| 122 | |
| 123 | /* check if the target asserted */ |
| 124 | if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { |
| 125 | /* target signaled an assert, process this pending interrupt |
| 126 | * this will call the target failure handler */ |
| 127 | DevServiceDebugInterrupt(pDev); |
| 128 | } |
| 129 | |
| 130 | break; |
| 131 | } |
| 132 | |
| 133 | /* delay a little */ |
| 134 | msleep(DELAY_PER_INTERVAL_MS); |
| 135 | AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout)); |
| 136 | } |
| 137 | |
| 138 | AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n")); |
| 139 | |
| 140 | return status; |
| 141 | } |
| 142 | |
| 143 | static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev) |
| 144 | { |
| 145 | A_STATUS status; |
| 146 | A_UINT8 cpu_int_status; |
| 147 | A_UINT8 regBuffer[4]; |
| 148 | |
| 149 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n")); |
| 150 | cpu_int_status = pDev->IrqProcRegisters.cpu_int_status & |
| 151 | pDev->IrqEnableRegisters.cpu_int_status_enable; |
| 152 | AR_DEBUG_ASSERT(cpu_int_status); |
| 153 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, |
| 154 | ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", |
| 155 | cpu_int_status)); |
| 156 | |
| 157 | /* Clear the interrupt */ |
| 158 | pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */ |
| 159 | |
| 160 | /* set up the register transfer buffer to hit the register 4 times , this is done |
| 161 | * to make the access 4-byte aligned to mitigate issues with host bus interconnects that |
| 162 | * restrict bus transfer lengths to be a multiple of 4-bytes */ |
| 163 | |
| 164 | /* set W1C value to clear the interrupt, this hits the register first */ |
| 165 | regBuffer[0] = cpu_int_status; |
| 166 | /* the remaining 4 values are set to zero which have no-effect */ |
| 167 | regBuffer[1] = 0; |
| 168 | regBuffer[2] = 0; |
| 169 | regBuffer[3] = 0; |
| 170 | |
| 171 | status = HIFReadWrite(pDev->HIFDevice, |
| 172 | CPU_INT_STATUS_ADDRESS, |
| 173 | regBuffer, |
| 174 | 4, |
| 175 | HIF_WR_SYNC_BYTE_FIX, |
| 176 | NULL); |
| 177 | |
| 178 | AR_DEBUG_ASSERT(status == A_OK); |
| 179 | return status; |
| 180 | } |
| 181 | |
| 182 | |
| 183 | static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev) |
| 184 | { |
| 185 | A_STATUS status; |
| 186 | A_UINT8 error_int_status; |
| 187 | A_UINT8 regBuffer[4]; |
| 188 | |
| 189 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n")); |
| 190 | error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F; |
| 191 | AR_DEBUG_ASSERT(error_int_status); |
| 192 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, |
| 193 | ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", |
| 194 | error_int_status)); |
| 195 | |
| 196 | if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) { |
| 197 | /* Wakeup */ |
| 198 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n")); |
| 199 | } |
| 200 | |
| 201 | if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) { |
| 202 | /* Rx Underflow */ |
| 203 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n")); |
| 204 | } |
| 205 | |
| 206 | if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) { |
| 207 | /* Tx Overflow */ |
| 208 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n")); |
| 209 | } |
| 210 | |
| 211 | /* Clear the interrupt */ |
| 212 | pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */ |
| 213 | |
| 214 | /* set up the register transfer buffer to hit the register 4 times , this is done |
| 215 | * to make the access 4-byte aligned to mitigate issues with host bus interconnects that |
| 216 | * restrict bus transfer lengths to be a multiple of 4-bytes */ |
| 217 | |
| 218 | /* set W1C value to clear the interrupt, this hits the register first */ |
| 219 | regBuffer[0] = error_int_status; |
| 220 | /* the remaining 4 values are set to zero which have no-effect */ |
| 221 | regBuffer[1] = 0; |
| 222 | regBuffer[2] = 0; |
| 223 | regBuffer[3] = 0; |
| 224 | |
| 225 | status = HIFReadWrite(pDev->HIFDevice, |
| 226 | ERROR_INT_STATUS_ADDRESS, |
| 227 | regBuffer, |
| 228 | 4, |
| 229 | HIF_WR_SYNC_BYTE_FIX, |
| 230 | NULL); |
| 231 | |
| 232 | AR_DEBUG_ASSERT(status == A_OK); |
| 233 | return status; |
| 234 | } |
| 235 | |
| 236 | static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev) |
| 237 | { |
| 238 | A_UINT32 dummy; |
| 239 | A_STATUS status; |
| 240 | |
| 241 | /* Send a target failure event to the application */ |
| 242 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n")); |
| 243 | |
| 244 | if (pDev->TargetFailureCallback != NULL) { |
| 245 | pDev->TargetFailureCallback(pDev->HTCContext); |
| 246 | } |
| 247 | |
| 248 | /* clear the interrupt , the debug error interrupt is |
| 249 | * counter 0 */ |
| 250 | /* read counter to clear interrupt */ |
| 251 | status = HIFReadWrite(pDev->HIFDevice, |
| 252 | COUNT_DEC_ADDRESS, |
| 253 | (A_UINT8 *)&dummy, |
| 254 | 4, |
| 255 | HIF_RD_SYNC_BYTE_INC, |
| 256 | NULL); |
| 257 | |
| 258 | AR_DEBUG_ASSERT(status == A_OK); |
| 259 | return status; |
| 260 | } |
| 261 | |
| 262 | static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev) |
| 263 | { |
| 264 | A_UINT8 counter_int_status; |
| 265 | |
| 266 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n")); |
| 267 | |
| 268 | counter_int_status = pDev->IrqProcRegisters.counter_int_status & |
| 269 | pDev->IrqEnableRegisters.counter_int_status_enable; |
| 270 | |
| 271 | AR_DEBUG_ASSERT(counter_int_status); |
| 272 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, |
| 273 | ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", |
| 274 | counter_int_status)); |
| 275 | |
| 276 | /* Check if the debug interrupt is pending */ |
| 277 | if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { |
| 278 | return DevServiceDebugInterrupt(pDev); |
| 279 | } |
| 280 | |
| 281 | return A_OK; |
| 282 | } |
| 283 | |
| 284 | /* callback when our fetch to get interrupt status registers completes */ |
| 285 | static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket) |
| 286 | { |
| 287 | AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; |
| 288 | A_UINT32 lookAhead = 0; |
| 289 | A_BOOL otherInts = FALSE; |
| 290 | |
| 291 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); |
| 292 | |
| 293 | do { |
| 294 | |
| 295 | if (A_FAILED(pPacket->Status)) { |
| 296 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR, |
| 297 | (" GetEvents I/O request failed, status:%d \n", pPacket->Status)); |
| 298 | /* bail out, don't unmask HIF interrupt */ |
| 299 | break; |
| 300 | } |
| 301 | |
| 302 | if (pDev->GetPendingEventsFunc != NULL) { |
| 303 | /* the HIF layer collected the information for us */ |
| 304 | HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer; |
| 305 | if (pEvents->Events & HIF_RECV_MSG_AVAIL) { |
| 306 | lookAhead = pEvents->LookAhead; |
| 307 | if (0 == lookAhead) { |
| 308 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n")); |
| 309 | } |
| 310 | } |
| 311 | if (pEvents->Events & HIF_OTHER_EVENTS) { |
| 312 | otherInts = TRUE; |
| 313 | } |
| 314 | } else { |
| 315 | /* standard interrupt table handling.... */ |
| 316 | AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer; |
| 317 | A_UINT8 host_int_status; |
| 318 | |
| 319 | host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable; |
| 320 | |
| 321 | if (host_int_status & (1 << HTC_MAILBOX)) { |
| 322 | host_int_status &= ~(1 << HTC_MAILBOX); |
| 323 | if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) { |
| 324 | /* mailbox has a message and the look ahead is valid */ |
| 325 | lookAhead = pReg->rx_lookahead[HTC_MAILBOX]; |
| 326 | if (0 == lookAhead) { |
| 327 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n")); |
| 328 | } |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | if (host_int_status) { |
| 333 | /* there are other interrupts to handle */ |
| 334 | otherInts = TRUE; |
| 335 | } |
| 336 | } |
| 337 | |
| 338 | if (otherInts || (lookAhead == 0)) { |
| 339 | /* if there are other interrupts to process, we cannot do this in the async handler so |
| 340 | * ack the interrupt which will cause our sync handler to run again |
| 341 | * if however there are no more messages, we can now ack the interrupt */ |
| 342 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, |
| 343 | (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n", |
| 344 | otherInts, lookAhead)); |
| 345 | HIFAckInterrupt(pDev->HIFDevice); |
| 346 | } else { |
| 347 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, |
| 348 | (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n", |
| 349 | lookAhead)); |
| 350 | /* lookahead is non-zero and there are no other interrupts to service, |
| 351 | * go get the next message */ |
| 352 | pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, NULL); |
| 353 | } |
| 354 | |
| 355 | } while (FALSE); |
| 356 | |
| 357 | /* free this IO packet */ |
| 358 | AR6KFreeIOPacket(pDev,pPacket); |
| 359 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n")); |
| 360 | } |
| 361 | |
| 362 | /* called by the HTC layer when it wants us to check if the device has any more pending |
| 363 | * recv messages, this starts off a series of async requests to read interrupt registers */ |
| 364 | A_STATUS DevCheckPendingRecvMsgsAsync(void *context) |
| 365 | { |
| 366 | AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; |
| 367 | A_STATUS status = A_OK; |
| 368 | HTC_PACKET *pIOPacket; |
| 369 | |
| 370 | /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can |
| 371 | * cause us to switch contexts */ |
| 372 | |
| 373 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev)); |
| 374 | |
| 375 | do { |
| 376 | |
| 377 | if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { |
| 378 | /* break the async processing chain right here, no need to continue. |
| 379 | * The DevDsrHandler() will handle things in a loop when things are driven |
| 380 | * synchronously */ |
| 381 | break; |
| 382 | } |
| 383 | /* first allocate one of our HTC packets we created for async I/O |
| 384 | * we reuse HTC packet definitions so that we can use the completion mechanism |
| 385 | * in DevRWCompletionHandler() */ |
| 386 | pIOPacket = AR6KAllocIOPacket(pDev); |
| 387 | |
| 388 | if (NULL == pIOPacket) { |
| 389 | /* there should be only 1 asynchronous request out at a time to read these registers |
| 390 | * so this should actually never happen */ |
| 391 | status = A_NO_MEMORY; |
| 392 | AR_DEBUG_ASSERT(FALSE); |
| 393 | break; |
| 394 | } |
| 395 | |
| 396 | /* stick in our completion routine when the I/O operation completes */ |
| 397 | pIOPacket->Completion = DevGetEventAsyncHandler; |
| 398 | pIOPacket->pContext = pDev; |
| 399 | |
| 400 | if (pDev->GetPendingEventsFunc) { |
| 401 | /* HIF layer has it's own mechanism, pass the IO to it.. */ |
| 402 | status = pDev->GetPendingEventsFunc(pDev->HIFDevice, |
| 403 | (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer, |
| 404 | pIOPacket); |
| 405 | |
| 406 | } else { |
| 407 | /* standard way, read the interrupt register table asynchronously again */ |
| 408 | status = HIFReadWrite(pDev->HIFDevice, |
| 409 | HOST_INT_STATUS_ADDRESS, |
| 410 | pIOPacket->pBuffer, |
| 411 | AR6K_IRQ_PROC_REGS_SIZE, |
| 412 | HIF_RD_ASYNC_BYTE_INC, |
| 413 | pIOPacket); |
| 414 | } |
| 415 | |
| 416 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n")); |
| 417 | } while (FALSE); |
| 418 | |
| 419 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n")); |
| 420 | |
| 421 | return status; |
| 422 | } |
| 423 | |
| 424 | /* process pending interrupts synchronously */ |
| 425 | static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing) |
| 426 | { |
| 427 | A_STATUS status = A_OK; |
| 428 | A_UINT8 host_int_status = 0; |
| 429 | A_UINT32 lookAhead = 0; |
| 430 | |
| 431 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev)); |
| 432 | |
| 433 | /*** NOTE: the HIF implementation guarantees that the context of this call allows |
| 434 | * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that |
| 435 | * can block or switch thread/task ontexts. |
| 436 | * This is a fully schedulable context. |
| 437 | * */ |
| 438 | do { |
| 439 | |
| 440 | if (pDev->GetPendingEventsFunc != NULL) { |
| 441 | HIF_PENDING_EVENTS_INFO events; |
| 442 | |
| 443 | /* the HIF layer uses a special mechanism to get events |
| 444 | * get this synchronously */ |
| 445 | status = pDev->GetPendingEventsFunc(pDev->HIFDevice, |
| 446 | &events, |
| 447 | NULL); |
| 448 | |
| 449 | if (A_FAILED(status)) { |
| 450 | break; |
| 451 | } |
| 452 | |
| 453 | if (events.Events & HIF_RECV_MSG_AVAIL) { |
| 454 | lookAhead = events.LookAhead; |
| 455 | if (0 == lookAhead) { |
| 456 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n")); |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | if (!(events.Events & HIF_OTHER_EVENTS) || |
| 461 | !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) { |
| 462 | /* no need to read the register table, no other interesting interrupts. |
| 463 | * Some interfaces (like SPI) can shadow interrupt sources without |
| 464 | * requiring the host to do a full table read */ |
| 465 | break; |
| 466 | } |
| 467 | |
| 468 | /* otherwise fall through and read the register table */ |
| 469 | } |
| 470 | |
| 471 | /* |
| 472 | * Read the first 28 bytes of the HTC register table. This will yield us |
| 473 | * the value of different int status registers and the lookahead |
| 474 | * registers. |
| 475 | * length = sizeof(int_status) + sizeof(cpu_int_status) + |
| 476 | * sizeof(error_int_status) + sizeof(counter_int_status) + |
| 477 | * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) + |
| 478 | * sizeof(hole) + sizeof(rx_lookahead) + |
| 479 | * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) + |
| 480 | * sizeof(error_status_enable) + |
| 481 | * sizeof(counter_int_status_enable); |
| 482 | * |
| 483 | */ |
| 484 | status = HIFReadWrite(pDev->HIFDevice, |
| 485 | HOST_INT_STATUS_ADDRESS, |
| 486 | (A_UINT8 *)&pDev->IrqProcRegisters, |
| 487 | AR6K_IRQ_PROC_REGS_SIZE, |
| 488 | HIF_RD_SYNC_BYTE_INC, |
| 489 | NULL); |
| 490 | |
| 491 | if (A_FAILED(status)) { |
| 492 | break; |
| 493 | } |
| 494 | |
| 495 | if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) { |
| 496 | DevDumpRegisters(&pDev->IrqProcRegisters, |
| 497 | &pDev->IrqEnableRegisters); |
| 498 | } |
| 499 | |
| 500 | /* Update only those registers that are enabled */ |
| 501 | host_int_status = pDev->IrqProcRegisters.host_int_status & |
| 502 | pDev->IrqEnableRegisters.int_status_enable; |
| 503 | |
| 504 | if (NULL == pDev->GetPendingEventsFunc) { |
| 505 | /* only look at mailbox status if the HIF layer did not provide this function, |
| 506 | * on some HIF interfaces reading the RX lookahead is not valid to do */ |
| 507 | if (host_int_status & (1 << HTC_MAILBOX)) { |
| 508 | /* mask out pending mailbox value, we use "lookAhead" as the real flag for |
| 509 | * mailbox processing below */ |
| 510 | host_int_status &= ~(1 << HTC_MAILBOX); |
| 511 | if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) { |
| 512 | /* mailbox has a message and the look ahead is valid */ |
| 513 | lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; |
| 514 | if (0 == lookAhead) { |
| 515 | AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n")); |
| 516 | } |
| 517 | } |
| 518 | } |
| 519 | } else { |
| 520 | /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/ |
| 521 | host_int_status &= ~(1 << HTC_MAILBOX); |
| 522 | } |
| 523 | |
| 524 | } while (FALSE); |
| 525 | |
| 526 | |
| 527 | do { |
| 528 | |
| 529 | /* did the interrupt status fetches succeed? */ |
| 530 | if (A_FAILED(status)) { |
| 531 | break; |
| 532 | } |
| 533 | |
| 534 | if ((0 == host_int_status) && (0 == lookAhead)) { |
| 535 | /* nothing to process, the caller can use this to break out of a loop */ |
| 536 | *pDone = TRUE; |
| 537 | break; |
| 538 | } |
| 539 | |
| 540 | if (lookAhead != 0) { |
| 541 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead)); |
| 542 | /* Mailbox Interrupt, the HTC layer may issue async requests to empty the |
| 543 | * mailbox... |
| 544 | * When emptying the recv mailbox we use the async handler above called from the |
| 545 | * completion routine of the callers read request. This can improve performance |
| 546 | * by reducing context switching when we rapidly pull packets */ |
| 547 | status = pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, pASyncProcessing); |
| 548 | if (A_FAILED(status)) { |
| 549 | break; |
| 550 | } |
| 551 | } |
| 552 | |
| 553 | /* now handle the rest of them */ |
| 554 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, |
| 555 | (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n", |
| 556 | host_int_status)); |
| 557 | |
| 558 | if (HOST_INT_STATUS_CPU_GET(host_int_status)) { |
| 559 | /* CPU Interrupt */ |
| 560 | status = DevServiceCPUInterrupt(pDev); |
| 561 | if (A_FAILED(status)){ |
| 562 | break; |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | if (HOST_INT_STATUS_ERROR_GET(host_int_status)) { |
| 567 | /* Error Interrupt */ |
| 568 | status = DevServiceErrorInterrupt(pDev); |
| 569 | if (A_FAILED(status)){ |
| 570 | break; |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) { |
| 575 | /* Counter Interrupt */ |
| 576 | status = DevServiceCounterInterrupt(pDev); |
| 577 | if (A_FAILED(status)){ |
| 578 | break; |
| 579 | } |
| 580 | } |
| 581 | |
| 582 | } while (FALSE); |
| 583 | |
| 584 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n", |
| 585 | *pDone, *pASyncProcessing, status)); |
| 586 | |
| 587 | return status; |
| 588 | } |
| 589 | |
| 590 | |
| 591 | /* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/ |
| 592 | A_STATUS DevDsrHandler(void *context) |
| 593 | { |
| 594 | AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; |
| 595 | A_STATUS status = A_OK; |
| 596 | A_BOOL done = FALSE; |
| 597 | A_BOOL asyncProc = FALSE; |
| 598 | |
| 599 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); |
| 600 | |
| 601 | |
| 602 | while (!done) { |
| 603 | status = ProcessPendingIRQs(pDev, &done, &asyncProc); |
| 604 | if (A_FAILED(status)) { |
| 605 | break; |
| 606 | } |
| 607 | |
| 608 | if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { |
| 609 | /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */ |
| 610 | asyncProc = FALSE; |
| 611 | /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers. |
| 612 | * this has a nice side effect of blocking us until all async read requests are completed. |
| 613 | * This behavior is required on some HIF implementations that do not allow ASYNC |
| 614 | * processing in interrupt handlers (like Windows CE) */ |
| 615 | } |
| 616 | |
| 617 | if (asyncProc) { |
| 618 | /* the function performed some async I/O for performance, we |
| 619 | need to exit the ISR immediately, the check below will prevent the interrupt from being |
| 620 | Ack'd while we handle it asynchronously */ |
| 621 | break; |
| 622 | } |
| 623 | |
| 624 | } |
| 625 | |
| 626 | if (A_SUCCESS(status) && !asyncProc) { |
| 627 | /* Ack the interrupt only if : |
| 628 | * 1. we did not get any errors in processing interrupts |
| 629 | * 2. there are no outstanding async processing requests */ |
| 630 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n")); |
| 631 | HIFAckInterrupt(pDev->HIFDevice); |
| 632 | } |
| 633 | |
| 634 | AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n")); |
| 635 | return A_OK; |
| 636 | } |
| 637 | |
| 638 | |
| 639 | |
