| 1 | /* |
| 2 | * HDQ generic GPIO bitbang driver using FIQ |
| 3 | * |
| 4 | * (C) 2006-2007 by Openmoko, Inc. |
| 5 | * Author: Andy Green <andy@openmoko.com> |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/hdq.h> |
| 19 | |
| 20 | #define HDQ_READ 0 |
| 21 | #define HDQ_WRITE 0x80 |
| 22 | |
| 23 | enum hdq_bitbang_states { |
| 24 | HDQB_IDLE = 0, |
| 25 | HDQB_TX_BREAK, |
| 26 | HDQB_TX_BREAK_RECOVERY, |
| 27 | HDQB_ADS_CALC, |
| 28 | HDQB_ADS_LOW, |
| 29 | HDQB_ADS_HIGH, |
| 30 | HDQB_WAIT_RX, |
| 31 | HDQB_DATA_RX_LOW, |
| 32 | HDQB_DATA_RX_HIGH, |
| 33 | HDQB_WAIT_TX, |
| 34 | }; |
| 35 | |
| 36 | static struct hdq_priv { |
| 37 | u8 hdq_probed; /* nonzero after HDQ driver probed */ |
| 38 | struct mutex hdq_lock; /* if you want to use hdq, you have to take lock */ |
| 39 | unsigned long hdq_gpio_pin; /* GTA02 = GPD14 which pin to meddle with */ |
| 40 | u8 hdq_ads; /* b7..b6 = register address, b0 = r/w */ |
| 41 | u8 hdq_tx_data; /* data to tx for write action */ |
| 42 | u8 hdq_rx_data; /* data received in read action */ |
| 43 | u8 hdq_request_ctr; /* incremented by "user" to request a transfer */ |
| 44 | u8 hdq_transaction_ctr; /* incremented after each transfer */ |
| 45 | u8 hdq_error; /* 0 = no error */ |
| 46 | u8 hdq_ctr; |
| 47 | u8 hdq_ctr2; |
| 48 | u8 hdq_bit; |
| 49 | u8 hdq_shifter; |
| 50 | u8 hdq_tx_data_done; |
| 51 | enum hdq_bitbang_states hdq_state; |
| 52 | int reported_error; |
| 53 | |
| 54 | struct hdq_platform_data *pdata; |
| 55 | } hdq_priv; |
| 56 | |
| 57 | |
| 58 | static void hdq_bad(void) |
| 59 | { |
| 60 | if (!hdq_priv.reported_error) |
| 61 | printk(KERN_ERR "HDQ error: %d\n", hdq_priv.hdq_error); |
| 62 | hdq_priv.reported_error = 1; |
| 63 | } |
| 64 | |
| 65 | static void hdq_good(void) |
| 66 | { |
| 67 | if (hdq_priv.reported_error) |
| 68 | printk(KERN_INFO "HDQ responds again\n"); |
| 69 | hdq_priv.reported_error = 0; |
| 70 | } |
| 71 | |
| 72 | int hdq_fiq_handler(void) |
| 73 | { |
| 74 | if (!hdq_priv.hdq_probed) |
| 75 | return 0; |
| 76 | |
| 77 | switch (hdq_priv.hdq_state) { |
| 78 | case HDQB_IDLE: |
| 79 | if (hdq_priv.hdq_request_ctr == hdq_priv.hdq_transaction_ctr) |
| 80 | break; |
| 81 | hdq_priv.hdq_ctr = 250 / HDQ_SAMPLE_PERIOD_US; |
| 82 | hdq_priv.pdata->gpio_set(0); |
| 83 | hdq_priv.pdata->gpio_dir_out(); |
| 84 | hdq_priv.hdq_tx_data_done = 0; |
| 85 | hdq_priv.hdq_state = HDQB_TX_BREAK; |
| 86 | break; |
| 87 | |
| 88 | case HDQB_TX_BREAK: /* issue low for > 190us */ |
| 89 | if (--hdq_priv.hdq_ctr == 0) { |
| 90 | hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US; |
| 91 | hdq_priv.hdq_state = HDQB_TX_BREAK_RECOVERY; |
| 92 | hdq_priv.pdata->gpio_set(1); |
| 93 | } |
| 94 | break; |
| 95 | |
| 96 | case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */ |
| 97 | if (--hdq_priv.hdq_ctr) |
| 98 | break; |
| 99 | hdq_priv.hdq_shifter = hdq_priv.hdq_ads; |
| 100 | hdq_priv.hdq_bit = 8; /* 8 bits of ads / rw */ |
| 101 | hdq_priv.hdq_tx_data_done = 0; /* doing ads */ |
| 102 | /* fallthru on last one */ |
| 103 | case HDQB_ADS_CALC: |
| 104 | if (hdq_priv.hdq_shifter & 1) |
| 105 | hdq_priv.hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US; |
| 106 | else |
| 107 | hdq_priv.hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US; |
| 108 | /* carefully precompute the other phase length */ |
| 109 | hdq_priv.hdq_ctr2 = (210 - (hdq_priv.hdq_ctr * HDQ_SAMPLE_PERIOD_US)) / |
| 110 | HDQ_SAMPLE_PERIOD_US; |
| 111 | hdq_priv.hdq_state = HDQB_ADS_LOW; |
| 112 | hdq_priv.hdq_shifter >>= 1; |
| 113 | hdq_priv.hdq_bit--; |
| 114 | hdq_priv.pdata->gpio_set(0); |
| 115 | break; |
| 116 | |
| 117 | case HDQB_ADS_LOW: |
| 118 | if (--hdq_priv.hdq_ctr) |
| 119 | break; |
| 120 | hdq_priv.pdata->gpio_set(1); |
| 121 | hdq_priv.hdq_state = HDQB_ADS_HIGH; |
| 122 | break; |
| 123 | |
| 124 | case HDQB_ADS_HIGH: |
| 125 | if (--hdq_priv.hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */ |
| 126 | break; |
| 127 | if (hdq_priv.hdq_bit) { /* more bits to do */ |
| 128 | hdq_priv.hdq_state = HDQB_ADS_CALC; |
| 129 | break; |
| 130 | } |
| 131 | /* no more bits, wait it out until hdq_priv.hdq_ctr2 exhausted */ |
| 132 | if (hdq_priv.hdq_ctr2) |
| 133 | break; |
| 134 | /* ok no more bits and very last state */ |
| 135 | hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US; |
| 136 | /* FIXME 0 = read */ |
| 137 | if (hdq_priv.hdq_ads & 0x80) { /* write the byte out */ |
| 138 | /* set delay before payload */ |
| 139 | hdq_priv.hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US; |
| 140 | /* already high, no need to write */ |
| 141 | hdq_priv.hdq_state = HDQB_WAIT_TX; |
| 142 | break; |
| 143 | } |
| 144 | /* read the next byte */ |
| 145 | hdq_priv.hdq_bit = 8; /* 8 bits of data */ |
| 146 | hdq_priv.hdq_ctr = 2500 / HDQ_SAMPLE_PERIOD_US; |
| 147 | hdq_priv.hdq_state = HDQB_WAIT_RX; |
| 148 | hdq_priv.pdata->gpio_dir_in(); |
| 149 | break; |
| 150 | |
| 151 | case HDQB_WAIT_TX: /* issue low for > 40us */ |
| 152 | if (--hdq_priv.hdq_ctr) |
| 153 | break; |
| 154 | if (!hdq_priv.hdq_tx_data_done) { /* was that the data sent? */ |
| 155 | hdq_priv.hdq_tx_data_done++; |
| 156 | hdq_priv.hdq_shifter = hdq_priv.hdq_tx_data; |
| 157 | hdq_priv.hdq_bit = 8; /* 8 bits of data */ |
| 158 | hdq_priv.hdq_state = HDQB_ADS_CALC; /* start sending */ |
| 159 | break; |
| 160 | } |
| 161 | hdq_priv.hdq_error = 0; |
| 162 | hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr; |
| 163 | hdq_priv.hdq_state = HDQB_IDLE; /* all tx is done */ |
| 164 | /* idle in input mode, it's pulled up by 10K */ |
| 165 | hdq_priv.pdata->gpio_dir_in(); |
| 166 | break; |
| 167 | |
| 168 | case HDQB_WAIT_RX: /* wait for battery to talk to us */ |
| 169 | if (hdq_priv.pdata->gpio_get() == 0) { |
| 170 | /* it talks to us! */ |
| 171 | hdq_priv.hdq_ctr2 = 1; |
| 172 | hdq_priv.hdq_bit = 8; /* 8 bits of data */ |
| 173 | /* timeout */ |
| 174 | hdq_priv.hdq_ctr = 500 / HDQ_SAMPLE_PERIOD_US; |
| 175 | hdq_priv.hdq_state = HDQB_DATA_RX_LOW; |
| 176 | break; |
| 177 | } |
| 178 | if (--hdq_priv.hdq_ctr == 0) { /* timed out, error */ |
| 179 | hdq_priv.hdq_error = 1; |
| 180 | hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr; |
| 181 | hdq_priv.hdq_state = HDQB_IDLE; /* abort */ |
| 182 | } |
| 183 | break; |
| 184 | |
| 185 | /* |
| 186 | * HDQ basically works by measuring the low time of the bit cell |
| 187 | * 32-50us --> '1', 80 - 145us --> '0' |
| 188 | */ |
| 189 | |
| 190 | case HDQB_DATA_RX_LOW: |
| 191 | if (hdq_priv.pdata->gpio_get()) { |
| 192 | hdq_priv.hdq_rx_data >>= 1; |
| 193 | if (hdq_priv.hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US)) |
| 194 | hdq_priv.hdq_rx_data |= 0x80; |
| 195 | |
| 196 | if (--hdq_priv.hdq_bit == 0) { |
| 197 | hdq_priv.hdq_error = 0; |
| 198 | hdq_priv.hdq_transaction_ctr = |
| 199 | hdq_priv.hdq_request_ctr; |
| 200 | |
| 201 | hdq_priv.hdq_state = HDQB_IDLE; |
| 202 | } else |
| 203 | hdq_priv.hdq_state = HDQB_DATA_RX_HIGH; |
| 204 | /* timeout */ |
| 205 | hdq_priv.hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US; |
| 206 | hdq_priv.hdq_ctr2 = 1; |
| 207 | break; |
| 208 | } |
| 209 | hdq_priv.hdq_ctr2++; |
| 210 | if (--hdq_priv.hdq_ctr) |
| 211 | break; |
| 212 | /* timed out, error */ |
| 213 | hdq_priv.hdq_error = 2; |
| 214 | hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr; |
| 215 | hdq_priv.hdq_state = HDQB_IDLE; /* abort */ |
| 216 | break; |
| 217 | |
| 218 | case HDQB_DATA_RX_HIGH: |
| 219 | if (!hdq_priv.pdata->gpio_get()) { |
| 220 | /* it talks to us! */ |
| 221 | hdq_priv.hdq_ctr2 = 1; |
| 222 | /* timeout */ |
| 223 | hdq_priv.hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US; |
| 224 | hdq_priv.hdq_state = HDQB_DATA_RX_LOW; |
| 225 | break; |
| 226 | } |
| 227 | if (--hdq_priv.hdq_ctr) |
| 228 | break; |
| 229 | /* timed out, error */ |
| 230 | hdq_priv.hdq_error = 3; |
| 231 | hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr; |
| 232 | |
| 233 | /* we're in input mode already */ |
| 234 | hdq_priv.hdq_state = HDQB_IDLE; /* abort */ |
| 235 | break; |
| 236 | } |
| 237 | |
| 238 | /* Are we interested in keeping the FIQ source alive ? */ |
| 239 | if (hdq_priv.hdq_state != HDQB_IDLE) |
| 240 | return 1; |
| 241 | else |
| 242 | return 0; |
| 243 | } |
| 244 | static int fiq_busy(void) |
| 245 | { |
| 246 | int request = (volatile u8)hdq_priv.hdq_request_ctr; |
| 247 | int transact = (volatile u8)hdq_priv.hdq_transaction_ctr; |
| 248 | |
| 249 | |
| 250 | return (request != transact); |
| 251 | } |
| 252 | |
| 253 | int hdq_initialized(void) |
| 254 | { |
| 255 | return hdq_priv.hdq_probed; |
| 256 | } |
| 257 | EXPORT_SYMBOL_GPL(hdq_initialized); |
| 258 | |
| 259 | int hdq_read(int address) |
| 260 | { |
| 261 | int count_sleeps = 5; |
| 262 | int ret = -ETIME; |
| 263 | |
| 264 | if (!hdq_priv.hdq_probed) |
| 265 | return -EINVAL; |
| 266 | |
| 267 | mutex_lock(&hdq_priv.hdq_lock); |
| 268 | |
| 269 | hdq_priv.hdq_error = 0; |
| 270 | hdq_priv.hdq_ads = address | HDQ_READ; |
| 271 | hdq_priv.hdq_request_ctr++; |
| 272 | hdq_priv.pdata->kick_fiq(); |
| 273 | /* |
| 274 | * FIQ takes care of it while we block our calling process |
| 275 | * But we're not spinning -- other processes run normally while |
| 276 | * we wait for the result |
| 277 | */ |
| 278 | while (count_sleeps--) { |
| 279 | msleep(10); /* valid transaction always completes in < 10ms */ |
| 280 | |
| 281 | if (fiq_busy()) |
| 282 | continue; |
| 283 | |
| 284 | if (hdq_priv.hdq_error) { |
| 285 | hdq_bad(); |
| 286 | goto done; /* didn't see a response in good time */ |
| 287 | } |
| 288 | hdq_good(); |
| 289 | |
| 290 | ret = hdq_priv.hdq_rx_data; |
| 291 | goto done; |
| 292 | } |
| 293 | |
| 294 | done: |
| 295 | mutex_unlock(&hdq_priv.hdq_lock); |
| 296 | return ret; |
| 297 | } |
| 298 | EXPORT_SYMBOL_GPL(hdq_read); |
| 299 | |
| 300 | int hdq_write(int address, u8 data) |
| 301 | { |
| 302 | int count_sleeps = 5; |
| 303 | int ret = -ETIME; |
| 304 | |
| 305 | if (!hdq_priv.hdq_probed) |
| 306 | return -EINVAL; |
| 307 | |
| 308 | mutex_lock(&hdq_priv.hdq_lock); |
| 309 | |
| 310 | hdq_priv.hdq_error = 0; |
| 311 | hdq_priv.hdq_ads = address | HDQ_WRITE; |
| 312 | hdq_priv.hdq_tx_data = data; |
| 313 | hdq_priv.hdq_request_ctr++; |
| 314 | hdq_priv.pdata->kick_fiq(); |
| 315 | /* |
| 316 | * FIQ takes care of it while we block our calling process |
| 317 | * But we're not spinning -- other processes run normally while |
| 318 | * we wait for the result |
| 319 | */ |
| 320 | while (count_sleeps--) { |
| 321 | msleep(10); /* valid transaction always completes in < 10ms */ |
| 322 | |
| 323 | if (fiq_busy()) |
| 324 | continue; /* something bad with FIQ */ |
| 325 | |
| 326 | if (hdq_priv.hdq_error) { |
| 327 | hdq_bad(); |
| 328 | goto done; /* didn't see a response in good time */ |
| 329 | } |
| 330 | hdq_good(); |
| 331 | |
| 332 | ret = 0; |
| 333 | goto done; |
| 334 | } |
| 335 | |
| 336 | done: |
| 337 | mutex_unlock(&hdq_priv.hdq_lock); |
| 338 | return ret; |
| 339 | } |
| 340 | EXPORT_SYMBOL_GPL(hdq_write); |
| 341 | |
| 342 | /* sysfs */ |
| 343 | |
| 344 | static ssize_t hdq_sysfs_dump(struct device *dev, struct device_attribute *attr, |
| 345 | char *buf) |
| 346 | { |
| 347 | int n; |
| 348 | int v; |
| 349 | u8 u8a[128]; /* whole address space for HDQ */ |
| 350 | char *end = buf; |
| 351 | |
| 352 | if (!hdq_priv.hdq_probed) |
| 353 | return -EINVAL; |
| 354 | |
| 355 | /* the dump does not take care about 16 bit regs, because at this |
| 356 | * bus level we don't know about the chip details |
| 357 | */ |
| 358 | for (n = 0; n < sizeof(u8a); n++) { |
| 359 | v = hdq_read(n); |
| 360 | if (v < 0) |
| 361 | goto bail; |
| 362 | u8a[n] = v; |
| 363 | } |
| 364 | |
| 365 | for (n = 0; n < sizeof(u8a); n += 16) { |
| 366 | hex_dump_to_buffer(u8a + n, sizeof(u8a), 16, 1, end, 4096, 0); |
| 367 | end += strlen(end); |
| 368 | *end++ = '\n'; |
| 369 | *end = '\0'; |
| 370 | } |
| 371 | return (end - buf); |
| 372 | |
| 373 | bail: |
| 374 | return sprintf(buf, "ERROR %d\n", v); |
| 375 | } |
| 376 | |
| 377 | /* you write by <address> <data>, eg, "34 128" */ |
| 378 | |
| 379 | #define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0) |
| 380 | |
| 381 | static ssize_t hdq_sysfs_write(struct device *dev, |
| 382 | struct device_attribute *attr, |
| 383 | const char *buf, size_t count) |
| 384 | { |
| 385 | const char *end = buf + count; |
| 386 | int address = atoi(buf); |
| 387 | |
| 388 | if (!hdq_priv.hdq_probed) |
| 389 | return -EINVAL; |
| 390 | |
| 391 | while ((buf != end) && (*buf != ' ')) |
| 392 | buf++; |
| 393 | if (buf >= end) |
| 394 | return 0; |
| 395 | while ((buf < end) && (*buf == ' ')) |
| 396 | buf++; |
| 397 | if (buf >= end) |
| 398 | return 0; |
| 399 | |
| 400 | hdq_write(address, atoi(buf)); |
| 401 | |
| 402 | return count; |
| 403 | } |
| 404 | |
| 405 | static DEVICE_ATTR(dump, 0400, hdq_sysfs_dump, NULL); |
| 406 | static DEVICE_ATTR(write, 0600, NULL, hdq_sysfs_write); |
| 407 | |
| 408 | static struct attribute *hdq_sysfs_entries[] = { |
| 409 | &dev_attr_dump.attr, |
| 410 | &dev_attr_write.attr, |
| 411 | NULL |
| 412 | }; |
| 413 | |
| 414 | static struct attribute_group hdq_attr_group = { |
| 415 | .name = "hdq", |
| 416 | .attrs = hdq_sysfs_entries, |
| 417 | }; |
| 418 | |
| 419 | |
| 420 | #ifdef CONFIG_PM |
| 421 | static int hdq_suspend(struct platform_device *pdev, pm_message_t state) |
| 422 | { |
| 423 | /* after 18s of this, the battery monitor will also go to sleep */ |
| 424 | hdq_priv.pdata->gpio_dir_in(); |
| 425 | hdq_priv.pdata->disable_fiq(); |
| 426 | return 0; |
| 427 | } |
| 428 | |
| 429 | static int hdq_resume(struct platform_device *pdev) |
| 430 | { |
| 431 | hdq_priv.pdata->gpio_set(1); |
| 432 | hdq_priv.pdata->gpio_dir_out(); |
| 433 | hdq_priv.pdata->enable_fiq(); |
| 434 | return 0; |
| 435 | } |
| 436 | #endif |
| 437 | |
| 438 | static int __init hdq_probe(struct platform_device *pdev) |
| 439 | { |
| 440 | struct resource *r = platform_get_resource(pdev, 0, 0); |
| 441 | int ret; |
| 442 | struct hdq_platform_data *pdata = pdev->dev.platform_data; |
| 443 | |
| 444 | if (!r || !pdata) |
| 445 | return -EINVAL; |
| 446 | |
| 447 | platform_set_drvdata(pdev, NULL); |
| 448 | |
| 449 | mutex_init(&hdq_priv.hdq_lock); |
| 450 | |
| 451 | /* set our HDQ comms pin from the platform data */ |
| 452 | hdq_priv.hdq_gpio_pin = r->start; |
| 453 | hdq_priv.pdata = pdata; |
| 454 | |
| 455 | hdq_priv.pdata->gpio_set(1); |
| 456 | hdq_priv.pdata->gpio_dir_out(); |
| 457 | |
| 458 | /* Initialize FIQ */ |
| 459 | if (hdq_priv.pdata->enable_fiq() < 0) { |
| 460 | dev_err(&pdev->dev, "Could not enable FIQ source\n"); |
| 461 | return -EINVAL; |
| 462 | } |
| 463 | |
| 464 | ret = sysfs_create_group(&pdev->dev.kobj, &hdq_attr_group); |
| 465 | if (ret) |
| 466 | return ret; |
| 467 | |
| 468 | hdq_priv.hdq_probed = 1; /* we are ready to do stuff now */ |
| 469 | |
| 470 | /* |
| 471 | * if wanted, users can defer registration of devices |
| 472 | * that depend on HDQ until after we register, and can use our |
| 473 | * device as parent so suspend-resume ordering is correct |
| 474 | */ |
| 475 | if (pdata->attach_child_devices) |
| 476 | (pdata->attach_child_devices)(&pdev->dev); |
| 477 | |
| 478 | hdq_priv.pdata = pdata; |
| 479 | |
| 480 | return 0; |
| 481 | } |
| 482 | |
| 483 | static int hdq_remove(struct platform_device *pdev) |
| 484 | { |
| 485 | sysfs_remove_group(&pdev->dev.kobj, &hdq_attr_group); |
| 486 | return 0; |
| 487 | } |
| 488 | |
| 489 | static struct platform_driver hdq_driver = { |
| 490 | .probe = hdq_probe, |
| 491 | .remove = hdq_remove, |
| 492 | #ifdef CONFIG_PM |
| 493 | .suspend = hdq_suspend, |
| 494 | .resume = hdq_resume, |
| 495 | #endif |
| 496 | .driver = { |
| 497 | .name = "hdq", |
| 498 | }, |
| 499 | }; |
| 500 | |
| 501 | static int __init hdq_init(void) |
| 502 | { |
| 503 | return platform_driver_register(&hdq_driver); |
| 504 | } |
| 505 | |
| 506 | static void __exit hdq_exit(void) |
| 507 | { |
| 508 | platform_driver_unregister(&hdq_driver); |
| 509 | } |
| 510 | |
| 511 | module_init(hdq_init); |
| 512 | module_exit(hdq_exit); |
| 513 | |
| 514 | MODULE_AUTHOR("Andy Green <andy@openmoko.com>"); |
| 515 | MODULE_DESCRIPTION("HDQ driver"); |
| 516 | |
