| 1 | --- /dev/null |
| 2 | +++ b/arch/arm/plat-s3c/dev-usb.c |
| 3 | @@ -0,0 +1,50 @@ |
| 4 | +/* linux/arch/arm/plat-s3c/dev-usb.c |
| 5 | + * |
| 6 | + * Copyright 2008 Simtec Electronics |
| 7 | + * Ben Dooks <ben@simtec.co.uk> |
| 8 | + * http://armlinux.simtec.co.uk/ |
| 9 | + * |
| 10 | + * S3C series device definition for USB host |
| 11 | + * |
| 12 | + * This program is free software; you can redistribute it and/or modify |
| 13 | + * it under the terms of the GNU General Public License version 2 as |
| 14 | + * published by the Free Software Foundation. |
| 15 | +*/ |
| 16 | + |
| 17 | +#include <linux/kernel.h> |
| 18 | +#include <linux/string.h> |
| 19 | +#include <linux/platform_device.h> |
| 20 | + |
| 21 | +#include <mach/irqs.h> |
| 22 | +#include <mach/map.h> |
| 23 | + |
| 24 | +#include <plat/devs.h> |
| 25 | + |
| 26 | + |
| 27 | +static struct resource s3c_usb_resource[] = { |
| 28 | + [0] = { |
| 29 | + .start = S3C24XX_PA_USBHOST, |
| 30 | + .end = S3C24XX_PA_USBHOST + 0x100 - 1, |
| 31 | + .flags = IORESOURCE_MEM, |
| 32 | + }, |
| 33 | + [1] = { |
| 34 | + .start = IRQ_USBH, |
| 35 | + .end = IRQ_USBH, |
| 36 | + .flags = IORESOURCE_IRQ, |
| 37 | + } |
| 38 | +}; |
| 39 | + |
| 40 | +static u64 s3c_device_usb_dmamask = 0xffffffffUL; |
| 41 | + |
| 42 | +struct platform_device s3c_device_usb = { |
| 43 | + .name = "s3c-ohci", |
| 44 | + .id = -1, |
| 45 | + .num_resources = ARRAY_SIZE(s3c_usb_resource), |
| 46 | + .resource = s3c_usb_resource, |
| 47 | + .dev = { |
| 48 | + .dma_mask = &s3c_device_usb_dmamask, |
| 49 | + .coherent_dma_mask = 0xffffffffUL |
| 50 | + } |
| 51 | +}; |
| 52 | + |
| 53 | +EXPORT_SYMBOL(s3c_device_usb); |
| 54 | --- /dev/null |
| 55 | +++ b/arch/arm/plat-s3c/include/plat/regs-usb-hs-otg.h |
| 56 | @@ -0,0 +1,360 @@ |
| 57 | +/* linux/include/asm-arm/arch-s3c2410/regs-udc.h |
| 58 | + * |
| 59 | + * Copyright (C) 2008 Samsung Electronics |
| 60 | + * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> |
| 61 | + * |
| 62 | + * This include file is free software; you can redistribute it and/or |
| 63 | + * modify it under the terms of the GNU General Public License as |
| 64 | + * published by the Free Software Foundation; either version 2 of |
| 65 | + * the License, or (at your option) any later version. |
| 66 | +*/ |
| 67 | + |
| 68 | +#ifndef __ASM_ARCH_REGS_USB_HS_OTG_H |
| 69 | +#define __ASM_ARCH_REGS_USB_HS_OTG_H |
| 70 | + |
| 71 | +/* USB2.0 OTG Controller register */ |
| 72 | +#define S3C_USBOTG_PHYREG(x) ((x) + 0x100000 /* S3C64XX_VA_OTGSFR */) |
| 73 | +#define S3C_USBOTG_PHYPWR S3C_USBOTG_PHYREG(0x0) |
| 74 | +#define S3C_USBOTG_PHYCLK S3C_USBOTG_PHYREG(0x4) |
| 75 | +#define S3C_USBOTG_RSTCON S3C_USBOTG_PHYREG(0x8) |
| 76 | + |
| 77 | +/* USB2.0 OTG Controller register */ |
| 78 | +/* Core Global Registers */ |
| 79 | +#define S3C_USBOTGREG(x) ((x) /*+ S3C64XX_VA_OTG */) |
| 80 | +/* OTG Control & Status */ |
| 81 | +#define S3C_UDC_OTG_GOTGCTL S3C_USBOTGREG(0x000) |
| 82 | +/* OTG Interrupt */ |
| 83 | +#define S3C_UDC_OTG_GOTGINT S3C_USBOTGREG(0x004) |
| 84 | +/* Core AHB Configuration */ |
| 85 | +#define S3C_UDC_OTG_GAHBCFG S3C_USBOTGREG(0x008) |
| 86 | +/* Core USB Configuration */ |
| 87 | +#define S3C_UDC_OTG_GUSBCFG S3C_USBOTGREG(0x00C) |
| 88 | +/* Core Reset */ |
| 89 | +#define S3C_UDC_OTG_GRSTCTL S3C_USBOTGREG(0x010) |
| 90 | +/* Core Interrupt */ |
| 91 | +#define S3C_UDC_OTG_GINTSTS S3C_USBOTGREG(0x014) |
| 92 | +/* Core Interrupt Mask */ |
| 93 | +#define S3C_UDC_OTG_GINTMSK S3C_USBOTGREG(0x018) |
| 94 | +/* Receive Status Debug Read/Status Read */ |
| 95 | +#define S3C_UDC_OTG_GRXSTSR S3C_USBOTGREG(0x01C) |
| 96 | +/* Receive Status Debug Pop/Status Pop */ |
| 97 | +#define S3C_UDC_OTG_GRXSTSP S3C_USBOTGREG(0x020) |
| 98 | +/* Receive FIFO Size */ |
| 99 | +#define S3C_UDC_OTG_GRXFSIZ S3C_USBOTGREG(0x024) |
| 100 | +/* Non-Periodic Transmit FIFO Size */ |
| 101 | +#define S3C_UDC_OTG_GNPTXFSIZ S3C_USBOTGREG(0x028) |
| 102 | +/* Non-Periodic Transmit FIFO/Queue Status */ |
| 103 | +#define S3C_UDC_OTG_GNPTXSTS S3C_USBOTGREG(0x02C) |
| 104 | + |
| 105 | +/* Host Periodic Transmit FIFO Size */ |
| 106 | +#define S3C_UDC_OTG_HPTXFSIZ S3C_USBOTGREG(0x100) |
| 107 | +/* Device Periodic Transmit FIFO-1 Size */ |
| 108 | +#define S3C_UDC_OTG_DPTXFSIZ1 S3C_USBOTGREG(0x104) |
| 109 | +/* Device Periodic Transmit FIFO-2 Size */ |
| 110 | +#define S3C_UDC_OTG_DPTXFSIZ2 S3C_USBOTGREG(0x108) |
| 111 | +/* Device Periodic Transmit FIFO-3 Size */ |
| 112 | +#define S3C_UDC_OTG_DPTXFSIZ3 S3C_USBOTGREG(0x10C) |
| 113 | +/* Device Periodic Transmit FIFO-4 Size */ |
| 114 | +#define S3C_UDC_OTG_DPTXFSIZ4 S3C_USBOTGREG(0x110) |
| 115 | +/* Device Periodic Transmit FIFO-5 Size */ |
| 116 | +#define S3C_UDC_OTG_DPTXFSIZ5 S3C_USBOTGREG(0x114) |
| 117 | +/* Device Periodic Transmit FIFO-6 Size */ |
| 118 | +#define S3C_UDC_OTG_DPTXFSIZ6 S3C_USBOTGREG(0x118) |
| 119 | +/* Device Periodic Transmit FIFO-7 Size */ |
| 120 | +#define S3C_UDC_OTG_DPTXFSIZ7 S3C_USBOTGREG(0x11C) |
| 121 | +/* Device Periodic Transmit FIFO-8 Size */ |
| 122 | +#define S3C_UDC_OTG_DPTXFSIZ8 S3C_USBOTGREG(0x120) |
| 123 | +/* Device Periodic Transmit FIFO-9 Size */ |
| 124 | +#define S3C_UDC_OTG_DPTXFSIZ9 S3C_USBOTGREG(0x124) |
| 125 | +/* Device Periodic Transmit FIFO-10 Size */ |
| 126 | +#define S3C_UDC_OTG_DPTXFSIZ10 S3C_USBOTGREG(0x128) |
| 127 | +/* Device Periodic Transmit FIFO-11 Size */ |
| 128 | +#define S3C_UDC_OTG_DPTXFSIZ11 S3C_USBOTGREG(0x12C) |
| 129 | +/* Device Periodic Transmit FIFO-12 Size */ |
| 130 | +#define S3C_UDC_OTG_DPTXFSIZ12 S3C_USBOTGREG(0x130) |
| 131 | +/* Device Periodic Transmit FIFO-13 Size */ |
| 132 | +#define S3C_UDC_OTG_DPTXFSIZ13 S3C_USBOTGREG(0x134) |
| 133 | +/* Device Periodic Transmit FIFO-14 Size */ |
| 134 | +#define S3C_UDC_OTG_DPTXFSIZ14 S3C_USBOTGREG(0x138) |
| 135 | +/* Device Periodic Transmit FIFO-15 Size */ |
| 136 | +#define S3C_UDC_OTG_DPTXFSIZ15 S3C_USBOTGREG(0x13C) |
| 137 | + |
| 138 | +/* Host Mode Registers |
| 139 | + * Host Global Registers */ |
| 140 | +/* Host Configuration */ |
| 141 | +#define S3C_UDC_OTG_HCFG S3C_USBOTGREG(0x400) |
| 142 | +/* Host Frame Interval */ |
| 143 | +#define S3C_UDC_OTG_HFIR S3C_USBOTGREG(0x404) |
| 144 | +/* Host Frame Number/Frame Time Remaining */ |
| 145 | +#define S3C_UDC_OTG_HFNUM S3C_USBOTGREG(0x408) |
| 146 | +/* Host Periodic Transmit FIFO/Queue Status */ |
| 147 | +#define S3C_UDC_OTG_HPTXSTS S3C_USBOTGREG(0x410) |
| 148 | +/* Host All Channels Interrupt */ |
| 149 | +#define S3C_UDC_OTG_HAINT S3C_USBOTGREG(0x414) |
| 150 | +/* Host All Channels Interrupt Mask */ |
| 151 | +#define S3C_UDC_OTG_HAINTMSK S3C_USBOTGREG(0x418) |
| 152 | + |
| 153 | +/* Host Port Control & Status Registers */ |
| 154 | +#define S3C_UDC_OTG_HPRT S3C_USBOTGREG(0x440) |
| 155 | + |
| 156 | +/* Host Channel-Specific Registers */ |
| 157 | +/* Host Channel-0 Characteristics */ |
| 158 | +#define S3C_UDC_OTG_HCCHAR0 S3C_USBOTGREG(0x500) |
| 159 | +/* Host Channel-0 Split Control */ |
| 160 | +#define S3C_UDC_OTG_HCSPLT0 S3C_USBOTGREG(0x504) |
| 161 | +/* Host Channel-0 Interrupt */ |
| 162 | +#define S3C_UDC_OTG_HCINT0 S3C_USBOTGREG(0x508) |
| 163 | +/* Host Channel-0 Interrupt Mask */ |
| 164 | +#define S3C_UDC_OTG_HCINTMSK0 S3C_USBOTGREG(0x50C) |
| 165 | +/* Host Channel-0 Transfer Size */ |
| 166 | +#define S3C_UDC_OTG_HCTSIZ0 S3C_USBOTGREG(0x510) |
| 167 | +/* Host Channel-0 DMA Address */ |
| 168 | +#define S3C_UDC_OTG_HCDMA0 S3C_USBOTGREG(0x514) |
| 169 | + |
| 170 | +/* Device Mode Registers |
| 171 | + * Device Global Registers */ |
| 172 | +/* Device Configuration */ |
| 173 | +#define S3C_UDC_OTG_DCFG S3C_USBOTGREG(0x800) |
| 174 | +/* Device Control */ |
| 175 | +#define S3C_UDC_OTG_DCTL S3C_USBOTGREG(0x804) |
| 176 | +/* Device Status */ |
| 177 | +#define S3C_UDC_OTG_DSTS S3C_USBOTGREG(0x808) |
| 178 | +/* Device IN Endpoint Common Interrupt Mask */ |
| 179 | +#define S3C_UDC_OTG_DIEPMSK S3C_USBOTGREG(0x810) |
| 180 | +/* Device OUT Endpoint Common Interrupt Mask */ |
| 181 | +#define S3C_UDC_OTG_DOEPMSK S3C_USBOTGREG(0x814) |
| 182 | +/* Device All Endpoints Interrupt */ |
| 183 | +#define S3C_UDC_OTG_DAINT S3C_USBOTGREG(0x818) |
| 184 | +/* Device All Endpoints Interrupt Mask */ |
| 185 | +#define S3C_UDC_OTG_DAINTMSK S3C_USBOTGREG(0x81C) |
| 186 | +/* Device IN Token Sequence Learning Queue Read 1 */ |
| 187 | +#define S3C_UDC_OTG_DTKNQR1 S3C_USBOTGREG(0x820) |
| 188 | +/* Device IN Token Sequence Learning Queue Read 2 */ |
| 189 | +#define S3C_UDC_OTG_DTKNQR2 S3C_USBOTGREG(0x824) |
| 190 | +/* Device VBUS Discharge Time */ |
| 191 | +#define S3C_UDC_OTG_DVBUSDIS S3C_USBOTGREG(0x828) |
| 192 | +/* Device VBUS Pulsing Time */ |
| 193 | +#define S3C_UDC_OTG_DVBUSPULSE S3C_USBOTGREG(0x82C) |
| 194 | +/* Device IN Token Sequence Learning Queue Read 3 */ |
| 195 | +#define S3C_UDC_OTG_DTKNQR3 S3C_USBOTGREG(0x830) |
| 196 | +/* Device IN Token Sequence Learning Queue Read 4 */ |
| 197 | +#define S3C_UDC_OTG_DTKNQR4 S3C_USBOTGREG(0x834) |
| 198 | + |
| 199 | +/* Device Logical IN Endpoint-Specific Registers */ |
| 200 | +/* Device IN Endpoint 0 Control */ |
| 201 | +#define S3C_UDC_OTG_DIEPCTL0 S3C_USBOTGREG(0x900) |
| 202 | +/* Device IN Endpoint 0 Interrupt */ |
| 203 | +#define S3C_UDC_OTG_DIEPINT0 S3C_USBOTGREG(0x908) |
| 204 | +/* Device IN Endpoint 0 Transfer Size */ |
| 205 | +#define S3C_UDC_OTG_DIEPTSIZ0 S3C_USBOTGREG(0x910) |
| 206 | +/* Device IN Endpoint 0 DMA Address */ |
| 207 | +#define S3C_UDC_OTG_DIEPDMA0 S3C_USBOTGREG(0x914) |
| 208 | + |
| 209 | +/* Device IN Endpoint 2 Control */ |
| 210 | +#define S3C_UDC_OTG_DIEPCTL2 S3C_USBOTGREG(0x940) |
| 211 | +/* Device IN Endpoint 2 Interrupt */ |
| 212 | +#define S3C_UDC_OTG_DIEPINT2 S3C_USBOTGREG(0x948) |
| 213 | +/* Device IN Endpoint 2 Transfer Size */ |
| 214 | +#define S3C_UDC_OTG_DIEPTSIZ2 S3C_USBOTGREG(0x950) |
| 215 | +/* Device IN Endpoint 2 DMA Address */ |
| 216 | +#define S3C_UDC_OTG_DIEPDMA2 S3C_USBOTGREG(0x954) |
| 217 | + |
| 218 | +/* Device IN Endpoint 3 Control */ |
| 219 | +#define S3C_UDC_OTG_DIEPCTL3 S3C_USBOTGREG(0x960) |
| 220 | +/* Device IN Endpoint 3 Interrupt */ |
| 221 | +#define S3C_UDC_OTG_DIEPINT3 S3C_USBOTGREG(0x968) |
| 222 | +/* Device IN Endpoint 3 Transfer Size */ |
| 223 | +#define S3C_UDC_OTG_DIEPTSIZ3 S3C_USBOTGREG(0x970) |
| 224 | +/* Device IN Endpoint 3 DMA Address */ |
| 225 | +#define S3C_UDC_OTG_DIEPDMA3 S3C_USBOTGREG(0x974) |
| 226 | + |
| 227 | +/* Device Logical OUT Endpoint-Specific Registers */ |
| 228 | +/* Device OUT Endpoint 0 Control */ |
| 229 | +#define S3C_UDC_OTG_DOEPCTL0 S3C_USBOTGREG(0xB00) |
| 230 | +/* Device OUT Endpoint 0 Interrupt */ |
| 231 | +#define S3C_UDC_OTG_DOEPINT0 S3C_USBOTGREG(0xB08) |
| 232 | +/* Device OUT Endpoint 0 Transfer Size */ |
| 233 | +#define S3C_UDC_OTG_DOEPTSIZ0 S3C_USBOTGREG(0xB10) |
| 234 | +/* Device OUT Endpoint 0 DMA Address */ |
| 235 | +#define S3C_UDC_OTG_DOEPDMA0 S3C_USBOTGREG(0xB14) |
| 236 | + |
| 237 | +/* Device OUT Endpoint 1 Control */ |
| 238 | +#define S3C_UDC_OTG_DOEPCTL1 S3C_USBOTGREG(0xB20) |
| 239 | +/* Device OUT Endpoint 1 Interrupt */ |
| 240 | +#define S3C_UDC_OTG_DOEPINT1 S3C_USBOTGREG(0xB28) |
| 241 | +/* Device OUT Endpoint 1 Transfer Size */ |
| 242 | +#define S3C_UDC_OTG_DOEPTSIZ1 S3C_USBOTGREG(0xB30) |
| 243 | +/* Device OUT Endpoint 1 DMA Address */ |
| 244 | +#define S3C_UDC_OTG_DOEPDMA1 S3C_USBOTGREG(0xB34) |
| 245 | + |
| 246 | +/* Endpoint FIFO address */ |
| 247 | +#define S3C_UDC_OTG_EP0_FIFO S3C_USBOTGREG(0x1000) |
| 248 | +#define S3C_UDC_OTG_EP1_FIFO S3C_USBOTGREG(0x2000) |
| 249 | +#define S3C_UDC_OTG_EP2_FIFO S3C_USBOTGREG(0x3000) |
| 250 | +#define S3C_UDC_OTG_EP3_FIFO S3C_USBOTGREG(0x4000) |
| 251 | +#define S3C_UDC_OTG_EP4_FIFO S3C_USBOTGREG(0x5000) |
| 252 | +#define S3C_UDC_OTG_EP5_FIFO S3C_USBOTGREG(0x6000) |
| 253 | +#define S3C_UDC_OTG_EP6_FIFO S3C_USBOTGREG(0x7000) |
| 254 | +#define S3C_UDC_OTG_EP7_FIFO S3C_USBOTGREG(0x8000) |
| 255 | +#define S3C_UDC_OTG_EP8_FIFO S3C_USBOTGREG(0x9000) |
| 256 | + |
| 257 | +/* S3C_USBOTG_PHYPWR */ |
| 258 | +#define OTG_ENABLE (0x0<<4) |
| 259 | +#define OTG_DISABLE (0x1<<4) |
| 260 | +#define ANALOG_PWR_UP (0x0<<3) |
| 261 | +#define ANALOG_PWR_DOWN (0x1<<3) |
| 262 | +#define SUSPEND_DISABLE (0x0<<0) |
| 263 | +#define SUSPEND_ENABLE (0x1<<0) |
| 264 | + |
| 265 | +/* S3C_USBOTG_PHYCLK */ |
| 266 | +#define REF_CLK_CRYSTAL (0x0<<5) |
| 267 | +#define REF_CLK_OSCC (0x1<<5) |
| 268 | + |
| 269 | +/* S3C_USBOTG_RSTCON */ |
| 270 | +#define SW_RST_OFF (0x0<<0) |
| 271 | +#define SW_RST_ON (0x1<<0) |
| 272 | + |
| 273 | +/* S3C_UDC_OTG_GOTGCTL */ |
| 274 | +#define B_SESSION_VALID (0x1<<19) |
| 275 | +#define A_SESSION_VALID (0x1<<18) |
| 276 | + |
| 277 | +/* S3C_UDC_OTG_GAHBCFG */ |
| 278 | +#define PTXFE_HALF (0x0<<8) |
| 279 | +#define PTXFE_ZERO (0x1<<8) |
| 280 | +#define NPTXFE_HALF (0x0<<7) |
| 281 | +#define NPTXFE_ZERO (0x1<<7) |
| 282 | +#define MODE_SLAVE (0x0<<5) |
| 283 | +#define MODE_DMA (0x1<<5) |
| 284 | +#define BURST_SINGLE (0x0<<1) |
| 285 | +#define BURST_INCR (0x1<<1) |
| 286 | +#define BURST_INCR4 (0x3<<1) |
| 287 | +#define BURST_INCR8 (0x5<<1) |
| 288 | +#define BURST_INCR16 (0x7<<1) |
| 289 | +#define GBL_INT_UNMASK (0x1<<0) |
| 290 | +#define GBL_INT_MASK (0x0<<0) |
| 291 | + |
| 292 | +/* S3C_UDC_OTG_GUSBCFG */ |
| 293 | +#define PHY_CLK_480M (0x0<<15) |
| 294 | +#define PHY_CLK_48M (0x1<<15) |
| 295 | +#define TXFIFO_RE_DIS (0x0<<14) |
| 296 | +#define TXFIFO_RE_EN (0x1<<14) |
| 297 | +#define TURN_AROUND (0x5<<10) |
| 298 | +#define HNP_DISABLE (0x0<<9) |
| 299 | +#define HNP_ENABLE (0x1<<9) |
| 300 | +#define SRP_DISABLE (0x0<<8) |
| 301 | +#define SRP_ENABLE (0x1<<8) |
| 302 | +#define ULPI_DDR (0x0<<7) |
| 303 | +#define HS_UTMI (0x0<<6) |
| 304 | +#define INTERF_UTMI (0x0<<4) |
| 305 | +#define INTERF_ULPI (0x1<<4) |
| 306 | +#define PHY_INTERF_8 (0x0<<3) |
| 307 | +#define PHY_INTERF_16 (0x1<<3) |
| 308 | +#define TIME_OUT_CAL (0x7<<0) |
| 309 | + |
| 310 | +/* S3C_UDC_OTG_GRSTCTL */ |
| 311 | +#define AHB_MASTER_IDLE (1u<<31) |
| 312 | +#define CORE_SOFT_RESET (0x1<<0) |
| 313 | + |
| 314 | +/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */ |
| 315 | +#define INT_RESUME (0x1<<31) |
| 316 | +#define INT_DISCONN (0x1<<29) |
| 317 | +#define INT_CONN_CNG (0x1<<28) |
| 318 | +#define INT_OUT_EP (0x1<<19) |
| 319 | +#define INT_IN_EP (0x1<<18) |
| 320 | +#define INT_ENUMDONE (0x1<<13) |
| 321 | +#define INT_RESET (0x1<<12) |
| 322 | +#define INT_SUSPEND (0x1<<11) |
| 323 | +#define INT_EARLY_SUSPEND (0x1<<10) |
| 324 | +#define INT_TX_FIFO_EMPTY (0x1<<5) |
| 325 | +#define INT_RX_FIFO_NOT_EMPTY (0x1<<4) |
| 326 | +#define INT_SOF (0x1<<3) |
| 327 | +#define INT_DEV_MODE (0x0<<0) |
| 328 | +#define INT_HOST_MODE (0x1<<1) |
| 329 | + |
| 330 | +#define FULL_SPEED_CONTROL_PKT_SIZE 8 |
| 331 | +#define FULL_SPEED_BULK_PKT_SIZE 64 |
| 332 | + |
| 333 | +#define HIGH_SPEED_CONTROL_PKT_SIZE 64 |
| 334 | +#define HIGH_SPEED_BULK_PKT_SIZE 512 |
| 335 | + |
| 336 | +/* S3C_UDC_OTG_DSTS */ |
| 337 | +#define RX_FIFO_SIZE (2048<<0) |
| 338 | +#define NPTX_FIFO_START_ADDR (RX_FIFO_SIZE<<0) |
| 339 | +#define NPTX_FIFO_SIZE (2048<<16) |
| 340 | +#define PTX_FIFO_SIZE (2048<<16) |
| 341 | +#define USB_HIGH_30_60MHZ (0x0<<1) |
| 342 | +#define USB_FULL_30_60MHZ (0x1<<1) |
| 343 | +#define USB_LOW_6MHZ (0x2<<1) |
| 344 | +#define USB_FULL_48MHZ (0x3<<1) |
| 345 | + |
| 346 | +/* S3C_UDC_OTG_GRXSTSP */ |
| 347 | +#define BYTE_COUNT(x) ((x & (0x7FF<<4)) >> 4) |
| 348 | +#define PKT_STS(x) ((x & (0xF<<17)) >> 17) |
| 349 | +#define EP_NUM(x) (x & 0xF) |
| 350 | + |
| 351 | +#define OUT_PKT_RECEIVED (0x2) |
| 352 | +#define OUT_COMPLELTED (0x3) |
| 353 | +#define SETUP_COMPLETED (0x4) |
| 354 | +#define SETUP_PKT_RECEIVED (0x6) |
| 355 | + |
| 356 | +/* S3C_UDC_OTG_DCFG */ |
| 357 | +#define EP_MIS_CNT(x) (x<<18) |
| 358 | +#define DEVICE_ADDR(x) (x<<4) |
| 359 | +#define SPEED_2_HIGH (0x0<<0) |
| 360 | +#define SPEED_2_FULL (0x1<<0) |
| 361 | +#define SPEED_1_LOW (0x2<<0) |
| 362 | +#define SPEED_1_FULL (0x3<<0) |
| 363 | + |
| 364 | +/* S3C_UDC_OTG_DCTL device control register */ |
| 365 | +#define NORMAL_OPERATION (0x1<<0) |
| 366 | +#define SOFT_DISCONNECT (0x1<<1) |
| 367 | + |
| 368 | +/* S3C_UDC_OTG_DSTS */ |
| 369 | +#define ENUM_SPEED(x) (x & (0x3<<1)) |
| 370 | +#define FRAME_CNT(x) (x & (0x3ff<<8)) |
| 371 | + |
| 372 | +/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */ |
| 373 | +#define S3C_UDC_INT_IN_EP0 (0x1<<0) |
| 374 | +#define S3C_UDC_INT_IN_EP2 (0x1<<2) |
| 375 | +#define S3C_UDC_INT_IN_EP3 (0x1<<3) |
| 376 | +#define S3C_UDC_INT_OUT_EP0 (0x1<<16) |
| 377 | +#define S3C_UDC_INT_OUT_EP1 (0x1<<17) |
| 378 | +#define S3C_UDC_INT_OUT_EP4 (0x1<<20) |
| 379 | + |
| 380 | +/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control |
| 381 | + IN/OUT endpoint 0 control register */ |
| 382 | +#define DEPCTL_EPENA (0x1<<31) |
| 383 | +#define DEPCTL_EPDIS (0x1<<30) |
| 384 | +#define DEPCTL_SNAK (0x1<<27) |
| 385 | +#define DEPCTL_CNAK (0x1<<26) |
| 386 | +#define DEPCTL_CTRL_TYPE (0x0<<18) |
| 387 | +#define DEPCTL_ISO_TYPE (0x1<<18) |
| 388 | +#define DEPCTL_BULK_TYPE (0x2<<18) |
| 389 | +#define DEPCTL_INTR_TYPE (0x3<<18) |
| 390 | +#define DEPCTL_USBACTEP (0x1<<15) |
| 391 | +#define DEPCTL0_MPS_64 (0x0<<0) |
| 392 | +#define DEPCTL0_MPS_32 (0x1<<0) |
| 393 | +#define DEPCTL0_MPS_16 (0x2<<0) |
| 394 | +#define DEPCTL0_MPS_8 (0x3<<0) |
| 395 | + |
| 396 | +/* S3C_UDC_OTG_DIEPINTn */ |
| 397 | +#define IN_EP_NAK_EFF (0x1<<6) |
| 398 | +#define IN_TK_EPMIS (0x1<<5) |
| 399 | +#define IN_TK_TXFEMP (0x1<<4) |
| 400 | +#define IN_EP_TIMEOUT (0x1<<3) |
| 401 | + |
| 402 | +/* S3C_UDC_OTG_DOEPINTn */ |
| 403 | +#define BACK2BACK_SETUP (0x1<<6) |
| 404 | +#define OUT_TK_EP_DIS (0x1<<4) |
| 405 | +#define SETUP_PHASE_DONE (0x1<<3) |
| 406 | + |
| 407 | +/* S3C_UDC_OTG_DIEPINTn/DOEPINTn */ |
| 408 | +#define AHB_ERROR (0x1<<2) |
| 409 | +#define EPDISBLD (0x1<<1) |
| 410 | +#define TRANSFER_DONE (0x1<<0) |
| 411 | + |
| 412 | +/* S3C_UDC_OTG_DIEPTSIZn */ |
| 413 | +#define PKT_CNT(x) (x<<19) |
| 414 | +#define XFERSIZE(x) (x<<0) |
| 415 | + |
| 416 | +#endif |
| 417 | --- a/arch/arm/plat-s3c/Kconfig |
| 418 | +++ b/arch/arm/plat-s3c/Kconfig |
| 419 | @@ -184,4 +184,9 @@ config S3C_DEV_FB |
| 420 | help |
| 421 | Compile in platform device definition for framebuffer |
| 422 | |
| 423 | +config S3C_DEV_USB_HOST |
| 424 | + bool |
| 425 | + help |
| 426 | + Compile in platform device definition for USB host. |
| 427 | + |
| 428 | endif |
| 429 | --- a/arch/arm/plat-s3c/Makefile |
| 430 | +++ b/arch/arm/plat-s3c/Makefile |
| 431 | @@ -35,6 +35,8 @@ obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmm |
| 432 | obj-y += dev-i2c0.o |
| 433 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o |
| 434 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o |
| 435 | +obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o |
| 436 | + |
| 437 | obj-$(CONFIG_S3C_PWM) += pwm.o |
| 438 | obj-$(CONFIG_S3C_DMA) += dma.o |
| 439 | |
| 440 | --- a/arch/arm/plat-s3c24xx/devs.c |
| 441 | +++ b/arch/arm/plat-s3c24xx/devs.c |
| 442 | @@ -136,36 +136,6 @@ struct platform_device *s3c24xx_uart_src |
| 443 | struct platform_device *s3c24xx_uart_devs[4] = { |
| 444 | }; |
| 445 | |
| 446 | -/* USB Host Controller */ |
| 447 | - |
| 448 | -static struct resource s3c_usb_resource[] = { |
| 449 | - [0] = { |
| 450 | - .start = S3C24XX_PA_USBHOST, |
| 451 | - .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1, |
| 452 | - .flags = IORESOURCE_MEM, |
| 453 | - }, |
| 454 | - [1] = { |
| 455 | - .start = IRQ_USBH, |
| 456 | - .end = IRQ_USBH, |
| 457 | - .flags = IORESOURCE_IRQ, |
| 458 | - } |
| 459 | -}; |
| 460 | - |
| 461 | -static u64 s3c_device_usb_dmamask = 0xffffffffUL; |
| 462 | - |
| 463 | -struct platform_device s3c_device_usb = { |
| 464 | - .name = "s3c2410-ohci", |
| 465 | - .id = -1, |
| 466 | - .num_resources = ARRAY_SIZE(s3c_usb_resource), |
| 467 | - .resource = s3c_usb_resource, |
| 468 | - .dev = { |
| 469 | - .dma_mask = &s3c_device_usb_dmamask, |
| 470 | - .coherent_dma_mask = 0xffffffffUL |
| 471 | - } |
| 472 | -}; |
| 473 | - |
| 474 | -EXPORT_SYMBOL(s3c_device_usb); |
| 475 | - |
| 476 | /* LCD Controller */ |
| 477 | |
| 478 | static struct resource s3c_lcd_resource[] = { |
| 479 | |
