| 1 | /* |
| 2 | * arch/ubicom32/include/asm/gpio.h |
| 3 | * Definitions for GPIO operations on Ubicom32 architecture. |
| 4 | * |
| 5 | * (C) Copyright 2009, Ubicom, Inc. |
| 6 | * |
| 7 | * This file is part of the Ubicom32 Linux Kernel Port. |
| 8 | * |
| 9 | * The Ubicom32 Linux Kernel Port is free software: you can redistribute |
| 10 | * it and/or modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation, either version 2 of the |
| 12 | * License, or (at your option) any later version. |
| 13 | * |
| 14 | * The Ubicom32 Linux Kernel Port is distributed in the hope that it |
| 15 | * will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 16 | * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 17 | * the GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with the Ubicom32 Linux Kernel Port. If not, |
| 21 | * see <http://www.gnu.org/licenses/>. |
| 22 | * |
| 23 | * Ubicom32 implementation derived from (with many thanks): |
| 24 | * arch/m68knommu |
| 25 | * arch/blackfin |
| 26 | * arch/parisc |
| 27 | */ |
| 28 | #ifndef _ASM_UBICOM32_GPIO_H |
| 29 | #define _ASM_UBICOM32_GPIO_H |
| 30 | |
| 31 | #include <linux/compiler.h> |
| 32 | #include <asm/irq.h> |
| 33 | |
| 34 | #include <asm/ip5000.h> |
| 35 | |
| 36 | #define ARCH_NR_GPIOS 512 |
| 37 | #define MAX_UBICOM_ONCHIP_GPIO (9 * 32) |
| 38 | |
| 39 | /* |
| 40 | * Macros for manipulating GPIO numbers |
| 41 | */ |
| 42 | #define gpio_bit(gn) (1 << (gn & 0x1f)) |
| 43 | #define gpio_bank(gn) (gn >> 5) |
| 44 | |
| 45 | #define gpio_pin_index(gn) (gn & 0x1f) |
| 46 | #define gpio_port_index(gn) (gn >> 5) |
| 47 | |
| 48 | #define GPIO_RA_0 ((32 * 0) + 0) |
| 49 | #define GPIO_RA_1 ((32 * 0) + 1) |
| 50 | #define GPIO_RA_2 ((32 * 0) + 2) |
| 51 | #define GPIO_RA_3 ((32 * 0) + 3) |
| 52 | #define GPIO_RA_4 ((32 * 0) + 4) |
| 53 | #define GPIO_RA_5 ((32 * 0) + 5) |
| 54 | #define GPIO_RA_6 ((32 * 0) + 6) |
| 55 | #define GPIO_RA_7 ((32 * 0) + 7) |
| 56 | |
| 57 | #define GPIO_RB_0 ((32 * 1) + 0) |
| 58 | #define GPIO_RB_1 ((32 * 1) + 1) |
| 59 | #define GPIO_RB_2 ((32 * 1) + 2) |
| 60 | #define GPIO_RB_3 ((32 * 1) + 3) |
| 61 | #define GPIO_RB_4 ((32 * 1) + 4) |
| 62 | #define GPIO_RB_5 ((32 * 1) + 5) |
| 63 | #define GPIO_RB_6 ((32 * 1) + 6) |
| 64 | #define GPIO_RB_7 ((32 * 1) + 7) |
| 65 | #define GPIO_RB_8 ((32 * 1) + 8) |
| 66 | #define GPIO_RB_9 ((32 * 1) + 9) |
| 67 | #define GPIO_RB_10 ((32 * 1) + 10) |
| 68 | #define GPIO_RB_11 ((32 * 1) + 11) |
| 69 | #define GPIO_RB_12 ((32 * 1) + 12) |
| 70 | #define GPIO_RB_13 ((32 * 1) + 13) |
| 71 | #define GPIO_RB_14 ((32 * 1) + 14) |
| 72 | #define GPIO_RB_15 ((32 * 1) + 15) |
| 73 | #define GPIO_RB_16 ((32 * 1) + 16) |
| 74 | #define GPIO_RB_17 ((32 * 1) + 17) |
| 75 | #define GPIO_RB_18 ((32 * 1) + 18) |
| 76 | #define GPIO_RB_19 ((32 * 1) + 19) |
| 77 | |
| 78 | #define GPIO_RC_0 ((32 * 2) + 0) |
| 79 | #define GPIO_RC_1 ((32 * 2) + 1) |
| 80 | #define GPIO_RC_2 ((32 * 2) + 2) |
| 81 | #define GPIO_RC_3 ((32 * 2) + 3) |
| 82 | #define GPIO_RC_4 ((32 * 2) + 4) |
| 83 | #define GPIO_RC_5 ((32 * 2) + 5) |
| 84 | #define GPIO_RC_6 ((32 * 2) + 6) |
| 85 | #define GPIO_RC_7 ((32 * 2) + 7) |
| 86 | #define GPIO_RC_8 ((32 * 2) + 8) |
| 87 | #define GPIO_RC_9 ((32 * 2) + 9) |
| 88 | #define GPIO_RC_10 ((32 * 2) + 10) |
| 89 | #define GPIO_RC_11 ((32 * 2) + 11) |
| 90 | #define GPIO_RC_12 ((32 * 2) + 12) |
| 91 | #define GPIO_RC_13 ((32 * 2) + 13) |
| 92 | #define GPIO_RC_14 ((32 * 2) + 14) |
| 93 | #define GPIO_RC_15 ((32 * 2) + 15) |
| 94 | #define GPIO_RC_16 ((32 * 2) + 16) |
| 95 | #define GPIO_RC_17 ((32 * 2) + 17) |
| 96 | #define GPIO_RC_18 ((32 * 2) + 18) |
| 97 | #define GPIO_RC_19 ((32 * 2) + 19) |
| 98 | #define GPIO_RC_20 ((32 * 2) + 20) |
| 99 | #define GPIO_RC_21 ((32 * 2) + 21) |
| 100 | #define GPIO_RC_22 ((32 * 2) + 22) |
| 101 | #define GPIO_RC_23 ((32 * 2) + 23) |
| 102 | #define GPIO_RC_24 ((32 * 2) + 24) |
| 103 | #define GPIO_RC_25 ((32 * 2) + 25) |
| 104 | #define GPIO_RC_26 ((32 * 2) + 26) |
| 105 | #define GPIO_RC_27 ((32 * 2) + 27) |
| 106 | #define GPIO_RC_28 ((32 * 2) + 28) |
| 107 | #define GPIO_RC_29 ((32 * 2) + 29) |
| 108 | #define GPIO_RC_30 ((32 * 2) + 30) |
| 109 | #define GPIO_RC_31 ((32 * 2) + 31) |
| 110 | |
| 111 | #define GPIO_RD_0 ((32 * 3) + 0) |
| 112 | #define GPIO_RD_1 ((32 * 3) + 1) |
| 113 | #define GPIO_RD_2 ((32 * 3) + 2) |
| 114 | #define GPIO_RD_3 ((32 * 3) + 3) |
| 115 | #define GPIO_RD_4 ((32 * 3) + 4) |
| 116 | #define GPIO_RD_5 ((32 * 3) + 5) |
| 117 | #define GPIO_RD_6 ((32 * 3) + 6) |
| 118 | #define GPIO_RD_7 ((32 * 3) + 7) |
| 119 | #define GPIO_RD_8 ((32 * 3) + 8) |
| 120 | #define GPIO_RD_9 ((32 * 3) + 9) |
| 121 | #define GPIO_RD_10 ((32 * 3) + 10) |
| 122 | #define GPIO_RD_11 ((32 * 3) + 11) |
| 123 | |
| 124 | #define GPIO_RE_0 ((32 * 4) + 0) |
| 125 | #define GPIO_RE_1 ((32 * 4) + 1) |
| 126 | #define GPIO_RE_2 ((32 * 4) + 2) |
| 127 | #define GPIO_RE_3 ((32 * 4) + 3) |
| 128 | #define GPIO_RE_4 ((32 * 4) + 4) |
| 129 | #define GPIO_RE_5 ((32 * 4) + 5) |
| 130 | #define GPIO_RE_6 ((32 * 4) + 6) |
| 131 | #define GPIO_RE_7 ((32 * 4) + 7) |
| 132 | |
| 133 | #define GPIO_RF_0 ((32 * 5) + 0) |
| 134 | #define GPIO_RF_1 ((32 * 5) + 1) |
| 135 | #define GPIO_RF_2 ((32 * 5) + 2) |
| 136 | #define GPIO_RF_3 ((32 * 5) + 3) |
| 137 | #define GPIO_RF_4 ((32 * 5) + 4) |
| 138 | #define GPIO_RF_5 ((32 * 5) + 5) |
| 139 | #define GPIO_RF_6 ((32 * 5) + 6) |
| 140 | #define GPIO_RF_7 ((32 * 5) + 7) |
| 141 | #define GPIO_RF_8 ((32 * 5) + 8) |
| 142 | #define GPIO_RF_9 ((32 * 5) + 9) |
| 143 | #define GPIO_RF_10 ((32 * 5) + 10) |
| 144 | #define GPIO_RF_11 ((32 * 5) + 11) |
| 145 | #define GPIO_RF_12 ((32 * 5) + 12) |
| 146 | #define GPIO_RF_13 ((32 * 5) + 13) |
| 147 | #define GPIO_RF_14 ((32 * 5) + 14) |
| 148 | #define GPIO_RF_15 ((32 * 5) + 15) |
| 149 | |
| 150 | #define GPIO_RG_0 ((32 * 6) + 0) |
| 151 | #define GPIO_RG_1 ((32 * 6) + 1) |
| 152 | #define GPIO_RG_2 ((32 * 6) + 2) |
| 153 | #define GPIO_RG_3 ((32 * 6) + 3) |
| 154 | #define GPIO_RG_4 ((32 * 6) + 4) |
| 155 | #define GPIO_RG_5 ((32 * 6) + 5) |
| 156 | #define GPIO_RG_6 ((32 * 6) + 6) |
| 157 | #define GPIO_RG_7 ((32 * 6) + 7) |
| 158 | #define GPIO_RG_8 ((32 * 6) + 8) |
| 159 | #define GPIO_RG_9 ((32 * 6) + 9) |
| 160 | #define GPIO_RG_10 ((32 * 6) + 10) |
| 161 | #define GPIO_RG_11 ((32 * 6) + 11) |
| 162 | #define GPIO_RG_12 ((32 * 6) + 12) |
| 163 | #define GPIO_RG_13 ((32 * 6) + 13) |
| 164 | #define GPIO_RG_14 ((32 * 6) + 14) |
| 165 | #define GPIO_RG_15 ((32 * 6) + 15) |
| 166 | #define GPIO_RG_16 ((32 * 6) + 16) |
| 167 | #define GPIO_RG_17 ((32 * 6) + 17) |
| 168 | #define GPIO_RG_18 ((32 * 6) + 18) |
| 169 | #define GPIO_RG_19 ((32 * 6) + 19) |
| 170 | #define GPIO_RG_20 ((32 * 6) + 20) |
| 171 | #define GPIO_RG_21 ((32 * 6) + 21) |
| 172 | #define GPIO_RG_22 ((32 * 6) + 22) |
| 173 | #define GPIO_RG_23 ((32 * 6) + 23) |
| 174 | #define GPIO_RG_24 ((32 * 6) + 24) |
| 175 | #define GPIO_RG_25 ((32 * 6) + 25) |
| 176 | #define GPIO_RG_26 ((32 * 6) + 26) |
| 177 | #define GPIO_RG_27 ((32 * 6) + 27) |
| 178 | #define GPIO_RG_28 ((32 * 6) + 28) |
| 179 | #define GPIO_RG_29 ((32 * 6) + 29) |
| 180 | #define GPIO_RG_30 ((32 * 6) + 30) |
| 181 | #define GPIO_RG_31 ((32 * 6) + 31) |
| 182 | |
| 183 | #define GPIO_RH_0 ((32 * 7) + 0) |
| 184 | #define GPIO_RH_1 ((32 * 7) + 1) |
| 185 | #define GPIO_RH_2 ((32 * 7) + 2) |
| 186 | #define GPIO_RH_3 ((32 * 7) + 3) |
| 187 | #define GPIO_RH_4 ((32 * 7) + 4) |
| 188 | #define GPIO_RH_5 ((32 * 7) + 5) |
| 189 | #define GPIO_RH_6 ((32 * 7) + 6) |
| 190 | #define GPIO_RH_7 ((32 * 7) + 7) |
| 191 | #define GPIO_RH_8 ((32 * 7) + 8) |
| 192 | #define GPIO_RH_9 ((32 * 7) + 9) |
| 193 | |
| 194 | #define GPIO_RI_0 ((32 * 8) + 0) |
| 195 | #define GPIO_RI_1 ((32 * 8) + 1) |
| 196 | #define GPIO_RI_2 ((32 * 8) + 2) |
| 197 | #define GPIO_RI_3 ((32 * 8) + 3) |
| 198 | #define GPIO_RI_4 ((32 * 8) + 4) |
| 199 | #define GPIO_RI_5 ((32 * 8) + 5) |
| 200 | #define GPIO_RI_6 ((32 * 8) + 6) |
| 201 | #define GPIO_RI_7 ((32 * 8) + 7) |
| 202 | #define GPIO_RI_8 ((32 * 8) + 8) |
| 203 | #define GPIO_RI_9 ((32 * 8) + 9) |
| 204 | #define GPIO_RI_10 ((32 * 8) + 10) |
| 205 | #define GPIO_RI_11 ((32 * 8) + 11) |
| 206 | #define GPIO_RI_12 ((32 * 8) + 12) |
| 207 | #define GPIO_RI_13 ((32 * 8) + 13) |
| 208 | #define GPIO_RI_14 ((32 * 8) + 14) |
| 209 | #define GPIO_RI_15 ((32 * 8) + 15) |
| 210 | |
| 211 | /* |
| 212 | * The following section defines extra GPIO available to some boards. |
| 213 | * These GPIO are generally external to the processor (i.e. SPI/I2C |
| 214 | * expander chips). |
| 215 | * |
| 216 | * Note that these defines show all possible GPIO available, however, |
| 217 | * depending on the actual board configuration, some GPIO are not |
| 218 | * available for use. |
| 219 | */ |
| 220 | #ifdef CONFIG_IP7500MEDIA |
| 221 | /* |
| 222 | * U15 |
| 223 | */ |
| 224 | #define IP7500MEDIA_U15_BASE (32 * 10) |
| 225 | #define IP7500MEDIA_IO0 (IP7500MEDIA_U15_BASE + 0) |
| 226 | #define IP7500MEDIA_IO1 (IP7500MEDIA_U15_BASE + 1) |
| 227 | #define IP7500MEDIA_IO2 (IP7500MEDIA_U15_BASE + 2) |
| 228 | #define IP7500MEDIA_IO3 (IP7500MEDIA_U15_BASE + 3) |
| 229 | #define IP7500MEDIA_IO4 (IP7500MEDIA_U15_BASE + 4) |
| 230 | #define IP7500MEDIA_IO5 (IP7500MEDIA_U15_BASE + 5) |
| 231 | #define IP7500MEDIA_IO6 (IP7500MEDIA_U15_BASE + 6) |
| 232 | #define IP7500MEDIA_IO7 (IP7500MEDIA_U15_BASE + 7) |
| 233 | |
| 234 | /* |
| 235 | * U16 |
| 236 | */ |
| 237 | #define IP7500MEDIA_U16_BASE (32 * 11) |
| 238 | #define IP7500MEDIA_IO8 (IP7500MEDIA_U16_BASE + 0) |
| 239 | #define IP7500MEDIA_IO9 (IP7500MEDIA_U16_BASE + 1) |
| 240 | #define IP7500MEDIA_IO10 (IP7500MEDIA_U16_BASE + 2) |
| 241 | #define IP7500MEDIA_IO11 (IP7500MEDIA_U16_BASE + 3) |
| 242 | #define IP7500MEDIA_IO12 (IP7500MEDIA_U16_BASE + 4) |
| 243 | #define IP7500MEDIA_IO13 (IP7500MEDIA_U16_BASE + 5) |
| 244 | #define IP7500MEDIA_IO14 (IP7500MEDIA_U16_BASE + 6) |
| 245 | #define IP7500MEDIA_IO15 (IP7500MEDIA_U16_BASE + 7) |
| 246 | |
| 247 | /* |
| 248 | * U17 |
| 249 | */ |
| 250 | #define IP7500MEDIA_U17_BASE (32 * 12) |
| 251 | #define IP7500MEDIA_IO16 (IP7500MEDIA_U17_BASE + 0) |
| 252 | #define IP7500MEDIA_IO17 (IP7500MEDIA_U17_BASE + 1) |
| 253 | #define IP7500MEDIA_IO18 (IP7500MEDIA_U17_BASE + 2) |
| 254 | #define IP7500MEDIA_IO19 (IP7500MEDIA_U17_BASE + 3) |
| 255 | #define IP7500MEDIA_IO20 (IP7500MEDIA_U17_BASE + 4) |
| 256 | #define IP7500MEDIA_IO21 (IP7500MEDIA_U17_BASE + 5) |
| 257 | #define IP7500MEDIA_IO22 (IP7500MEDIA_U17_BASE + 6) |
| 258 | #define IP7500MEDIA_IO23 (IP7500MEDIA_U17_BASE + 7) |
| 259 | |
| 260 | /* |
| 261 | * U18 |
| 262 | */ |
| 263 | #define IP7500MEDIA_U18_BASE (32 * 13) |
| 264 | #define IP7500MEDIA_IO24 (IP7500MEDIA_U18_BASE + 0) |
| 265 | #define IP7500MEDIA_IO25 (IP7500MEDIA_U18_BASE + 1) |
| 266 | #define IP7500MEDIA_IO26 (IP7500MEDIA_U18_BASE + 2) |
| 267 | #define IP7500MEDIA_IO27 (IP7500MEDIA_U18_BASE + 3) |
| 268 | #define IP7500MEDIA_IO28 (IP7500MEDIA_U18_BASE + 4) |
| 269 | #define IP7500MEDIA_IO29 (IP7500MEDIA_U18_BASE + 5) |
| 270 | #define IP7500MEDIA_IO30 (IP7500MEDIA_U18_BASE + 6) |
| 271 | #define IP7500MEDIA_IO31 (IP7500MEDIA_U18_BASE + 7) |
| 272 | #endif |
| 273 | |
| 274 | #ifdef CONFIG_IP7145DPF |
| 275 | /* |
| 276 | * U48 |
| 277 | */ |
| 278 | #define IP7145DPF_U48_BASE (32 * 10) |
| 279 | #define IP7145DPF_IO0 (IP7145DPF_U48_BASE + 0) |
| 280 | #define IP7145DPF_IO1 (IP7145DPF_U48_BASE + 1) |
| 281 | #define IP7145DPF_IO2 (IP7145DPF_U48_BASE + 2) |
| 282 | #define IP7145DPF_IO3 (IP7145DPF_U48_BASE + 3) |
| 283 | #define IP7145DPF_IO4 (IP7145DPF_U48_BASE + 4) |
| 284 | #define IP7145DPF_IO5 (IP7145DPF_U48_BASE + 5) |
| 285 | #define IP7145DPF_IO6 (IP7145DPF_U48_BASE + 6) |
| 286 | #define IP7145DPF_IO7 (IP7145DPF_U48_BASE + 7) |
| 287 | |
| 288 | /* |
| 289 | * U72 |
| 290 | */ |
| 291 | #define IP7145DPF_U72_BASE (32 * 11) |
| 292 | #define IP7145DPF_IOB0 (IP7145DPF_U72_BASE + 0) |
| 293 | #define IP7145DPF_IOB1 (IP7145DPF_U72_BASE + 1) |
| 294 | #define IP7145DPF_IOB2 (IP7145DPF_U72_BASE + 2) |
| 295 | #define IP7145DPF_IOB3 (IP7145DPF_U72_BASE + 3) |
| 296 | #define IP7145DPF_IOB4 (IP7145DPF_U72_BASE + 4) |
| 297 | #define IP7145DPF_IOB5 (IP7145DPF_U72_BASE + 5) |
| 298 | #define IP7145DPF_IOB6 (IP7145DPF_U72_BASE + 6) |
| 299 | #define IP7145DPF_IOB7 (IP7145DPF_U72_BASE + 7) |
| 300 | #endif |
| 301 | |
| 302 | #include <asm-generic/gpio.h> |
| 303 | |
| 304 | /* |
| 305 | * The following macros bypass gpiolib to generate direct references |
| 306 | * to the port registers. These assume, minimally, that either |
| 307 | * gpio_direction_input() or gpio_direction_output() have already been |
| 308 | * called to setup the pin direction and to enable the pin function to |
| 309 | * be gpio. These macros generate the hardware port address based on |
| 310 | * the assumption that all ports are 32 bits wide (even though we know |
| 311 | * they are not). This is so we can efficiently turn pin numbers into |
| 312 | * port addresses without a lookup. |
| 313 | * |
| 314 | * These operations must be done in one instruction to prevent clobbering |
| 315 | * other thread's accesses to the same port. |
| 316 | */ |
| 317 | #define UBICOM32_GPIO_ENABLE(pin) \ |
| 318 | do { \ |
| 319 | asm volatile ("or.4 (%[port]), (%[port]), %[mask]\n\t" \ |
| 320 | : \ |
| 321 | : [port] "a" (&UBICOM32_IO_PORT(IO_BASE + (gpio_bank(pin) << 12))->gpio_mask), \ |
| 322 | [mask] "d" (gpio_bit(pin)) \ |
| 323 | : "cc", "memory" \ |
| 324 | ); \ |
| 325 | } while (0); |
| 326 | |
| 327 | #define UBICOM32_GPIO_DISABLE(pin) \ |
| 328 | do { \ |
| 329 | asm volatile ("and.4 (%[port]), (%[port]), %[mask]\n\t" \ |
| 330 | : \ |
| 331 | : [port] "a" (&UBICOM32_IO_PORT(IO_BASE + (gpio_bank(pin) << 12))->gpio_mask), \ |
| 332 | [mask] "d" (~gpio_bit(pin)) \ |
| 333 | : "cc", "memory" \ |
| 334 | ); \ |
| 335 | } while (0); |
| 336 | |
| 337 | #define UBICOM32_GPIO_SET_PIN_INPUT(pin) \ |
| 338 | do { \ |
| 339 | asm volatile ("and.4 (%[port]), (%[port]), %[mask]\n\t" \ |
| 340 | : \ |
| 341 | : [port] "a" (&UBICOM32_IO_PORT(IO_BASE + (gpio_bank(pin) << 12))->gpio_ctl), \ |
| 342 | [mask] "d" (~gpio_bit(pin)) \ |
| 343 | : "cc", "memory" \ |
| 344 | ); \ |
| 345 | } while (0); |
| 346 | |
| 347 | #define UBICOM32_GPIO_SET_PIN_OUTPUT(pin) \ |
| 348 | do { \ |
| 349 | asm volatile ("or.4 (%[port]), (%[port]), %[mask]\n\t" \ |
| 350 | : \ |
| 351 | : [port] "a" (&UBICOM32_IO_PORT(IO_BASE + (gpio_bank(pin) << 12))->gpio_ctl), \ |
| 352 | [mask] "d" (gpio_bit(pin)) \ |
| 353 | : "cc", "memory" \ |
| 354 | ); \ |
| 355 | } while (0); |
| 356 | |
| 357 | #define UBICOM32_GPIO_SET_PIN_TOGGLE(pin) \ |
| 358 | do { \ |
| 359 | asm volatile ("xor.4 (%[port]), (%[port]), %[mask]\n\t" \ |
| 360 | : \ |
| 361 | : [port] "a" (&UBICOM32_IO_PORT(IO_BASE + (gpio_bank(pin) << 12))->gpio_out), \ |
| 362 | [mask] "d" (gpio_bit(pin)) \ |
| 363 | : "cc", "memory" \ |
| 364 | ); \ |
| 365 | } while (0); |
| 366 | |
| 367 | #define UBICOM32_GPIO_SET_PIN_HIGH(pin) \ |
| 368 | do { \ |
| 369 | asm volatile ("or.4 (%[port]), (%[port]), %[mask]\n\t" \ |
| 370 | : \ |
| 371 | : [port] "a" (&UBICOM32_IO_PORT(IO_BASE + (gpio_bank(pin) << 12))->gpio_out), \ |
| 372 | [mask] "d" (gpio_bit(pin)) \ |
| 373 | : "cc", "memory" \ |
| 374 | ); \ |
| 375 | } while (0); |
| 376 | |
| 377 | #define UBICOM32_GPIO_SET_PIN_LOW(pin) \ |
| 378 | do { \ |
| 379 | asm volatile ("and.4 (%[port]), (%[port]), %[mask]\n\t" \ |
| 380 | : \ |
| 381 | : [port] "a" (&UBICOM32_IO_PORT(IO_BASE + (gpio_bank(pin) << 12))->gpio_out), \ |
| 382 | [mask] "d" (~gpio_bit(pin)) \ |
| 383 | : "cc", "memory" \ |
| 384 | ); \ |
| 385 | } while (0); |
| 386 | |
| 387 | #define UBICOM32_GPIO_SET_PIN(pin, val) \ |
| 388 | if ( val ) { \ |
| 389 | UBICOM32_GPIO_SET_PIN_HIGH(pin); \ |
| 390 | } else { \ |
| 391 | UBICOM32_GPIO_SET_PIN_LOW(pin); \ |
| 392 | } |
| 393 | |
| 394 | #define UBICOM32_GPIO_GET_PIN(pin) \ |
| 395 | (0 != (UBICOM32_IO_PORT(IO_BASE + (gpio_bank(pin) << 12))->gpio_in \ |
| 396 | & gpio_bit(pin))) |
| 397 | |
| 398 | |
| 399 | static inline int gpio_get_value(unsigned gpio) |
| 400 | { |
| 401 | if (gpio <= MAX_UBICOM_ONCHIP_GPIO) |
| 402 | return UBICOM32_GPIO_GET_PIN(gpio); |
| 403 | else |
| 404 | return __gpio_get_value(gpio); |
| 405 | } |
| 406 | |
| 407 | static inline void gpio_set_value(unsigned gpio, int value) |
| 408 | { |
| 409 | if (gpio <= MAX_UBICOM_ONCHIP_GPIO) |
| 410 | { |
| 411 | UBICOM32_GPIO_SET_PIN(gpio, value); |
| 412 | } |
| 413 | else |
| 414 | { |
| 415 | __gpio_set_value(gpio, value); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | static inline int gpio_cansleep(unsigned gpio) |
| 420 | { |
| 421 | return __gpio_cansleep(gpio); |
| 422 | } |
| 423 | |
| 424 | static inline int gpio_to_irq(unsigned gpio) |
| 425 | { |
| 426 | #if defined(IP5000) || defined(IP5000_REV2) |
| 427 | if ((gpio >= GPIO_RA_4) && (gpio <= GPIO_RA_6)) |
| 428 | return 25; |
| 429 | else |
| 430 | return -ENXIO; |
| 431 | |
| 432 | #elif defined(IP7000) || defined(IP7000_REV2) |
| 433 | if ((gpio >= GPIO_RA_4) && (gpio <= GPIO_RA_6)) |
| 434 | return 44 + (gpio - GPIO_RA_4); |
| 435 | else |
| 436 | return -ENXIO; |
| 437 | |
| 438 | #else |
| 439 | return -ENXIO; |
| 440 | |
| 441 | #endif |
| 442 | } |
| 443 | |
| 444 | static inline int irq_to_gpio(unsigned gpio) |
| 445 | { |
| 446 | return -ENXIO; |
| 447 | } |
| 448 | |
| 449 | extern struct ubicom32_io_port *ubi_gpio_get_port(unsigned gpio); |
| 450 | |
| 451 | extern int __init ubi_gpio_init(void); |
| 452 | |
| 453 | #endif /* _ASM_UBICOM32_GPIO_H */ |
| 454 | |
