| 1 | /* |
| 2 | * arch/ubicom32/include/asm/ip5000.h |
| 3 | * Specific details for the Ubicom IP5000 processor. |
| 4 | * |
| 5 | * (C) Copyright 2009, Ubicom, Inc. |
| 6 | * |
| 7 | * This file is part of the Ubicom32 Linux Kernel Port. |
| 8 | * |
| 9 | * The Ubicom32 Linux Kernel Port is free software: you can redistribute |
| 10 | * it and/or modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation, either version 2 of the |
| 12 | * License, or (at your option) any later version. |
| 13 | * |
| 14 | * The Ubicom32 Linux Kernel Port is distributed in the hope that it |
| 15 | * will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 16 | * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 17 | * the GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with the Ubicom32 Linux Kernel Port. If not, |
| 21 | * see <http://www.gnu.org/licenses/>. |
| 22 | * |
| 23 | * Ubicom32 implementation derived from (with many thanks): |
| 24 | * arch/m68knommu |
| 25 | * arch/blackfin |
| 26 | * arch/parisc |
| 27 | */ |
| 28 | |
| 29 | #ifndef _ASM_UBICOM32_IP5000_H |
| 30 | #define _ASM_UBICOM32_IP5000_H |
| 31 | |
| 32 | #include <asm/memory_map.h> |
| 33 | |
| 34 | /* |
| 35 | * Inline assembly define |
| 36 | */ |
| 37 | #define S(arg) #arg |
| 38 | #define D(arg) S(arg) |
| 39 | |
| 40 | /* |
| 41 | * Assembler include file |
| 42 | */ |
| 43 | #include <asm/ip5000-asm.h> |
| 44 | |
| 45 | /* |
| 46 | * Timing |
| 47 | */ |
| 48 | #define JMPT_PENALTY 3 |
| 49 | #define JMPF_PENALTY 7 |
| 50 | #define RET_PENALTY 7 |
| 51 | |
| 52 | /* |
| 53 | * Threads |
| 54 | */ |
| 55 | #if defined(IP5000) || defined(IP5000_REV2) |
| 56 | #define THREAD_COUNT 10 |
| 57 | #elif defined(IP7000) || defined(IP7000_REV2) |
| 58 | #define THREAD_COUNT 12 |
| 59 | #else |
| 60 | #error "Unknown IP5K silicon" |
| 61 | #endif |
| 62 | |
| 63 | /* |
| 64 | * Arch |
| 65 | */ |
| 66 | #if defined(IP5000) || defined(IP5000_REV2) |
| 67 | #define UBICOM32_ARCH_VERSION 3 |
| 68 | #elif defined(IP7000) || defined(IP7000_REV2) |
| 69 | #define UBICOM32_ARCH_VERSION 4 |
| 70 | #else |
| 71 | #error "Unknown IP5K silicon" |
| 72 | #endif |
| 73 | |
| 74 | |
| 75 | /* |
| 76 | * Registers |
| 77 | */ |
| 78 | #define ROSR_INT (1 << 0) |
| 79 | |
| 80 | /* Interrupts */ |
| 81 | #define INT_CHIP(reg, bit) (((reg) << 5) | (bit)) |
| 82 | #define INT_REG(interrupt) (((interrupt) >> 5) * 4) |
| 83 | #define INT_SET(interrupt) 0x0114 + INT_REG(interrupt) |
| 84 | #define INT_CLR(interrupt) 0x0124 + INT_REG(interrupt) |
| 85 | #define INT_STAT(interrupt) 0x0104 + INT_REG(interrupt) |
| 86 | #define INT_MASK(interrupt) 0x00C0 + INT_REG(interrupt) |
| 87 | #define INT_BIT(interrupt) ((interrupt) & 0x1F) |
| 88 | #define INT_BIT_MASK(interrupt) (1 << INT_BIT(interrupt)) |
| 89 | |
| 90 | /* |
| 91 | * The LOCK_INT and THREAD_INT are used to wake up corresponding thread. They are sharing |
| 92 | * the same set of SW interrupt resource. |
| 93 | * |
| 94 | * LOCK_INT(n): One SW INT per NRT thread that can participate lock operation. |
| 95 | * The threads that can participate lock are application threads and DSR thread. |
| 96 | * (Lock locks - numbers are hard-coded in lock.h) |
| 97 | * THREAD_INT(n): One SW INT per HRT thread for wake up trigger. |
| 98 | */ |
| 99 | #define LOCK_INT(thread) INT_CHIP(0, (thread)) |
| 100 | #define THREAD_INT(thread) INT_CHIP(0, (thread)) |
| 101 | |
| 102 | /* |
| 103 | * The SYSTEM_INT and DSR_INT are sharing the same set of SW interrupt resource. |
| 104 | * |
| 105 | * SYSTEM_INT(n): One SW INT per NRT threads (application threads) as system queue interrupt, |
| 106 | * and for DSR as self-trigger interrupt. |
| 107 | * (The application threads include at least thread 0) |
| 108 | * DSR_INT(n): One SW INT per HRT thread to request DSR service. |
| 109 | */ |
| 110 | #define SYSTEM_INT(thread) INT_CHIP(0, THREAD_COUNT + (thread)) |
| 111 | #define DSR_INT(thread) INT_CHIP(0, THREAD_COUNT + (thread)) |
| 112 | |
| 113 | /* GLOBAL_CTRL */ |
| 114 | #define GLOBAL_CTRL_TRAP_RST_EN (1 << 9) |
| 115 | #define GLOBAL_CTRL_AERROR_RST_EN (1 << 8) |
| 116 | #define GLOBAL_CTRL_MT_MIN_DELAY(x) ((x) << 3) |
| 117 | #define GLOBAL_CTRL_HRT_BANK_SELECT (1 << 2) |
| 118 | #define GLOBAL_CTRL_INT_EN (1 << 0) |
| 119 | |
| 120 | /* |
| 121 | * HRT Tables |
| 122 | */ |
| 123 | #define HRT_TABLE0_BASE 0x0800 |
| 124 | #define HRT_TABLE1_BASE 0x0900 |
| 125 | #define HRT_TABLE_SIZE 64 |
| 126 | |
| 127 | /* |
| 128 | * Break Point Trap Register |
| 129 | */ |
| 130 | #define ASYNCERROR_INT INT_CHIP(0, 31) |
| 131 | #define BREAKPOINT_INT INT_CHIP(1, 31) |
| 132 | |
| 133 | /* |
| 134 | * Port interrupts |
| 135 | * The non-existing FIFO INTs are mapped to INT2 for the ports. |
| 136 | */ |
| 137 | #define IO_PORT_PTR_TO_NUM(port) (((port) & 0x0000ffff) >> 12) |
| 138 | #define RX_FIFO_INT(port) \ |
| 139 | ((IO_PORT_PTR_TO_NUM(port) == 0) ? INT_CHIP(0, 25) : \ |
| 140 | ((IO_PORT_PTR_TO_NUM(port) == 1) ? INT_CHIP(0, 26) : \ |
| 141 | ((IO_PORT_PTR_TO_NUM(port) == 2) ? INT_CHIP(0, 29) : \ |
| 142 | ((IO_PORT_PTR_TO_NUM(port) == 3) ? INT_CHIP(1, 24) : \ |
| 143 | ((IO_PORT_PTR_TO_NUM(port) == 4) ? INT_CHIP(1, 27) : \ |
| 144 | ((IO_PORT_PTR_TO_NUM(port) == 5) ? INT_CHIP(1, 16) : \ |
| 145 | ((IO_PORT_PTR_TO_NUM(port) == 6) ? INT_CHIP(1, 19) : \ |
| 146 | ((IO_PORT_PTR_TO_NUM(port) == 7) ? INT_CHIP(1, 20) : \ |
| 147 | ((IO_PORT_PTR_TO_NUM(port) == 8) ? INT_CHIP(1, 21) : \ |
| 148 | INT_CHIP(1, 15)))))))))) |
| 149 | #define TX_FIFO_INT(port) \ |
| 150 | ((IO_PORT_PTR_TO_NUM(port) == 0) ? INT_CHIP(0, 24) : \ |
| 151 | ((IO_PORT_PTR_TO_NUM(port) == 1) ? INT_CHIP(0, 27) : \ |
| 152 | ((IO_PORT_PTR_TO_NUM(port) == 2) ? INT_CHIP(0, 29) : \ |
| 153 | ((IO_PORT_PTR_TO_NUM(port) == 3) ? INT_CHIP(1, 25) : \ |
| 154 | ((IO_PORT_PTR_TO_NUM(port) == 4) ? INT_CHIP(1, 28) : \ |
| 155 | ((IO_PORT_PTR_TO_NUM(port) == 5) ? INT_CHIP(1, 17) : \ |
| 156 | ((IO_PORT_PTR_TO_NUM(port) == 6) ? INT_CHIP(1, 19) : \ |
| 157 | ((IO_PORT_PTR_TO_NUM(port) == 7) ? INT_CHIP(1, 20) : \ |
| 158 | ((IO_PORT_PTR_TO_NUM(port) == 8) ? INT_CHIP(1, 22) : \ |
| 159 | INT_CHIP(1, 15)))))))))) |
| 160 | #define PORT_OTHER_INT(port) \ |
| 161 | ((IO_PORT_PTR_TO_NUM(port) == 0) ? INT_CHIP(0, 25) : \ |
| 162 | ((IO_PORT_PTR_TO_NUM(port) == 1) ? INT_CHIP(0, 28) : \ |
| 163 | ((IO_PORT_PTR_TO_NUM(port) == 2) ? INT_CHIP(0, 29) : \ |
| 164 | ((IO_PORT_PTR_TO_NUM(port) == 3) ? INT_CHIP(1, 26) : \ |
| 165 | ((IO_PORT_PTR_TO_NUM(port) == 4) ? INT_CHIP(1, 29) : \ |
| 166 | ((IO_PORT_PTR_TO_NUM(port) == 5) ? INT_CHIP(1, 18) : \ |
| 167 | ((IO_PORT_PTR_TO_NUM(port) == 6) ? INT_CHIP(1, 19) : \ |
| 168 | ((IO_PORT_PTR_TO_NUM(port) == 7) ? INT_CHIP(1, 20) : \ |
| 169 | ((IO_PORT_PTR_TO_NUM(port) == 8) ? INT_CHIP(1, 23) : \ |
| 170 | INT_CHIP(1, 15)))))))))) |
| 171 | |
| 172 | /* |
| 173 | * On Chip Peripherals Base. |
| 174 | */ |
| 175 | #define OCP_BASE 0x01000000 |
| 176 | #define OCP_GENERAL 0x000 |
| 177 | #define OCP_TIMERS 0x100 |
| 178 | #define OCP_TRNG 0x200 /* True Random Number Generator Control Reigsters */ |
| 179 | #define OCP_DEBUG 0x300 |
| 180 | #define OCP_SECURITY 0x400 |
| 181 | #define OCP_ICCR 0x500 /* I-Cache Control Registers */ |
| 182 | #define OCP_DCCR 0x600 /* D-Cache Control Registers */ |
| 183 | #define OCP_OCMC 0x700 /* On Chip Memory Control Registers */ |
| 184 | #define OCP_STATISTICS 0x800 /* Statistics Counters */ |
| 185 | #define OCP_MTEST 0x900 /* Memory Test Registers */ |
| 186 | #define OCP_MCFG 0xa00 /* Memory Configuration Registers -- IP7000 only */ |
| 187 | #define OCP_DEBUG_INST 0x000 /* Up to 16M */ |
| 188 | |
| 189 | /* |
| 190 | * General Configuration Registers (PLL) |
| 191 | */ |
| 192 | #define GENERAL_CFG_BASE (OCP_BASE + OCP_GENERAL) |
| 193 | #define GEN_CLK_CORE_CFG 0x00 |
| 194 | #define GEN_CLK_IO_CFG 0x04 |
| 195 | #define GEN_CLK_DDR_CFG 0x08 |
| 196 | #define GEN_CLK_DDRDS_CFG 0x0c |
| 197 | #define GEN_CLK_SLIP_CLR 0x10 |
| 198 | #define GEN_CLK_SLIP_START 0x14 |
| 199 | #define GEN_CLK_SERDES_SEL 0x18 /* IP7000 only */ |
| 200 | #define GEN_CLK_DDR_CFG2 0x1c /* IP7000 only */ |
| 201 | #define GEN_DDR_CAL_CTRL 0x30 /* IP5000 only */ |
| 202 | #define GEN_DDR_CAL_STAT 0x34 /* IP5000 only */ |
| 203 | #define GEN_USB_DFT_CTRL 0x38 /* IP5000 only */ |
| 204 | #define GEN_USB_DFT_STAT 0x3c /* IP5000 only */ |
| 205 | #define GEN_USB_PHY_CFG 0x40 /* IP7000 only */ |
| 206 | #define GEN_USB_PHY_TEST 0x44 /* IP7000 only */ |
| 207 | #define GEN_USB_PHY_STAT 0x48 /* IP7000 only */ |
| 208 | #define GEN_SW_RESET 0x80 |
| 209 | #define GEN_RESET_REASON 0x84 |
| 210 | #define GEN_BOND_CFG 0x88 |
| 211 | #define GEN_IO_PU_CFG 0x8c |
| 212 | #define GEN_MEM_RM_CFG 0x90 |
| 213 | #define GEN_IO_CONFIG 0x94 |
| 214 | |
| 215 | #define GEN_CLK_PLL_SECURITY_BIT_NO 31 |
| 216 | #define GEN_CLK_PLL_SECURITY (1 << GEN_CLK_PLL_SECURITY_BIT_NO) |
| 217 | #define GEN_CLK_PLL_ENSAT (1 << 30) |
| 218 | #define GEN_CLK_PLL_FASTEN (1 << 29) |
| 219 | #define GEN_CLK_PLL_NR(v) (((v) - 1) << 23) |
| 220 | #define GEN_CLK_PLL_NF(v) (((v) - 1) << 11) |
| 221 | #define GEN_CLK_PLL_OD(v) (((v) - 1) << 8) |
| 222 | #define GEN_CLK_PLL_RESET (1 << 7) |
| 223 | #define GEN_CLK_PLL_BYPASS (1 << 6) |
| 224 | #define GEN_CLK_PLL_POWERDOWN (1 << 5) |
| 225 | #define GEN_CLK_PLL_SELECT (1 << 4) |
| 226 | |
| 227 | #define GEN_GET_CLK_PLL_NR(v) ((((v) >> 23) & 0x003f) + 1) |
| 228 | #define GEN_GET_CLK_PLL_NF(v) ((((v) >> 11) & 0x0fff) + 1) |
| 229 | #define GEN_GET_CLK_PLL_OD(v) ((((v) >> 8) & 0x7) + 1) |
| 230 | |
| 231 | |
| 232 | #define RESET_FLAG_DST_MEM_ERROR (1 << 18) |
| 233 | #define RESET_FLAG_SRC1_MEM_ERROR (1 << 17) |
| 234 | #define RESET_FLAG_WRITE_ADDR (1 << 16) |
| 235 | #define RESET_FLAG_DST_SYNC_ERROR (1 << 15) |
| 236 | #define RESET_FLAG_SRC1_SYNC_ERROR (1 << 14) |
| 237 | #define RESET_FLAG_DST_ALGN_ERROR (1 << 13) |
| 238 | #define RESET_FLAG_SRC1_ALGN_ERROR (1 << 12) |
| 239 | #define RESET_FLAG_DST_ADDR_ERROR (1 << 11) |
| 240 | #define RESET_FLAG_SRC1_ADDR_ERROR (1 << 10) |
| 241 | #define RESET_FLAG_ILLEGAL_INST (1 << 9) |
| 242 | #define RESET_FLAG_INST_SYNC_ERROR (1 << 8) |
| 243 | #define RESET_FLAG_INST_ADDR_ERROR (1 << 7) |
| 244 | #define RESET_FLAG_DATA_PORT_ERROR (1 << 6) |
| 245 | #define RESET_FLAG_INST_PORT_ERROR (1 << 5) |
| 246 | #define RESET_FLAG_SW_RESET (1 << 4) |
| 247 | #define RESET_FLAG_DEBUG (1 << 3) |
| 248 | #define RESET_FLAG_WATCHDOG (1 << 2) |
| 249 | #define RESET_FLAG_POWER_ON (1 << 1) |
| 250 | #define RESET_FLAG_EXTERNAL (1 << 0) |
| 251 | |
| 252 | /* |
| 253 | * Timer block |
| 254 | */ |
| 255 | #define TIMER_BASE (OCP_BASE + OCP_TIMERS) |
| 256 | #define TIMER_MPTVAL 0x00 |
| 257 | #define TIMER_RTCOM 0x04 |
| 258 | #define TIMER_TKEY 0x08 |
| 259 | #define TIMER_WDCOM 0x0c |
| 260 | #define TIMER_WDCFG 0x10 |
| 261 | #define TIMER_SYSVAL 0x14 |
| 262 | #define TIMER_SYSCOM(tmr) (0x18 + (tmr) * 4) |
| 263 | #define TIMER_TRN_CFG 0x100 |
| 264 | #define TIMER_TRN 0x104 |
| 265 | |
| 266 | #define TIMER_COUNT 10 |
| 267 | #define TIMER_INT(tmr) INT_CHIP(1, (tmr)) |
| 268 | #define TIMER_TKEYVAL 0xa1b2c3d4 |
| 269 | #define TIMER_WATCHDOG_DISABLE 0x4d3c2b1a |
| 270 | #define TIMER_TRN_CFG_ENABLE_OSC 0x00000007 |
| 271 | |
| 272 | #ifndef __ASSEMBLY__ |
| 273 | /* |
| 274 | * ubicom32_io_timer |
| 275 | */ |
| 276 | struct ubicom32_io_timer { |
| 277 | volatile u32_t mptval; |
| 278 | volatile u32_t rtcom; |
| 279 | volatile u32_t tkey; |
| 280 | volatile u32_t wdcom; |
| 281 | volatile u32_t wdcfg; |
| 282 | volatile u32_t sysval; |
| 283 | volatile u32_t syscom[TIMER_COUNT]; |
| 284 | volatile u32_t reserved[64 - 6 - TIMER_COUNT]; // skip all the way to OCP-TRNG section |
| 285 | volatile u32_t rsgcfg; |
| 286 | volatile u32_t trn; |
| 287 | }; |
| 288 | |
| 289 | #define UBICOM32_IO_TIMER ((struct ubicom32_io_timer *)TIMER_BASE) |
| 290 | #endif |
| 291 | |
| 292 | #define UBICOM32_VECTOR_TO_TIMER_INDEX(vector) (vector - TIMER_INT(0)) |
| 293 | |
| 294 | /* |
| 295 | * OCP-Debug Module (Mailbox) |
| 296 | */ |
| 297 | #define ISD_MAILBOX_BASE (OCP_BASE + OCP_DEBUG) |
| 298 | #define ISD_MAILBOX_IN 0x00 |
| 299 | #define ISD_MAILBOX_OUT 0x04 |
| 300 | #define ISD_MAILBOX_STATUS 0x08 |
| 301 | |
| 302 | #define ISD_MAILBOX_INT INT_CHIP(1, 30) |
| 303 | |
| 304 | #define ISD_MAILBOX_STATUS_IN_FULL (1 << 31) |
| 305 | #define ISD_MAILBOX_STATUS_IN_EMPTY (1 << 30) |
| 306 | #define ISD_MAILBOX_STATUS_OUT_FULL (1 << 29) |
| 307 | #define ISD_MAILBOX_STATUS_OUT_EMPTY (1 << 28) |
| 308 | |
| 309 | /* |
| 310 | * OCP-Security |
| 311 | */ |
| 312 | #define SECURITY_BASE (OCP_BASE + OCP_SECURITY) |
| 313 | #define SECURITY_BASE_EFFECTIVE_ADDRESS (SECURITY_BASE >> 7) // To load the base address in a single instruction |
| 314 | #define SECURITY_CTRL 0x00 |
| 315 | #define SECURITY_CTRL_BYTE_OFFSET(x) ((x) << 16) |
| 316 | #define SECURITY_CTRL_KEY_SIZE(x) ((x) << 8) |
| 317 | #define SECURITY_CTRL_HASH_ALG_NONE (0 << 4) |
| 318 | #define SECURITY_CTRL_HASH_ALG_MD5 (1 << 4) |
| 319 | #define SECURITY_CTRL_HASH_ALG_SHA1 (2 << 4) |
| 320 | #define SECURITY_CTRL_CBC (1 << 3) |
| 321 | #define SECURITY_CTRL_CIPHER_ALG_AES (0 << 1) |
| 322 | #define SECURITY_CTRL_CIPHER_ALG_NONE (1 << 1) |
| 323 | #define SECURITY_CTRL_CIPHER_ALG_DES (2 << 1) |
| 324 | #define SECURITY_CTRL_CIPHER_ALG_3DES (3 << 1) |
| 325 | #define SECURITY_CTRL_ENCIPHER (1 << 0) |
| 326 | #define SECURITY_CTRL_DECIPHER (0 << 0) |
| 327 | #define SECURITY_STAT 0x04 |
| 328 | #define SECURITY_STAT_BUSY (1 << 0) |
| 329 | #define SECURITY_KEY_VALUE(x) (0x10 + (x) * 4) |
| 330 | #define SECURITY_KEY_IN(x) (0x30 + (x) * 4) |
| 331 | #define SECURITY_KEY_OUT(x) (0x50 + (x) * 4) |
| 332 | #define SECURITY_KEY_HASH(x) (0x70 + (x) * 4) |
| 333 | |
| 334 | /* |
| 335 | * OCP-ICCR |
| 336 | */ |
| 337 | #define ICCR_BASE (OCP_BASE + OCP_ICCR) |
| 338 | #define ICACHE_TOTAL_SIZE 16384 /* in bytes */ |
| 339 | |
| 340 | /* |
| 341 | * OCP-DCCR |
| 342 | */ |
| 343 | #define DCCR_BASE (OCP_BASE + OCP_DCCR) |
| 344 | #if defined(IP5000) || defined(IP5000_REV2) |
| 345 | #define DCACHE_TOTAL_SIZE 8192 /* in bytes */ |
| 346 | #elif defined(IP7000) || defined(IP7000_REV2) |
| 347 | #define DCACHE_TOTAL_SIZE 16384 /* in bytes */ |
| 348 | #endif |
| 349 | |
| 350 | #if defined(IP5000) || defined(IP5000_REV2) || defined(IP7000) || defined(IP7000_REV2) |
| 351 | #define DCACHE_WRITE_QUEUE_LENGTH 6 |
| 352 | #else |
| 353 | #error "Unknown IP5K silicon" |
| 354 | #endif |
| 355 | |
| 356 | #define CACHE_LINE_SIZE 32 /* in bytes */ |
| 357 | |
| 358 | #define CCR_ADDR 0x00 |
| 359 | #define CCR_RDD 0x04 |
| 360 | #define CCR_WRD 0x08 |
| 361 | #define CCR_STAT 0x0c |
| 362 | #define CCR_CTRL 0x10 |
| 363 | |
| 364 | #define CCR_STAT_MCBE 0 |
| 365 | #define CCR_STAT_WIDEL 1 /* D-cache only */ |
| 366 | |
| 367 | #define CCR_CTRL_DONE 0 |
| 368 | #define CCR_CTRL_RESET 2 |
| 369 | #define CCR_CTRL_VALID 3 |
| 370 | #define CCR_CTRL_RD_DATA (1 << 4) |
| 371 | #define CCR_CTRL_RD_TAG (2 << 4) |
| 372 | #define CCR_CTRL_WR_DATA (3 << 4) |
| 373 | #define CCR_CTRL_WR_TAG (4 << 4) |
| 374 | #define CCR_CTRL_INV_INDEX (5 << 4) |
| 375 | #define CCR_CTRL_INV_ADDR (6 << 4) |
| 376 | #define CCR_CTRL_FLUSH_INDEX (7 << 4) /* D-cache only */ |
| 377 | #define CCR_CTRL_FLUSH_INV_INDEX (8 << 4) /* D-cache only */ |
| 378 | #define CCR_CTRL_FLUSH_ADDR (9 << 4) /* D-cache only */ |
| 379 | #define CCR_CTRL_FLUSH_INV_ADDR (10 << 4) /* D-cache only */ |
| 380 | |
| 381 | /* |
| 382 | * OCP-OCMC |
| 383 | */ |
| 384 | #define OCMC_BASE (OCP_BASE + OCP_OCMC) |
| 385 | #define OCMC_BANK_MASK 0x00 |
| 386 | #define OCMC_BIST_CNTL 0x04 /* IP5000 only */ |
| 387 | #define OCMC_BIST_STAT 0x08 /* IP5000 only */ |
| 388 | |
| 389 | #define OCMC_BANK_PROG(n) ((1<<(n))-1) |
| 390 | |
| 391 | #define OCMC_BIST_WRCK (1 << 7) |
| 392 | #define OCMC_BIST_RESET (1 << 5) |
| 393 | #define OCMC_BIST_SMART (1 << 4) |
| 394 | #define OCMC_BIST_RUN (1 << 3) |
| 395 | #define OCMC_BIST_REPAIR (1 << 2) |
| 396 | |
| 397 | #define OCMC_BIST_READY (1 << 3) |
| 398 | #define OCMC_BIST_FAIL (1 << 2) |
| 399 | |
| 400 | /* |
| 401 | * OCP-STATISTICS |
| 402 | */ |
| 403 | #define STATISTICS_BASE (OCP_BASE + OCP_STATISTICS) |
| 404 | #define STAT_COUNTER_CTRL(n) ((n)*8) |
| 405 | #define STAT_COUNTER(n) ((n)*8 + 4) |
| 406 | |
| 407 | #define STAT_EVENT_MP_INST 0 |
| 408 | #define STAT_EVENT_OCM_ACCESS 4 |
| 409 | #define STAT_EVENT_OCM_REQ 5 |
| 410 | #define STAT_EVENT_IC_REQ_INVAL 13 |
| 411 | #define STAT_EVENT_IC_MISS_INVAL 14 |
| 412 | #define STAT_EVENT_IC_REQ_INVAL_NACK 15 |
| 413 | #define STAT_EVENT_IC_REQ_VAL 16 |
| 414 | #define STAT_EVENT_IC_MISS_VAL 17 |
| 415 | #define STAT_EVENT_IC_REQ_VAL_NACK 18 |
| 416 | #define STAT_EVENT_IC_MISS_Q 19 |
| 417 | #define STAT_EVENT_DC_RD_REQ 20 |
| 418 | #define STAT_EVENT_DC_RD_MISS 21 |
| 419 | #define STAT_EVENT_DC_WR_REQ 22 |
| 420 | #define STAT_EVENT_DC_WR_MISS 23 |
| 421 | #define STAT_EVENT_DC_MISS_Q 24 |
| 422 | #define STAT_EVENT_DC_WB_FULL 25 |
| 423 | #define STAT_EVENT_DC_REQ_NACK 26 |
| 424 | #define STAT_EVENT_DC_CORE_REQ 27 |
| 425 | #define STAT_EVENT_DC_MISS 28 |
| 426 | #define STAT_EVENT_DC_EVICT 29 |
| 427 | #define STAT_EVENT_TRUE 30 |
| 428 | #define STAT_EVENT_FALSE 31 |
| 429 | |
| 430 | /* |
| 431 | * OCP_MTEST |
| 432 | */ |
| 433 | #define MTEST_BASE (OCP_BASE + OCP_MTEST) |
| 434 | #define MTEST_ADDR 0x00 |
| 435 | #define MTEST_WR 0x04 |
| 436 | #define MTEST_RD 0x08 |
| 437 | #define MTEST_CTRL 0x0c |
| 438 | |
| 439 | /* |
| 440 | * OCP_MCFG (IP7000 only) |
| 441 | */ |
| 442 | #define MCFG_BASE (OCP_BASE + OCP_MCFG) |
| 443 | #define MCFG_CTRL 0x00 |
| 444 | #define MCFG_WCFG 0x04 |
| 445 | #define MCFG_RCFG 0x08 |
| 446 | |
| 447 | /* |
| 448 | * Port registers |
| 449 | */ |
| 450 | #define IO_BASE 0x02000000 |
| 451 | #define RA (IO_BASE + 0x00000000) |
| 452 | #define RB (IO_BASE + 0x00001000) |
| 453 | #define RC (IO_BASE + 0x00002000) |
| 454 | #define RD (IO_BASE + 0x00003000) |
| 455 | #define RE (IO_BASE + 0x00004000) |
| 456 | #define RF (IO_BASE + 0x00005000) |
| 457 | #define RG (IO_BASE + 0x00006000) |
| 458 | #define RH (IO_BASE + 0x00007000) |
| 459 | #define RI (IO_BASE + 0x00008000) |
| 460 | #define RJ (IO_BASE + 0x00009000) |
| 461 | #define RLATCH (IO_BASE + 0x00ff0000) // For latched output only |
| 462 | #define IO_PORT_BR_OFFSET 0x00000800 |
| 463 | |
| 464 | /* |
| 465 | * General I/O Register Map (per port) |
| 466 | */ |
| 467 | #define IO_FUNC 0x00 |
| 468 | #define IO_GPIO_CTL 0x04 |
| 469 | #define IO_GPIO_OUT 0x08 |
| 470 | #define IO_GPIO_IN 0x0C |
| 471 | #define IO_INT_STATUS 0x10 |
| 472 | #define IO_INT_MASK 0x14 |
| 473 | #define IO_INT_SET 0x18 |
| 474 | #define IO_INT_CLR 0x1C |
| 475 | #define IO_TX_FIFO 0x20 |
| 476 | #define IO_TX_FIFO_HI 0x24 |
| 477 | #define IO_RX_FIFO 0x28 |
| 478 | #define IO_RX_FIFO_HI 0x2c |
| 479 | #define IO_CTL0 0x30 |
| 480 | #define IO_CTL1 0x34 |
| 481 | #define IO_CTL2 0x38 |
| 482 | #define IO_STATUS0 0x3c |
| 483 | #define IO_STATUS1 0x40 |
| 484 | #define IO_STATUS2 0x44 |
| 485 | #define IO_FIFO_WATER 0x48 |
| 486 | #define IO_FIFO_LEVEL 0x4c |
| 487 | #define IO_GPIO_MASK 0x50 |
| 488 | |
| 489 | #define IO_FUNC_FUNCTION_RESET(func) ((1 << ((func) - 1)) << 4) /* Function 0 doesn't need reset */ |
| 490 | #define IO_FUNC_RX_FIFO (1 << 3) |
| 491 | #define IO_FUNC_SELECT(func) ((func) << 0) |
| 492 | |
| 493 | /* |
| 494 | * External interrupt pins. |
| 495 | */ |
| 496 | #define EXT_INT_IO_BIT(pin) ((pin) + 5) // Interrupt pin number -> I/O INT bit |
| 497 | #define EXT_INT_RISING_EDGE(pin) (0x2 << (2*(pin) + 7)) |
| 498 | #define EXT_INT_FALLING_EDGE(pin) (0x1 << (2*(pin) + 7)) |
| 499 | |
| 500 | /* |
| 501 | * Flash |
| 502 | */ |
| 503 | #define IO_XFL_BASE RA |
| 504 | |
| 505 | #define IO_XFL_INT_START (1 << 16) |
| 506 | #define IO_XFL_INT_ERR (1 << 8) |
| 507 | #define IO_XFL_INT_DONE (1 << 0) |
| 508 | |
| 509 | #define IO_XFL_CTL0_MASK (0xffe07fff) |
| 510 | #define IO_XFL_CTL0_RD_CMD(cmd) (((cmd) & 0xff) << 24) |
| 511 | #define IO_XFL_CTL0_RD_DUMMY(n) (((n) & 0x7) << 21) |
| 512 | #define IO_XFL_CTL0_CLK_WIDTH(core_cycles) ((((core_cycles) + 1) & 0x7e) << 8) /* must be even number */ |
| 513 | #define IO_XFL_CTL0_CE_WAIT(spi_cycles) (((spi_cycles) & 0x3f) << 2) |
| 514 | #define IO_XFL_CTL0_MCB_LOCK (1 << 1) |
| 515 | #define IO_XFL_CTL0_ENABLE (1 << 0) |
| 516 | #define IO_XFL_CTL0_FAST_VALUE(div, wait) (IO_XFL_CTL0_RD_CMD(0xb) | IO_XFL_CTL0_RD_DUMMY(1) | IO_XFL_CTL0_CLK_WIDTH(div) | IO_XFL_CTL0_CE_WAIT(wait) | IO_XFL_CTL0_ENABLE) |
| 517 | #define IO_XFL_CTL0_VALUE(div, wait) (IO_XFL_CTL0_RD_CMD(3) | IO_XFL_CTL0_CLK_WIDTH(div) | IO_XFL_CTL0_CE_WAIT(wait) | IO_XFL_CTL0_ENABLE) |
| 518 | |
| 519 | #define IO_XFL_CTL1_MASK (0xc0003fff) |
| 520 | #define IO_XFL_CTL1_FC_INST(inst) (((inst) & 0x3) << 30) |
| 521 | #define IO_XFL_CTL1_FC_DATA(n) (((n) & 0x3ff) << 4) |
| 522 | #define IO_XFL_CTL1_FC_DUMMY(n) (((n) & 0x7) << 1) |
| 523 | #define IO_XFL_CTL1_FC_ADDR (1 << 0) |
| 524 | |
| 525 | #define IO_XFL_CTL2_FC_CMD(cmd) (((cmd) & 0xff) << 24) |
| 526 | #define IO_XFL_CTL2_FC_ADDR(addr) ((addr) & 0x00ffffff) /* Only up to 24 bits */ |
| 527 | |
| 528 | #define IO_XFL_STATUS0_MCB_ACTIVE (1 << 0) |
| 529 | #define IO_XFL_STATUS0_IOPCS_ACTIVE (1 << 1) |
| 530 | |
| 531 | /* |
| 532 | * SDRAM |
| 533 | */ |
| 534 | #define IO_SDRAM_DATA_BASE RG |
| 535 | #define IO_SDRAM_CNTL_BASE RH |
| 536 | |
| 537 | #define IO_SDRAM_CTRL0_EN_REF (1 << 0) |
| 538 | |
| 539 | /* |
| 540 | * Port function code (common fucntion codes for all I/O ports) |
| 541 | */ |
| 542 | #define IO_PORTX_FUNC_GPIO 0x00 |
| 543 | #define IO_PORTX_FUNC_XFL 0x01 |
| 544 | #define IO_PORTX_FUNC_PCI 0x01 |
| 545 | #define IO_PORTX_FUNC_SERDES 0x01 |
| 546 | #define IO_PORTX_FUNC_GMII 0x01 |
| 547 | #define IO_PORTX_FUNC_DDR 0x01 |
| 548 | #define IO_PORTX_FUNC_PCIX 0x01 |
| 549 | #define IO_PORTX_FUNC_USB2_0 0x01 |
| 550 | #define IO_PORTX_FUNC_GPIO_INT_CLK 0x02 |
| 551 | #define IO_PORTX_FUNC_PLIO 0x02 |
| 552 | #define IO_PORTX_FUNC_GPIO_INT 0x03 |
| 553 | #define IO_PORTX_FUNC_MII 0x03 |
| 554 | |
| 555 | /* |
| 556 | * Port 0 |
| 557 | */ |
| 558 | #define IO_PORT0_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 559 | #define IO_PORT0_FUNC_XFL_INT_CLK IO_PORTX_FUNC_XFL // Default mode after reset |
| 560 | #define IO_PORT0_FUNC_GPIO_INT_CLK IO_PORTX_FUNC_GPIO_INT_CLK |
| 561 | #define IO_PORT0_FUNC_GPIO_INT IO_PORTX_FUNC_GPIO_INT |
| 562 | |
| 563 | /* |
| 564 | * Port 1 |
| 565 | */ |
| 566 | #define IO_PORT1_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 567 | #define IO_PORT1_FUNC_PCI IO_PORTX_FUNC_PCI // PCI control |
| 568 | #define IO_PORT1_FUNC_MII IO_PORTX_FUNC_MII // port 4 MII extension |
| 569 | |
| 570 | /* |
| 571 | * Port 2 |
| 572 | */ |
| 573 | #define IO_PORT2_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 574 | #define IO_PORT2_FUNC_PCI IO_PORTX_FUNC_PCI // PCI data I/O |
| 575 | #define IO_PORT2_FUNC_PLIO IO_PORTX_FUNC_PLIO // Extended LM |
| 576 | |
| 577 | /* |
| 578 | * Port 3 |
| 579 | */ |
| 580 | #define IO_PORT3_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 581 | #define IO_PORT3_FUNC_SERDES IO_PORTX_FUNC_SERDES |
| 582 | #define IO_PORT3_FUNC_PLIO IO_PORTX_FUNC_PLIO |
| 583 | |
| 584 | /* |
| 585 | * Port 4 |
| 586 | */ |
| 587 | #define IO_PORT4_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 588 | #define IO_PORT4_FUNC_SERDES IO_PORTX_FUNC_SERDES |
| 589 | #define IO_PORT4_FUNC_PLIO IO_PORTX_FUNC_PLIO // Extended LM |
| 590 | #define IO_PORT4_FUNC_MII IO_PORTX_FUNC_MII |
| 591 | |
| 592 | /* |
| 593 | * Port 5 |
| 594 | */ |
| 595 | #define IO_PORT5_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 596 | #define IO_PORT5_FUNC_GMII IO_PORTX_FUNC_GMII |
| 597 | |
| 598 | /* |
| 599 | * Port 6 |
| 600 | */ |
| 601 | #define IO_PORT6_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 602 | #define IO_PORT6_FUNC_DDR IO_PORTX_FUNC_DDR |
| 603 | |
| 604 | /* |
| 605 | * Port 7 |
| 606 | */ |
| 607 | #define IO_PORT7_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 608 | #define IO_PORT7_FUNC_DDR IO_PORTX_FUNC_DDR |
| 609 | |
| 610 | /* |
| 611 | * Port 8 |
| 612 | */ |
| 613 | #define IO_PORT8_FUNC_GPIO IO_PORTX_FUNC_GPIO |
| 614 | #define IO_PORT8_FUNC_PCIX IO_PORTX_FUNC_PCIX |
| 615 | #define IO_PORT8_FUNC_PLIO IO_PORTX_FUNC_PLIO // Extended LM |
| 616 | #define IO_PORT8_FUNC_MII IO_PORTX_FUNC_MII // port 4 MII extension |
| 617 | |
| 618 | /* |
| 619 | * Port 9 |
| 620 | */ |
| 621 | #define IO_PORT9_FUNC_USB2_0 IO_PORTX_FUNC_USB2_0 |
| 622 | |
| 623 | /* |
| 624 | * FIFO |
| 625 | */ |
| 626 | #define IO_PORTX_INT_FIFO_TX_RESET (1 << 31) |
| 627 | #define IO_PORTX_INT_FIFO_RX_RESET (1 << 30) |
| 628 | #define IO_PORTX_INT_FIFO_TX_UF (1 << 15) |
| 629 | #define IO_PORTX_INT_FIFO_TX_WM (1 << 14) |
| 630 | #define IO_PORTX_INT_FIFO_RX_OF (1 << 13) |
| 631 | #define IO_PORTX_INT_FIFO_RX_WM (1 << 12) |
| 632 | |
| 633 | #define IO_PORTX_FUNC_FIFO_TX_WM(n) ((n) << 16) |
| 634 | #define IO_PORTX_FUNC_FIFO_RX_WM(n) ((n) << 0) |
| 635 | |
| 636 | /* |
| 637 | * MII |
| 638 | */ |
| 639 | #define IO_PORTX_INT_MII_TX_ERR_SEND (1 << 18) |
| 640 | #define IO_PORTX_INT_MII_TX_HALT (1 << 17) |
| 641 | #define IO_PORTX_INT_MII_TX_START (1 << 16) |
| 642 | #define IO_PORTX_INT_MII_THRESHOLD (1 << 8) |
| 643 | #define IO_PORTX_INT_MII_RX_EOP (1 << 7) |
| 644 | #define IO_PORTX_INT_MII_RX_SFD (1 << 6) |
| 645 | #define IO_PORTX_INT_MII_RX_ERR (1 << 5) |
| 646 | #define IO_PORTX_INT_MII_TX_EOP (1 << 4) |
| 647 | #define IO_PORTX_INT_MII_COL (1 << 3) |
| 648 | #define IO_PORTX_INT_MII_CRS (1 << 2) |
| 649 | #define IO_PORTX_INT_MII_ODD_NIB_ERR (1 << 1) |
| 650 | #define IO_PORTX_INT_MII_FALSE_CARRIER (1 << 0) |
| 651 | |
| 652 | /* |
| 653 | * SerDes |
| 654 | */ |
| 655 | #define IO_PORTX_INT_SERDES_TXBUF_VALID (1 << 16) |
| 656 | #define IO_PORTX_INT_SERDES_RXERR (1 << 7) |
| 657 | #define IO_PORTX_INT_SERDES_RXEOP (1 << 6) |
| 658 | #define IO_PORTX_INT_SERDES_SYND (1 << 5) |
| 659 | #define IO_PORTX_INT_SERDES_TXBE (1 << 4) |
| 660 | #define IO_PORTX_INT_SERDES_TXEOP (1 << 3) |
| 661 | #define IO_PORTX_INT_SERDES_SXLP (1 << 2) |
| 662 | #define IO_PORTX_INT_SERDES_RXBF (1 << 1) |
| 663 | #define IO_PORTX_INT_SERDES_RXCRS (1 << 0) |
| 664 | |
| 665 | #ifndef __ASSEMBLY__ |
| 666 | struct ubicom32_io_port { |
| 667 | volatile u32_t function; |
| 668 | volatile u32_t gpio_ctl; |
| 669 | volatile u32_t gpio_out; |
| 670 | volatile u32_t gpio_in; |
| 671 | volatile u32_t int_status; |
| 672 | volatile u32_t int_mask; |
| 673 | volatile u32_t int_set; |
| 674 | volatile u32_t int_clr; |
| 675 | volatile u32_t tx_fifo; |
| 676 | volatile u32_t tx_fifo_hi; |
| 677 | volatile u32_t rx_fifo; |
| 678 | volatile u32_t rx_fifo_hi; |
| 679 | volatile u32_t ctl0; |
| 680 | volatile u32_t ctl1; |
| 681 | volatile u32_t ctl2; |
| 682 | volatile u32_t status0; |
| 683 | volatile u32_t status1; |
| 684 | volatile u32_t status2; |
| 685 | volatile u32_t fifo_watermark; |
| 686 | volatile u32_t fifo_level; |
| 687 | volatile u32_t gpio_mask; |
| 688 | }; |
| 689 | |
| 690 | #define UBICOM32_IO_PORT(port) ((struct ubicom32_io_port *)((port))) |
| 691 | #endif |
| 692 | |
| 693 | #ifndef __ASSEMBLY__ |
| 694 | /* |
| 695 | * ubicom32_set_interrupt() |
| 696 | */ |
| 697 | extern inline void ubicom32_set_interrupt(u8_t interrupt) |
| 698 | { |
| 699 | u32_t ibit = INT_BIT_MASK(interrupt); |
| 700 | |
| 701 | if (INT_REG(interrupt) == INT_REG(INT_CHIP(0, 0))) { |
| 702 | asm volatile ( |
| 703 | "move.4 "D(INT_SET(INT_CHIP(0, 0)))", %0\n\t" |
| 704 | : |
| 705 | : "r" (ibit) |
| 706 | ); |
| 707 | |
| 708 | return; |
| 709 | } |
| 710 | |
| 711 | asm volatile ( |
| 712 | "move.4 "D(INT_SET(INT_CHIP(1, 0)))", %0\n\t" |
| 713 | : |
| 714 | : "r" (ibit) |
| 715 | ); |
| 716 | } |
| 717 | |
| 718 | /* |
| 719 | * ubicom32_clear_interrupt() |
| 720 | */ |
| 721 | extern inline void ubicom32_clear_interrupt(u8_t interrupt) |
| 722 | { |
| 723 | u32_t ibit = INT_BIT_MASK(interrupt); |
| 724 | |
| 725 | if (INT_REG(interrupt) == INT_REG(INT_CHIP(0, 0))) { |
| 726 | asm volatile ( |
| 727 | "move.4 "D(INT_CLR(INT_CHIP(0, 0)))", %0\n\t" |
| 728 | : |
| 729 | : "r" (ibit) |
| 730 | ); |
| 731 | |
| 732 | return; |
| 733 | } |
| 734 | |
| 735 | asm volatile ( |
| 736 | "move.4 "D(INT_CLR(INT_CHIP(1, 0)))", %0\n\t" |
| 737 | : |
| 738 | : "r" (ibit) |
| 739 | ); |
| 740 | } |
| 741 | |
| 742 | /* |
| 743 | * ubicom32_enable_interrupt() |
| 744 | */ |
| 745 | extern inline void ubicom32_enable_interrupt(u8_t interrupt) |
| 746 | { |
| 747 | u32_t ibit = INT_BIT_MASK(interrupt); |
| 748 | |
| 749 | if (INT_REG(interrupt) == INT_REG(INT_CHIP(0, 0))) { |
| 750 | asm volatile ( |
| 751 | "or.4 "D(INT_MASK(INT_CHIP(0, 0)))", "D(INT_MASK(INT_CHIP(0, 0)))", %0\n\t" |
| 752 | : |
| 753 | : "d" (ibit) |
| 754 | ); |
| 755 | |
| 756 | return; |
| 757 | } |
| 758 | |
| 759 | asm volatile ( |
| 760 | "or.4 "D(INT_MASK(INT_CHIP(1, 0)))", "D(INT_MASK(INT_CHIP(1, 0)))", %0\n\t" |
| 761 | : |
| 762 | : "d" (ibit) |
| 763 | ); |
| 764 | } |
| 765 | |
| 766 | /* |
| 767 | * ubicom32_disable_interrupt() |
| 768 | */ |
| 769 | extern inline void ubicom32_disable_interrupt(u8_t interrupt) |
| 770 | { |
| 771 | u32_t ibit = ~INT_BIT_MASK(interrupt); |
| 772 | |
| 773 | if (INT_REG(interrupt) == INT_REG(INT_CHIP(0, 0))) { |
| 774 | asm volatile ( |
| 775 | "and.4 "D(INT_MASK(INT_CHIP(0, 0)))", "D(INT_MASK(INT_CHIP(0, 0)))", %0\n\t" |
| 776 | : |
| 777 | : "d" (ibit) |
| 778 | ); |
| 779 | |
| 780 | return; |
| 781 | } |
| 782 | |
| 783 | asm volatile ( |
| 784 | "and.4 "D(INT_MASK(INT_CHIP(1, 0)))", "D(INT_MASK(INT_CHIP(1, 0)))", %0\n\t" |
| 785 | : |
| 786 | : "d" (ibit) |
| 787 | ); |
| 788 | } |
| 789 | |
| 790 | /* |
| 791 | * ubicom32_enable_global_interrupts() |
| 792 | */ |
| 793 | extern inline void ubicom32_enable_global_interrupts(void) |
| 794 | { |
| 795 | asm volatile( |
| 796 | "bset GLOBAL_CTRL, GLOBAL_CTRL, #%bit("D(GLOBAL_CTRL_INT_EN)")" |
| 797 | ); |
| 798 | } |
| 799 | |
| 800 | /* |
| 801 | * ubicom32_disable_global_interrupts() |
| 802 | */ |
| 803 | extern inline void ubicom32_disable_global_interrupts(void) |
| 804 | { |
| 805 | asm volatile( |
| 806 | "bclr GLOBAL_CTRL, GLOBAL_CTRL, #%bit("D(GLOBAL_CTRL_INT_EN)")" |
| 807 | ); |
| 808 | } |
| 809 | |
| 810 | /* |
| 811 | * ubicom32_get_reset_reason() |
| 812 | */ |
| 813 | extern inline u32_t ubicom32_get_reset_reason(void) |
| 814 | { |
| 815 | return *(u32_t *)(GENERAL_CFG_BASE + GEN_RESET_REASON); |
| 816 | } |
| 817 | |
| 818 | /* |
| 819 | * ubicom32_read_reg() |
| 820 | */ |
| 821 | extern inline u32_t ubicom32_read_reg(volatile void *reg) |
| 822 | { |
| 823 | u32_t v; |
| 824 | asm volatile ( |
| 825 | "move.4 %[dest], %[src] \n\t" |
| 826 | : [dest] "=r" (v) |
| 827 | : [src] "m" (*(u32_t *)reg) |
| 828 | ); |
| 829 | return v; |
| 830 | } |
| 831 | |
| 832 | /* |
| 833 | * ubicom32_write_reg() |
| 834 | */ |
| 835 | extern inline void ubicom32_write_reg(volatile void *reg, u32_t v) |
| 836 | { |
| 837 | asm volatile ( |
| 838 | "move.4 %[dest], %[src] \n\t" |
| 839 | : |
| 840 | : [src] "r" (v), [dest] "m" (*(u32_t *)reg) |
| 841 | ); |
| 842 | } |
| 843 | |
| 844 | #endif /* __ASSEMBLY__ */ |
| 845 | #endif /* _ASM_UBICOM32_IP5000_H */ |
| 846 | |
