| 1 | /* |
| 2 | * arch/ubicom32/mach-common/switch-bcm539x-reg.h |
| 3 | * Broadcom switch definitions for Ubicom32 architecture. |
| 4 | * |
| 5 | * (C) Copyright 2009, Ubicom, Inc. |
| 6 | * |
| 7 | * This file is part of the Ubicom32 Linux Kernel Port. |
| 8 | * |
| 9 | * The Ubicom32 Linux Kernel Port is free software: you can redistribute |
| 10 | * it and/or modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation, either version 2 of the |
| 12 | * License, or (at your option) any later version. |
| 13 | * |
| 14 | * The Ubicom32 Linux Kernel Port is distributed in the hope that it |
| 15 | * will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 16 | * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 17 | * the GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with the Ubicom32 Linux Kernel Port. If not, |
| 21 | * see <http://www.gnu.org/licenses/>. |
| 22 | * |
| 23 | * Ubicom32 implementation derived from (with many thanks): |
| 24 | * arch/m68knommu |
| 25 | * arch/blackfin |
| 26 | * arch/parisc |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * Broadcom 53xx RoboSwitch device driver. |
| 31 | * |
| 32 | * Copyright 2007, Broadcom Corporation |
| 33 | * All Rights Reserved. |
| 34 | * |
| 35 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 36 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 37 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 38 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 39 | * |
| 40 | * $Id$ |
| 41 | */ |
| 42 | |
| 43 | #ifndef _SWITCH_BCM539X_REG_H_ |
| 44 | #define _SWITCH_BCM539X_REG_H_ |
| 45 | |
| 46 | #define BCM539X_CMD_READ 0x60 |
| 47 | #define BCM539X_CMD_WRITE 0x61 |
| 48 | |
| 49 | #define BCM539X_GLOBAL_SPI_DATA0 0xf0 |
| 50 | |
| 51 | #define BCM539X_GLOBAL_SPI_STATUS 0xfe |
| 52 | #define BCM539X_GLOBAL_SPI_ST_SPIF (1<<7) |
| 53 | #define BCM539X_GLOBAL_SPI_ST_RACK (1<<5) |
| 54 | |
| 55 | #define BCM539X_GLOBAL_PAGE 0xff |
| 56 | |
| 57 | #define PAGE_PORT_TC 0x00 // Port Traffic Control Register |
| 58 | |
| 59 | #define PAGE_QOS_CTL 0x30 // QoS Global Control Register |
| 60 | #define PAGE_QOS_TAG 0x34 // Default IEEE 802.1Q TAG Register |
| 61 | |
| 62 | #define PAGE_MII_CTL_PORT0 0x10 // Internal PHY MII Register |
| 63 | #define PAGE_MII_CTL_PORT1 0x11 |
| 64 | #define PAGE_MII_CTL_PORT2 0x12 |
| 65 | #define PAGE_MII_CTL_PORT3 0x13 |
| 66 | #define PAGE_MII_CTL_PORT4 0x14 |
| 67 | |
| 68 | #define PAGE_STATUS 0x01 // Status Register Page |
| 69 | #define PAGE_RATE_CONTROL 0x41 // Broadcast Storm Suppression Register |
| 70 | |
| 71 | #define REG_GRATE_CONTROL 0x00 |
| 72 | |
| 73 | #define REG_LED_POWER 0x12 |
| 74 | |
| 75 | // Ingress Rate Control |
| 76 | #define REG_IRATE_CONTROLP0 0x10 |
| 77 | #define REG_IRATE_CONTROLP1 0x14 |
| 78 | #define REG_IRATE_CONTROLP2 0x18 |
| 79 | #define REG_IRATE_CONTROLP3 0x1C |
| 80 | #define REG_IRATE_CONTROLP4 0x20 |
| 81 | #define REG_IRATE_CONTROLP7 0x2C |
| 82 | #define REG_IRATE_CONTROLPI 0x30 |
| 83 | |
| 84 | // Egress Rate Control |
| 85 | #define REG_ERATE_CONTROLP0 0x80 |
| 86 | #define REG_ERATE_CONTROLP1 0x82 |
| 87 | #define REG_ERATE_CONTROLP2 0x84 |
| 88 | #define REG_ERATE_CONTROLP3 0x86 |
| 89 | #define REG_ERATE_CONTROLP4 0x88 |
| 90 | #define REG_ERATE_CONTROLP5 0x8A |
| 91 | #define REG_ERATE_CONTROLP6 0x8C |
| 92 | #define REG_ERATE_CONTROLP7 0x8E |
| 93 | #define REG_ERATE_CONTROLPI 0x90 |
| 94 | |
| 95 | #define REG_LINK_STATUS 0x00 |
| 96 | |
| 97 | #define REG_TC_PORT0 0x00 |
| 98 | #define REG_TC_PORT1 0x01 |
| 99 | #define REG_TC_PORT2 0x02 |
| 100 | #define REG_TC_PORT3 0x03 |
| 101 | #define REG_TC_PORT4 0x04 |
| 102 | #define REG_TC_PORT5 0x05 |
| 103 | |
| 104 | #define REG_SPEED_CTL 0x00 |
| 105 | #define REG_SPEED_ADV100 0x08 |
| 106 | #define REG_SPEED_ADV1000 0x12 |
| 107 | |
| 108 | #define REG_QOS_EN 0x00 |
| 109 | #define REG_QOS_TAG_PORT1 0x12 // Default IEEE 802.1Q TAG, PORT 1 |
| 110 | #define REG_QOS_TAG_PORT2 0x14 // Default IEEE 802.1Q TAG, PORT 2 |
| 111 | #define REG_QOS_TAG_PORT3 0x16 // Default IEEE 802.1Q TAG, PORT 3 |
| 112 | #define REG_QOS_TAG_PORT4 0x18 // Default IEEE 802.1Q TAG, PORT 4 |
| 113 | #define REG_QOS_PID_PORT1 0x52 // Ingress Port Priority ID MAP, PORT 1 |
| 114 | #define REG_QOS_PID_PORT2 0x54 // Ingress Port Priority ID MAP, PORT 2 |
| 115 | #define REG_QOS_PID_PORT3 0x56 // Ingress Port Priority ID MAP, PORT 3 |
| 116 | #define REG_QOS_PID_PORT4 0x58 // Ingress Port Priority ID MAP, PORT 4 |
| 117 | #define REG_QOS_TXQ_CTL 0x80 // Tx Queue Control Register |
| 118 | #define REG_QOS_TXQ_WHTQ0 0x81 // Tx Queue Weight Register Queue 0 |
| 119 | #define REG_QOS_TXQ_WHTQ1 0x82 // Tx Queue Weight Register Queue 1 |
| 120 | #define REG_QOS_TXQ_WHTQ2 0x83 // Tx Queue Weight Register Queue 2 |
| 121 | #define REG_QOS_TXQ_WHTQ3 0x84 // Tx Queue Weight Register Queue 3 |
| 122 | |
| 123 | #define REG_CTRL_PPSEL 0x24 /* 5397: Protected port select register */ |
| 124 | |
| 125 | #define RATE_CONTROL_ENABLED (1 << 22) |
| 126 | #define RATE_CONTROL_BSIZE ((1 << 10) | (1 << 9) | (1 << 8)) |
| 127 | |
| 128 | #define RATE_CONTROL_HIGH ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4)) |
| 129 | #define RATE_CONTROL_HIGH_N ~((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)) |
| 130 | |
| 131 | #define RATE_CONTROL_MEDIUM ((1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)) |
| 132 | #define RATE_CONTROL_MEDIUM_N ~((1 << 7)) |
| 133 | |
| 134 | #define RATE_CONTROL_NORMAL ((1 << 5) | (1 << 2) | (1 << 0)) |
| 135 | #define RATE_CONTROL_NORMAL_N ~((1 << 7) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1)) |
| 136 | |
| 137 | #define RATE_CONTROL_LOW ((1 << 4) | (1 << 3) | (1 << 0)) |
| 138 | #define RATE_CONTROL_LOW_N ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2) | (1 << 1)) |
| 139 | |
| 140 | // --- Gemtek, Configure the switch to support Ethernet Port QoS |
| 141 | |
| 142 | /* MII access registers */ |
| 143 | #define PSEUDO_PHYAD 0x1E /* MII Pseudo PHY address */ |
| 144 | #define REG_MII_PAGE 0x10 /* MII Page register */ |
| 145 | #define REG_MII_ADDR 0x11 /* MII Address register */ |
| 146 | #define REG_MII_DATA0 0x18 /* MII Data register 0 */ |
| 147 | #define REG_MII_DATA1 0x19 /* MII Data register 1 */ |
| 148 | #define REG_MII_DATA2 0x1a /* MII Data register 2 */ |
| 149 | #define REG_MII_DATA3 0x1b /* MII Data register 3 */ |
| 150 | |
| 151 | /* Page numbers */ |
| 152 | #define PAGE_CTRL 0x00 /* Control page */ |
| 153 | #define PAGE_MMR 0x02 /* 5397 Management/Mirroring page */ |
| 154 | #define PAGE_VTBL 0x05 /* ARL/VLAN Table access page */ |
| 155 | #define PAGE_VLAN 0x34 /* VLAN page */ |
| 156 | |
| 157 | /* Control page registers */ |
| 158 | #define REG_CTRL_PORT0 0x00 /* Port 0 traffic control register */ |
| 159 | #define REG_CTRL_PORT1 0x01 /* Port 1 traffic control register */ |
| 160 | #define REG_CTRL_PORT2 0x02 /* Port 2 traffic control register */ |
| 161 | #define REG_CTRL_PORT3 0x03 /* Port 3 traffic control register */ |
| 162 | #define REG_CTRL_PORT4 0x04 /* Port 4 traffic control register */ |
| 163 | #define REG_CTRL_PORT5 0x05 /* Port 5 traffic control register */ |
| 164 | #define REG_CTRL_PORT6 0x06 /* Port 6 traffic control register */ |
| 165 | #define REG_CTRL_PORT7 0x07 /* Port 7 traffic control register */ |
| 166 | #define REG_CTRL_MODE 0x0B /* Switch Mode register */ |
| 167 | #define REG_CTRL_MIIPO 0x0E /* 5325: MII Port Override register */ |
| 168 | #define REG_CTRL_SRST 0x79 /* Software reset control register */ |
| 169 | |
| 170 | #define REG_DEVICE_ID 0x30 /* 539x Device id: */ |
| 171 | #define DEVID5395 0x95 /* 5395 */ |
| 172 | #define DEVID5397 0x97 /* 5397 */ |
| 173 | #define DEVID5398 0x98 /* 5398 */ |
| 174 | #define REG_REVISION_ID 0x40 /* 539x Revision id: */ |
| 175 | |
| 176 | /* VLAN page registers */ |
| 177 | #define REG_VLAN_CTRL0 0x00 /* VLAN Control 0 register */ |
| 178 | #define REG_VLAN_CTRL1 0x01 /* VLAN Control 1 register */ |
| 179 | #define REG_VLAN_CTRL2 0x02 /* VLAN Control 2 register */ |
| 180 | #define REG_VLAN_CTRL3 0x03 /* VLAN Control 3 register */ |
| 181 | #define REG_VLAN_CTRL4 0x04 /* VLAN Control 4 register */ |
| 182 | #define REG_VLAN_CTRL5 0x05 /* VLAN Control 5 register */ |
| 183 | #define REG_VLAN_ACCESS 0x06 /* VLAN Table Access register */ |
| 184 | #define REG_VLAN_WRITE 0x08 /* VLAN Write register */ |
| 185 | #define REG_VLAN_READ 0x0C /* VLAN Read register */ |
| 186 | #define REG_VLAN_PTAG0 0x10 /* VLAN Default Port Tag register - port 0 */ |
| 187 | #define REG_VLAN_PTAG1 0x12 /* VLAN Default Port Tag register - port 1 */ |
| 188 | #define REG_VLAN_PTAG2 0x14 /* VLAN Default Port Tag register - port 2 */ |
| 189 | #define REG_VLAN_PTAG3 0x16 /* VLAN Default Port Tag register - port 3 */ |
| 190 | #define REG_VLAN_PTAG4 0x18 /* VLAN Default Port Tag register - port 4 */ |
| 191 | #define REG_VLAN_PTAG5 0x1a /* VLAN Default Port Tag register - port 5 */ |
| 192 | #define REG_VLAN_PTAG6 0x1c /* VLAN Default Port Tag register - port 6 */ |
| 193 | #define REG_VLAN_PTAG7 0x1e /* VLAN Default Port Tag register - port 7 */ |
| 194 | #define REG_VLAN_PTAG8 0x20 /* 539x: VLAN Default Port Tag register - IMP port */ |
| 195 | #define REG_VLAN_PMAP 0x20 /* 5325: VLAN Priority Re-map register */ |
| 196 | |
| 197 | /* ARL/VLAN Table Access page registers */ |
| 198 | #define REG_VTBL_CTRL 0x00 /* ARL Read/Write Control */ |
| 199 | #define REG_VTBL_MINDX 0x02 /* MAC Address Index */ |
| 200 | #define REG_VTBL_VINDX 0x08 /* VID Table Index */ |
| 201 | #define REG_VTBL_ARL_E0 0x10 /* ARL Entry 0 */ |
| 202 | #define REG_VTBL_ARL_E1 0x18 /* ARL Entry 1 */ |
| 203 | #define REG_VTBL_DAT_E0 0x18 /* ARL Table Data Entry 0 */ |
| 204 | #define REG_VTBL_SCTRL 0x20 /* ARL Search Control */ |
| 205 | #define REG_VTBL_SADDR 0x22 /* ARL Search Address */ |
| 206 | #define REG_VTBL_SRES 0x24 /* ARL Search Result */ |
| 207 | #define REG_VTBL_SREXT 0x2c /* ARL Search Result */ |
| 208 | #define REG_VTBL_VID_E0 0x30 /* VID Entry 0 */ |
| 209 | #define REG_VTBL_VID_E1 0x32 /* VID Entry 1 */ |
| 210 | #define REG_VTBL_PREG 0xFF /* Page Register */ |
| 211 | #define REG_VTBL_ACCESS 0x60 /* VLAN table access register */ |
| 212 | #define REG_VTBL_INDX 0x61 /* VLAN table address index register */ |
| 213 | #define REG_VTBL_ENTRY 0x63 /* VLAN table entry register */ |
| 214 | #define REG_VTBL_ACCESS_5395 0x80 /* VLAN table access register */ |
| 215 | #define REG_VTBL_INDX_5395 0x81 /* VLAN table address index register */ |
| 216 | #define REG_VTBL_ENTRY_5395 0x83 /* VLAN table entry register */ |
| 217 | |
| 218 | /* SPI registers */ |
| 219 | #define REG_SPI_PAGE 0xff /* SPI Page register */ |
| 220 | |
| 221 | #endif |
| 222 | |
