| 1 | From 9951cfc88b5d818391bebc7a56b678942b89721e Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Sun, 5 Jun 2011 23:38:45 +0200 |
| 4 | Subject: [PATCH 02/27] MIPS: ath79: Handle more MISC IRQs |
| 5 | |
| 6 | The AR724X SoCs have more IRQ sources hooked into the MISC IRQ controller. |
| 7 | The patch adds support for them. |
| 8 | |
| 9 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 10 | Cc: linux-mips@linux-mips.org |
| 11 | Patchwork: https://patchwork.linux-mips.org/patch/2440/ |
| 12 | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
| 13 | --- |
| 14 | arch/mips/ath79/irq.c | 12 ++++++++++++ |
| 15 | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++++ |
| 16 | arch/mips/include/asm/mach-ath79/irq.h | 4 ++++ |
| 17 | 3 files changed, 20 insertions(+), 0 deletions(-) |
| 18 | |
| 19 | --- a/arch/mips/ath79/irq.c |
| 20 | +++ b/arch/mips/ath79/irq.c |
| 21 | @@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsig |
| 22 | else if (pending & MISC_INT_TIMER) |
| 23 | generic_handle_irq(ATH79_MISC_IRQ_TIMER); |
| 24 | |
| 25 | + else if (pending & MISC_INT_TIMER2) |
| 26 | + generic_handle_irq(ATH79_MISC_IRQ_TIMER2); |
| 27 | + |
| 28 | + else if (pending & MISC_INT_TIMER3) |
| 29 | + generic_handle_irq(ATH79_MISC_IRQ_TIMER3); |
| 30 | + |
| 31 | + else if (pending & MISC_INT_TIMER4) |
| 32 | + generic_handle_irq(ATH79_MISC_IRQ_TIMER4); |
| 33 | + |
| 34 | else if (pending & MISC_INT_OHCI) |
| 35 | generic_handle_irq(ATH79_MISC_IRQ_OHCI); |
| 36 | |
| 37 | @@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsig |
| 38 | else if (pending & MISC_INT_WDOG) |
| 39 | generic_handle_irq(ATH79_MISC_IRQ_WDOG); |
| 40 | |
| 41 | + else if (pending & MISC_INT_ETHSW) |
| 42 | + generic_handle_irq(ATH79_MISC_IRQ_ETHSW); |
| 43 | + |
| 44 | else |
| 45 | spurious_interrupt(); |
| 46 | } |
| 47 | --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 48 | +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 49 | @@ -130,6 +130,10 @@ |
| 50 | |
| 51 | #define AR724X_RESET_REG_RESET_MODULE 0x1c |
| 52 | |
| 53 | +#define MISC_INT_ETHSW BIT(12) |
| 54 | +#define MISC_INT_TIMER4 BIT(10) |
| 55 | +#define MISC_INT_TIMER3 BIT(9) |
| 56 | +#define MISC_INT_TIMER2 BIT(8) |
| 57 | #define MISC_INT_DMA BIT(7) |
| 58 | #define MISC_INT_OHCI BIT(6) |
| 59 | #define MISC_INT_PERFC BIT(5) |
| 60 | --- a/arch/mips/include/asm/mach-ath79/irq.h |
| 61 | +++ b/arch/mips/include/asm/mach-ath79/irq.h |
| 62 | @@ -30,6 +30,10 @@ |
| 63 | #define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) |
| 64 | #define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) |
| 65 | #define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) |
| 66 | +#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8) |
| 67 | +#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9) |
| 68 | +#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10) |
| 69 | +#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12) |
| 70 | |
| 71 | #include_next <irq.h> |
| 72 | |
| 73 | |
