Root/target/linux/ar71xx/patches-3.2/007-MIPS-ath79-add-AR933X-specific-clock-init.patch

1From 29c8b2eef2011bf9392479487a51f6927892bfd6 Mon Sep 17 00:00:00 2001
2From: Gabor Juhos <juhosg@openwrt.org>
3Date: Mon, 20 Jun 2011 21:26:04 +0200
4Subject: [PATCH 07/27] MIPS: ath79: add AR933X specific clock init
5
6Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7Cc: linux-mips@linux-mips.org
8Cc: Kathy Giori <kgiori@qca.qualcomm.com>
9Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
10Patchwork: https://patchwork.linux-mips.org/patch/2522/
11Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
12---
13 arch/mips/ath79/clock.c | 55 ++++++++++++++++++++++++
14 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 22 +++++++++
15 arch/mips/include/asm/mach-ath79/ath79.h | 6 +++
16 3 files changed, 83 insertions(+), 0 deletions(-)
17
18--- a/arch/mips/ath79/clock.c
19+++ b/arch/mips/ath79/clock.c
20@@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(vo
21     ath79_uart_clk.rate = ath79_ahb_clk.rate;
22 }
23 
24+static void __init ar933x_clocks_init(void)
25+{
26+ u32 clock_ctrl;
27+ u32 cpu_config;
28+ u32 freq;
29+ u32 t;
30+
31+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
32+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
33+ ath79_ref_clk.rate = (40 * 1000 * 1000);
34+ else
35+ ath79_ref_clk.rate = (25 * 1000 * 1000);
36+
37+ clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
38+ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
39+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
40+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
41+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
42+ } else {
43+ cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
44+
45+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
46+ AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
47+ freq = ath79_ref_clk.rate / t;
48+
49+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
50+ AR933X_PLL_CPU_CONFIG_NINT_MASK;
51+ freq *= t;
52+
53+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
54+ AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
55+ if (t == 0)
56+ t = 1;
57+
58+ freq >>= t;
59+
60+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
61+ AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
62+ ath79_cpu_clk.rate = freq / t;
63+
64+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
65+ AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
66+ ath79_ddr_clk.rate = freq / t;
67+
68+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
69+ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
70+ ath79_ahb_clk.rate = freq / t;
71+ }
72+
73+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
74+ ath79_uart_clk.rate = ath79_ref_clk.rate;
75+}
76+
77 void __init ath79_clocks_init(void)
78 {
79     if (soc_is_ar71xx())
80@@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
81         ar724x_clocks_init();
82     else if (soc_is_ar913x())
83         ar913x_clocks_init();
84+ else if (soc_is_ar933x())
85+ ar933x_clocks_init();
86     else
87         BUG();
88 
89--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
90+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
91@@ -123,6 +123,24 @@
92 #define AR913X_AHB_DIV_SHIFT 19
93 #define AR913X_AHB_DIV_MASK 0x1
94 
95+#define AR933X_PLL_CPU_CONFIG_REG 0x00
96+#define AR933X_PLL_CLOCK_CTRL_REG 0x08
97+
98+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
99+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
100+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
101+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
102+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
103+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
104+
105+#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
106+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
107+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
108+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
109+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
110+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
111+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
112+
113 /*
114  * USB_CONFIG block
115  */
116@@ -155,6 +173,8 @@
117 
118 #define AR724X_RESET_REG_RESET_MODULE 0x1c
119 
120+#define AR933X_RESET_REG_BOOTSTRAP 0xac
121+
122 #define MISC_INT_ETHSW BIT(12)
123 #define MISC_INT_TIMER4 BIT(10)
124 #define MISC_INT_TIMER3 BIT(9)
125@@ -204,6 +224,8 @@
126 #define AR913X_RESET_USB_HOST BIT(5)
127 #define AR913X_RESET_USB_PHY BIT(4)
128 
129+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
130+
131 #define REV_ID_MAJOR_MASK 0xfff0
132 #define REV_ID_MAJOR_AR71XX 0x00a0
133 #define REV_ID_MAJOR_AR913X 0x00b0
134--- a/arch/mips/include/asm/mach-ath79/ath79.h
135+++ b/arch/mips/include/asm/mach-ath79/ath79.h
136@@ -68,6 +68,12 @@ static inline int soc_is_ar913x(void)
137         ath79_soc == ATH79_SOC_AR9132);
138 }
139 
140+static inline int soc_is_ar933x(void)
141+{
142+ return (ath79_soc == ATH79_SOC_AR9330 ||
143+ ath79_soc == ATH79_SOC_AR9331);
144+}
145+
146 extern void __iomem *ath79_ddr_base;
147 extern void __iomem *ath79_pll_base;
148 extern void __iomem *ath79_reset_base;
149

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