| 1 | From 1355a27c85ae89225e738b9016656a406542ed1b Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Mon, 20 Jun 2011 21:26:10 +0200 |
| 4 | Subject: [PATCH 13/27] MIPS: ath79: add AR933X specific USB platform device registration |
| 5 | |
| 6 | Also select the USB_ARCH_HAS_EHCI symbol in order to make the |
| 7 | EHCI driver available. |
| 8 | |
| 9 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 10 | Cc: linux-mips@linux-mips.org |
| 11 | Cc: Kathy Giori <kgiori@qca.qualcomm.com> |
| 12 | Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com> |
| 13 | Patchwork: https://patchwork.linux-mips.org/patch/2527/ |
| 14 | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
| 15 | --- |
| 16 | arch/mips/ath79/Kconfig | 1 + |
| 17 | arch/mips/ath79/dev-usb.c | 19 +++++++++++++++++++ |
| 18 | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 +++++++ |
| 19 | 3 files changed, 27 insertions(+), 0 deletions(-) |
| 20 | |
| 21 | --- a/arch/mips/ath79/Kconfig |
| 22 | +++ b/arch/mips/ath79/Kconfig |
| 23 | @@ -42,6 +42,7 @@ config SOC_AR913X |
| 24 | def_bool n |
| 25 | |
| 26 | config SOC_AR933X |
| 27 | + select USB_ARCH_HAS_EHCI |
| 28 | def_bool n |
| 29 | |
| 30 | config ATH79_DEV_AR913X_WMAC |
| 31 | --- a/arch/mips/ath79/dev-usb.c |
| 32 | +++ b/arch/mips/ath79/dev-usb.c |
| 33 | @@ -163,6 +163,23 @@ static void __init ar913x_usb_setup(void |
| 34 | platform_device_register(&ath79_ehci_device); |
| 35 | } |
| 36 | |
| 37 | +static void __init ar933x_usb_setup(void) |
| 38 | +{ |
| 39 | + ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE); |
| 40 | + mdelay(10); |
| 41 | + |
| 42 | + ath79_device_reset_clear(AR933X_RESET_USB_HOST); |
| 43 | + mdelay(10); |
| 44 | + |
| 45 | + ath79_device_reset_clear(AR933X_RESET_USB_PHY); |
| 46 | + mdelay(10); |
| 47 | + |
| 48 | + ath79_ehci_resources[0].start = AR933X_EHCI_BASE; |
| 49 | + ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; |
| 50 | + ath79_ehci_device.name = "ar933x-ehci"; |
| 51 | + platform_device_register(&ath79_ehci_device); |
| 52 | +} |
| 53 | + |
| 54 | void __init ath79_register_usb(void) |
| 55 | { |
| 56 | if (soc_is_ar71xx()) |
| 57 | @@ -173,6 +190,8 @@ void __init ath79_register_usb(void) |
| 58 | ar724x_usb_setup(); |
| 59 | else if (soc_is_ar913x()) |
| 60 | ar913x_usb_setup(); |
| 61 | + else if (soc_is_ar933x()) |
| 62 | + ar933x_usb_setup(); |
| 63 | else |
| 64 | BUG(); |
| 65 | } |
| 66 | --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 67 | +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 68 | @@ -56,6 +56,9 @@ |
| 69 | #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) |
| 70 | #define AR933X_UART_SIZE 0x14 |
| 71 | |
| 72 | +#define AR933X_EHCI_BASE 0x1b000000 |
| 73 | +#define AR933X_EHCI_SIZE 0x1000 |
| 74 | + |
| 75 | /* |
| 76 | * DDR_CTRL block |
| 77 | */ |
| 78 | @@ -230,6 +233,10 @@ |
| 79 | #define AR913X_RESET_USB_HOST BIT(5) |
| 80 | #define AR913X_RESET_USB_PHY BIT(4) |
| 81 | |
| 82 | +#define AR933X_RESET_USB_HOST BIT(5) |
| 83 | +#define AR933X_RESET_USB_PHY BIT(4) |
| 84 | +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) |
| 85 | + |
| 86 | #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) |
| 87 | |
| 88 | #define REV_ID_MAJOR_MASK 0xfff0 |
| 89 | |
