| 1 | From c01b6005cfa2d762c2de33d5be2e82f91afaa66f Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Fri, 9 Dec 2011 20:53:47 +0100 |
| 4 | Subject: [PATCH 25/35] MIPS: ath79: add GPIO support code for AR934X |
| 5 | |
| 6 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 7 | Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> |
| 8 | --- |
| 9 | arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++- |
| 10 | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + |
| 11 | 2 files changed, 47 insertions(+), 1 deletions(-) |
| 12 | |
| 13 | --- a/arch/mips/ath79/gpio.c |
| 14 | +++ b/arch/mips/ath79/gpio.c |
| 15 | @@ -1,9 +1,12 @@ |
| 16 | /* |
| 17 | * Atheros AR71XX/AR724X/AR913X GPIO API support |
| 18 | * |
| 19 | - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> |
| 20 | + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> |
| 21 | + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
| 22 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
| 23 | * |
| 24 | + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP |
| 25 | + * |
| 26 | * This program is free software; you can redistribute it and/or modify it |
| 27 | * under the terms of the GNU General Public License version 2 as published |
| 28 | * by the Free Software Foundation. |
| 29 | @@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s |
| 30 | return 0; |
| 31 | } |
| 32 | |
| 33 | +static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 34 | +{ |
| 35 | + void __iomem *base = ath79_gpio_base; |
| 36 | + unsigned long flags; |
| 37 | + |
| 38 | + spin_lock_irqsave(&ath79_gpio_lock, flags); |
| 39 | + |
| 40 | + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), |
| 41 | + base + AR71XX_GPIO_REG_OE); |
| 42 | + |
| 43 | + spin_unlock_irqrestore(&ath79_gpio_lock, flags); |
| 44 | + |
| 45 | + return 0; |
| 46 | +} |
| 47 | + |
| 48 | +static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
| 49 | + int value) |
| 50 | +{ |
| 51 | + void __iomem *base = ath79_gpio_base; |
| 52 | + unsigned long flags; |
| 53 | + |
| 54 | + spin_lock_irqsave(&ath79_gpio_lock, flags); |
| 55 | + |
| 56 | + if (value) |
| 57 | + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); |
| 58 | + else |
| 59 | + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); |
| 60 | + |
| 61 | + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), |
| 62 | + base + AR71XX_GPIO_REG_OE); |
| 63 | + |
| 64 | + spin_unlock_irqrestore(&ath79_gpio_lock, flags); |
| 65 | + |
| 66 | + return 0; |
| 67 | +} |
| 68 | + |
| 69 | static struct gpio_chip ath79_gpio_chip = { |
| 70 | .label = "ath79", |
| 71 | .get = ath79_gpio_get_value, |
| 72 | @@ -155,11 +194,17 @@ void __init ath79_gpio_init(void) |
| 73 | ath79_gpio_count = AR913X_GPIO_COUNT; |
| 74 | else if (soc_is_ar933x()) |
| 75 | ath79_gpio_count = AR933X_GPIO_COUNT; |
| 76 | + else if (soc_is_ar934x()) |
| 77 | + ath79_gpio_count = AR934X_GPIO_COUNT; |
| 78 | else |
| 79 | BUG(); |
| 80 | |
| 81 | ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); |
| 82 | ath79_gpio_chip.ngpio = ath79_gpio_count; |
| 83 | + if (soc_is_ar934x()) { |
| 84 | + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; |
| 85 | + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; |
| 86 | + } |
| 87 | |
| 88 | err = gpiochip_add(&ath79_gpio_chip); |
| 89 | if (err) |
| 90 | --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 91 | +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 92 | @@ -367,5 +367,6 @@ |
| 93 | #define AR724X_GPIO_COUNT 18 |
| 94 | #define AR913X_GPIO_COUNT 22 |
| 95 | #define AR933X_GPIO_COUNT 30 |
| 96 | +#define AR934X_GPIO_COUNT 23 |
| 97 | |
| 98 | #endif /* __ASM_MACH_AR71XX_REGS_H */ |
| 99 | |
