Root/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch

1From 9510a9988638ae2386277a832fab2df8ca37d75a Mon Sep 17 00:00:00 2001
2From: Gabor Juhos <juhosg@openwrt.org>
3Date: Fri, 18 Nov 2011 11:07:26 +0100
4Subject: [PATCH 06/35] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10Acked-by: René Bolldorf <xsecute@googlemail.com>
11
12v4: - add an Acked-by tag from René
13v4: - no changes
14v3: - no changes
15v2: - no changes
16---
17 arch/mips/pci/Makefile | 2 +-
18 arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++
19 arch/mips/pci/pci-ath724x.c | 139 -------------------------------------------
20 3 files changed, 140 insertions(+), 140 deletions(-)
21 create mode 100644 arch/mips/pci/pci-ar724x.c
22 delete mode 100644 arch/mips/pci/pci-ath724x.c
23
24--- a/arch/mips/pci/Makefile
25+++ b/arch/mips/pci/Makefile
26@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
27 obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
28                     ops-bcm63xx.o
29 obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
30-obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
31+obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
32 
33 #
34 # These are still pretty much in the old state, watch, go blind.
35--- /dev/null
36+++ b/arch/mips/pci/pci-ar724x.c
37@@ -0,0 +1,139 @@
38+/*
39+ * Atheros 724x PCI support
40+ *
41+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
42+ *
43+ * This program is free software; you can redistribute it and/or modify it
44+ * under the terms of the GNU General Public License version 2 as published
45+ * by the Free Software Foundation.
46+ */
47+
48+#include <linux/pci.h>
49+#include <asm/mach-ath79/pci.h>
50+
51+#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
52+#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
53+
54+#define ATH724X_PCI_DEV_BASE 0x14000000
55+#define ATH724X_PCI_MEM_BASE 0x10000000
56+#define ATH724X_PCI_MEM_SIZE 0x08000000
57+
58+static DEFINE_SPINLOCK(ath724x_pci_lock);
59+
60+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
61+ int size, uint32_t *value)
62+{
63+ unsigned long flags, addr, tval, mask;
64+
65+ if (devfn)
66+ return PCIBIOS_DEVICE_NOT_FOUND;
67+
68+ if (where & (size - 1))
69+ return PCIBIOS_BAD_REGISTER_NUMBER;
70+
71+ spin_lock_irqsave(&ath724x_pci_lock, flags);
72+
73+ switch (size) {
74+ case 1:
75+ addr = where & ~3;
76+ mask = 0xff000000 >> ((where % 4) * 8);
77+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
78+ tval = tval & ~mask;
79+ *value = (tval >> ((4 - (where % 4))*8));
80+ break;
81+ case 2:
82+ addr = where & ~3;
83+ mask = 0xffff0000 >> ((where % 4)*8);
84+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
85+ tval = tval & ~mask;
86+ *value = (tval >> ((4 - (where % 4))*8));
87+ break;
88+ case 4:
89+ *value = reg_read(ATH724X_PCI_DEV_BASE + where);
90+ break;
91+ default:
92+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
93+
94+ return PCIBIOS_BAD_REGISTER_NUMBER;
95+ }
96+
97+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
98+
99+ return PCIBIOS_SUCCESSFUL;
100+}
101+
102+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
103+ int size, uint32_t value)
104+{
105+ unsigned long flags, tval, addr, mask;
106+
107+ if (devfn)
108+ return PCIBIOS_DEVICE_NOT_FOUND;
109+
110+ if (where & (size - 1))
111+ return PCIBIOS_BAD_REGISTER_NUMBER;
112+
113+ spin_lock_irqsave(&ath724x_pci_lock, flags);
114+
115+ switch (size) {
116+ case 1:
117+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
118+ mask = 0xff000000 >> ((where % 4)*8);
119+ tval = reg_read(addr);
120+ tval = tval & ~mask;
121+ tval |= (value << ((4 - (where % 4))*8)) & mask;
122+ reg_write(addr, tval);
123+ break;
124+ case 2:
125+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
126+ mask = 0xffff0000 >> ((where % 4)*8);
127+ tval = reg_read(addr);
128+ tval = tval & ~mask;
129+ tval |= (value << ((4 - (where % 4))*8)) & mask;
130+ reg_write(addr, tval);
131+ break;
132+ case 4:
133+ reg_write((ATH724X_PCI_DEV_BASE + where), value);
134+ break;
135+ default:
136+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
137+
138+ return PCIBIOS_BAD_REGISTER_NUMBER;
139+ }
140+
141+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
142+
143+ return PCIBIOS_SUCCESSFUL;
144+}
145+
146+static struct pci_ops ath724x_pci_ops = {
147+ .read = ath724x_pci_read,
148+ .write = ath724x_pci_write,
149+};
150+
151+static struct resource ath724x_io_resource = {
152+ .name = "PCI IO space",
153+ .start = 0,
154+ .end = 0,
155+ .flags = IORESOURCE_IO,
156+};
157+
158+static struct resource ath724x_mem_resource = {
159+ .name = "PCI memory space",
160+ .start = ATH724X_PCI_MEM_BASE,
161+ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
162+ .flags = IORESOURCE_MEM,
163+};
164+
165+static struct pci_controller ath724x_pci_controller = {
166+ .pci_ops = &ath724x_pci_ops,
167+ .io_resource = &ath724x_io_resource,
168+ .mem_resource = &ath724x_mem_resource,
169+};
170+
171+int __init ath724x_pcibios_init(void)
172+{
173+ register_pci_controller(&ath724x_pci_controller);
174+
175+ return PCIBIOS_SUCCESSFUL;
176+}
177--- a/arch/mips/pci/pci-ath724x.c
178+++ /dev/null
179@@ -1,139 +0,0 @@
180-/*
181- * Atheros 724x PCI support
182- *
183- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
184- *
185- * This program is free software; you can redistribute it and/or modify it
186- * under the terms of the GNU General Public License version 2 as published
187- * by the Free Software Foundation.
188- */
189-
190-#include <linux/pci.h>
191-#include <asm/mach-ath79/pci.h>
192-
193-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
194-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
195-
196-#define ATH724X_PCI_DEV_BASE 0x14000000
197-#define ATH724X_PCI_MEM_BASE 0x10000000
198-#define ATH724X_PCI_MEM_SIZE 0x08000000
199-
200-static DEFINE_SPINLOCK(ath724x_pci_lock);
201-
202-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
203- int size, uint32_t *value)
204-{
205- unsigned long flags, addr, tval, mask;
206-
207- if (devfn)
208- return PCIBIOS_DEVICE_NOT_FOUND;
209-
210- if (where & (size - 1))
211- return PCIBIOS_BAD_REGISTER_NUMBER;
212-
213- spin_lock_irqsave(&ath724x_pci_lock, flags);
214-
215- switch (size) {
216- case 1:
217- addr = where & ~3;
218- mask = 0xff000000 >> ((where % 4) * 8);
219- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
220- tval = tval & ~mask;
221- *value = (tval >> ((4 - (where % 4))*8));
222- break;
223- case 2:
224- addr = where & ~3;
225- mask = 0xffff0000 >> ((where % 4)*8);
226- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
227- tval = tval & ~mask;
228- *value = (tval >> ((4 - (where % 4))*8));
229- break;
230- case 4:
231- *value = reg_read(ATH724X_PCI_DEV_BASE + where);
232- break;
233- default:
234- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
235-
236- return PCIBIOS_BAD_REGISTER_NUMBER;
237- }
238-
239- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
240-
241- return PCIBIOS_SUCCESSFUL;
242-}
243-
244-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
245- int size, uint32_t value)
246-{
247- unsigned long flags, tval, addr, mask;
248-
249- if (devfn)
250- return PCIBIOS_DEVICE_NOT_FOUND;
251-
252- if (where & (size - 1))
253- return PCIBIOS_BAD_REGISTER_NUMBER;
254-
255- spin_lock_irqsave(&ath724x_pci_lock, flags);
256-
257- switch (size) {
258- case 1:
259- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
260- mask = 0xff000000 >> ((where % 4)*8);
261- tval = reg_read(addr);
262- tval = tval & ~mask;
263- tval |= (value << ((4 - (where % 4))*8)) & mask;
264- reg_write(addr, tval);
265- break;
266- case 2:
267- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
268- mask = 0xffff0000 >> ((where % 4)*8);
269- tval = reg_read(addr);
270- tval = tval & ~mask;
271- tval |= (value << ((4 - (where % 4))*8)) & mask;
272- reg_write(addr, tval);
273- break;
274- case 4:
275- reg_write((ATH724X_PCI_DEV_BASE + where), value);
276- break;
277- default:
278- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
279-
280- return PCIBIOS_BAD_REGISTER_NUMBER;
281- }
282-
283- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
284-
285- return PCIBIOS_SUCCESSFUL;
286-}
287-
288-static struct pci_ops ath724x_pci_ops = {
289- .read = ath724x_pci_read,
290- .write = ath724x_pci_write,
291-};
292-
293-static struct resource ath724x_io_resource = {
294- .name = "PCI IO space",
295- .start = 0,
296- .end = 0,
297- .flags = IORESOURCE_IO,
298-};
299-
300-static struct resource ath724x_mem_resource = {
301- .name = "PCI memory space",
302- .start = ATH724X_PCI_MEM_BASE,
303- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
304- .flags = IORESOURCE_MEM,
305-};
306-
307-static struct pci_controller ath724x_pci_controller = {
308- .pci_ops = &ath724x_pci_ops,
309- .io_resource = &ath724x_io_resource,
310- .mem_resource = &ath724x_mem_resource,
311-};
312-
313-int __init ath724x_pcibios_init(void)
314-{
315- register_pci_controller(&ath724x_pci_controller);
316-
317- return PCIBIOS_SUCCESSFUL;
318-}
319

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