Root/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch

1--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
2+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
3@@ -20,7 +20,13 @@
4 #include <linux/io.h>
5 #include <linux/bitops.h>
6 
7+#define AR71XX_PCI_MEM_BASE 0x10000000
8+#define AR71XX_PCI_MEM_SIZE 0x08000000
9 #define AR71XX_APB_BASE 0x18000000
10+#define AR71XX_GE0_BASE 0x19000000
11+#define AR71XX_GE0_SIZE 0x10000
12+#define AR71XX_GE1_BASE 0x1a000000
13+#define AR71XX_GE1_SIZE 0x10000
14 #define AR71XX_EHCI_BASE 0x1b000000
15 #define AR71XX_EHCI_SIZE 0x1000
16 #define AR71XX_OHCI_BASE 0x1c000000
17@@ -40,6 +46,8 @@
18 #define AR71XX_PLL_SIZE 0x100
19 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
20 #define AR71XX_RESET_SIZE 0x100
21+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
22+#define AR71XX_MII_SIZE 0x100
23 
24 #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
25 #define AR7240_USB_CTRL_SIZE 0x100
26@@ -56,11 +64,15 @@
27 
28 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
29 #define AR933X_UART_SIZE 0x14
30+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
31+#define AR933X_GMAC_SIZE 0x04
32 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
33 #define AR933X_WMAC_SIZE 0x20000
34 #define AR933X_EHCI_BASE 0x1b000000
35 #define AR933X_EHCI_SIZE 0x1000
36 
37+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
38+#define AR934X_GMAC_SIZE 0x14
39 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
40 #define AR934X_WMAC_SIZE 0x20000
41 #define AR934X_EHCI_BASE 0x1b000000
42@@ -120,6 +132,9 @@
43 #define AR71XX_AHB_DIV_SHIFT 20
44 #define AR71XX_AHB_DIV_MASK 0x7
45 
46+#define AR71XX_ETH0_PLL_SHIFT 17
47+#define AR71XX_ETH1_PLL_SHIFT 19
48+
49 #define AR724X_PLL_REG_CPU_CONFIG 0x00
50 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
51 
52@@ -132,6 +147,8 @@
53 #define AR724X_DDR_DIV_SHIFT 22
54 #define AR724X_DDR_DIV_MASK 0x3
55 
56+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
57+
58 #define AR913X_PLL_REG_CPU_CONFIG 0x00
59 #define AR913X_PLL_REG_ETH_CONFIG 0x04
60 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
61@@ -144,6 +161,9 @@
62 #define AR913X_AHB_DIV_SHIFT 19
63 #define AR913X_AHB_DIV_MASK 0x1
64 
65+#define AR913X_ETH0_PLL_SHIFT 20
66+#define AR913X_ETH1_PLL_SHIFT 22
67+
68 #define AR933X_PLL_CPU_CONFIG_REG 0x00
69 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
70 
71@@ -285,7 +305,11 @@
72 #define AR913X_RESET_USB_HOST BIT(5)
73 #define AR913X_RESET_USB_PHY BIT(4)
74 
75+#define AR933X_RESET_GE1_MDIO BIT(23)
76+#define AR933X_RESET_GE0_MDIO BIT(22)
77+#define AR933X_RESET_GE1_MAC BIT(13)
78 #define AR933X_RESET_WMAC BIT(11)
79+#define AR933X_RESET_GE0_MAC BIT(9)
80 #define AR933X_RESET_USB_HOST BIT(5)
81 #define AR933X_RESET_USB_PHY BIT(4)
82 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
83@@ -323,6 +347,8 @@
84 #define AR934X_RESET_MBOX BIT(1)
85 #define AR934X_RESET_I2S BIT(0)
86 
87+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
88+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
89 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
90 
91 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
92@@ -427,6 +453,14 @@
93 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
94 #define AR71XX_GPIO_REG_FUNC 0x28
95 
96+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
97+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
98+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
99+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
100+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
101+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
102+#define AR934X_GPIO_REG_FUNC 0x6c
103+
104 #define AR71XX_GPIO_COUNT 16
105 #define AR7240_GPIO_COUNT 18
106 #define AR7241_GPIO_COUNT 20
107@@ -434,4 +468,124 @@
108 #define AR933X_GPIO_COUNT 30
109 #define AR934X_GPIO_COUNT 23
110 
111+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
112+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
113+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
114+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
115+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
116+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
117+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
118+
119+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
120+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
121+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
122+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
123+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
124+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
125+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
126+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
127+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
128+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
129+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
130+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
131+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
132+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
133+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
134+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
135+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
136+
137+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
138+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
139+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
140+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
141+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
142+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
143+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
144+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
145+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
146+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
147+
148+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
149+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
150+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
151+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
152+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
153+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
154+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
155+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
156+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
157+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
158+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
159+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
160+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
161+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
162+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
163+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
164+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
165+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
166+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
167+
168+#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
169+#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
170+#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
171+
172+#define AR934X_GPIO_OUT_GPIO 0x00
173+
174+/*
175+ * MII_CTRL block
176+ */
177+#define AR71XX_MII_REG_MII0_CTRL 0x00
178+#define AR71XX_MII_REG_MII1_CTRL 0x04
179+
180+#define AR71XX_MII_CTRL_IF_MASK 3
181+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
182+#define AR71XX_MII_CTRL_SPEED_MASK 3
183+#define AR71XX_MII_CTRL_SPEED_10 0
184+#define AR71XX_MII_CTRL_SPEED_100 1
185+#define AR71XX_MII_CTRL_SPEED_1000 2
186+
187+#define AR71XX_MII0_CTRL_IF_GMII 0
188+#define AR71XX_MII0_CTRL_IF_MII 1
189+#define AR71XX_MII0_CTRL_IF_RGMII 2
190+#define AR71XX_MII0_CTRL_IF_RMII 3
191+
192+#define AR71XX_MII1_CTRL_IF_RGMII 0
193+#define AR71XX_MII1_CTRL_IF_RMII 1
194+
195+/*
196+ * AR933X GMAC interface
197+ */
198+#define AR933X_GMAC_REG_ETH_CFG 0x00
199+
200+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
201+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
202+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
203+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
204+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
205+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
206+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
207+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
208+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
209+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
210+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
211+
212+/*
213+ * AR934X GMAC Interface
214+ */
215+#define AR934X_GMAC_REG_ETH_CFG 0x00
216+
217+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
218+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
219+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
220+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
221+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
222+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
223+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
224+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
225+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
226+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
227+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
228+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
229+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
230+
231 #endif /* __ASM_MACH_AR71XX_REGS_H */
232

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