Root/target/linux/brcm47xx/patches-3.2/0012-bcma-move-parallel-flash-into-a-union.patch

1From b7d9f9cd6a8e463c1061ea29ed3e614403625024 Mon Sep 17 00:00:00 2001
2From: Hauke Mehrtens <hauke@hauke-m.de>
3Date: Sun, 17 Jul 2011 14:51:47 +0200
4Subject: [PATCH 12/26] bcma: move parallel flash into a union
5
6
7Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
8---
9 arch/mips/bcm47xx/nvram.c | 3 +
10 drivers/bcma/driver_mips.c | 1 +
11 include/linux/bcma/bcma_driver_chipcommon.h | 73 ++++++++++++++++++++++++++-
12 3 files changed, 76 insertions(+), 1 deletions(-)
13
14--- a/arch/mips/bcm47xx/nvram.c
15+++ b/arch/mips/bcm47xx/nvram.c
16@@ -50,6 +50,9 @@ static void early_nvram_init(void)
17 #ifdef CONFIG_BCM47XX_BCMA
18     case BCM47XX_BUS_TYPE_BCMA:
19         bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc;
20+ if (bcma_cc->flash_type != BCMA_PFLASH)
21+ return;
22+
23         base = bcma_cc->pflash.window;
24         lim = bcma_cc->pflash.window_size;
25         break;
26--- a/drivers/bcma/driver_mips.c
27+++ b/drivers/bcma/driver_mips.c
28@@ -189,6 +189,7 @@ static void bcma_core_mips_flash_detect(
29         break;
30     case BCMA_CC_FLASHT_PARA:
31         pr_info("found parallel flash.\n");
32+ bus->drv_cc.flash_type = BCMA_PFLASH;
33         bus->drv_cc.pflash.window = 0x1c000000;
34         bus->drv_cc.pflash.window_size = 0x02000000;
35 
36--- a/include/linux/bcma/bcma_driver_chipcommon.h
37+++ b/include/linux/bcma/bcma_driver_chipcommon.h
38@@ -108,10 +108,68 @@
39 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
40 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
41 #define BCMA_CC_FLASHCTL 0x0040
42+
43+/* Start/busy bit in flashcontrol */
44+#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
45+#define BCMA_CC_FLASHCTL_ACTION 0x00000700
46+#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
47 #define BCMA_CC_FLASHCTL_START 0x80000000
48 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
49+
50+/* flashcontrol action+opcodes for ST flashes */
51+#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
52+#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
53+#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
54+#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
55+#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
56+#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
57+#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
58+#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
59+#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
60+#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
61+#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
62+#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
63+
64+
65+/* flashcontrol action+opcodes for Atmel flashes */
66+#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
67+#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
68+#define BCMA_CC_FLASHCTL_AT_BUF1_READ
69+#define BCMA_CC_FLASHCTL_AT_BUF2_READ
70+#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
71+#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
72+#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
73+#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
74+#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
75+#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
76+#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
77+#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
78+#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
79+#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
80+#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
81+#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
82+#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
83+#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
84+#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
85+#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
86+#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
87+
88 #define BCMA_CC_FLASHADDR 0x0044
89 #define BCMA_CC_FLASHDATA 0x0048
90+
91+/* Status register bits for ST flashes */
92+#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
93+#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
94+#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
95+#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
96+#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
97+
98+/* Status register bits for Atmel flashes */
99+#define BCMA_CC_FLASHDATA_AT_READY 0x80
100+#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
101+#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
102+#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
103+
104 #define BCMA_CC_BCAST_ADDR 0x0050
105 #define BCMA_CC_BCAST_DATA 0x0054
106 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
107@@ -300,6 +358,12 @@
108 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
109 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
110 
111+#define BCMA_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
112+#define BCMA_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
113+#define BCMA_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
114+#define BCMA_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
115+
116+
117 /* Data for the PMU, if available.
118  * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
119  */
120@@ -309,6 +373,10 @@ struct bcma_chipcommon_pmu {
121 };
122 
123 #ifdef CONFIG_BCMA_DRIVER_MIPS
124+enum bcma_flash_type {
125+ BCMA_PFLASH,
126+};
127+
128 struct bcma_pflash {
129     u8 buswidth;
130     u32 window;
131@@ -334,7 +402,10 @@ struct bcma_drv_cc {
132     u16 fast_pwrup_delay;
133     struct bcma_chipcommon_pmu pmu;
134 #ifdef CONFIG_BCMA_DRIVER_MIPS
135- struct bcma_pflash pflash;
136+ enum bcma_flash_type flash_type;
137+ union {
138+ struct bcma_pflash pflash;
139+ };
140 
141     int nr_serial_ports;
142     struct bcma_serial_port serial_ports[4];
143

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