Root/target/linux/brcm47xx/patches-3.2/0037-bcma-constants-for-PCI-and-use-them.patch

1From 300efafa8e1381a208c723bb9d03d46bf29f1ec0 Mon Sep 17 00:00:00 2001
2From: Hauke Mehrtens <hauke@hauke-m.de>
3Date: Sat, 14 Jan 2012 20:02:15 +0100
4Subject: [PATCH 24/31] bcma: constants for PCI and use them
5
6There are loots of magic numbers used in the PCIe code. These constants
7are from the Broadcom SDK and will also used in the host controller.
8
9Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
10---
11 drivers/bcma/driver_pci.c | 124 +++++++++++++++++++---------------
12 include/linux/bcma/bcma_driver_pci.h | 85 +++++++++++++++++++++++
13 2 files changed, 155 insertions(+), 54 deletions(-)
14
15--- a/drivers/bcma/driver_pci.c
16+++ b/drivers/bcma/driver_pci.c
17@@ -4,6 +4,7 @@
18  *
19  * Copyright 2005, Broadcom Corporation
20  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
21+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
22  *
23  * Licensed under the GNU/GPL. See COPYING for details.
24  */
25@@ -18,38 +19,39 @@
26 
27 static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
28 {
29- pcicore_write32(pc, 0x130, address);
30- pcicore_read32(pc, 0x130);
31- return pcicore_read32(pc, 0x134);
32+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
33+ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
34+ return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
35 }
36 
37 #if 0
38 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
39 {
40- pcicore_write32(pc, 0x130, address);
41- pcicore_read32(pc, 0x130);
42- pcicore_write32(pc, 0x134, data);
43+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
44+ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
45+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
46 }
47 #endif
48 
49 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
50 {
51- const u16 mdio_control = 0x128;
52- const u16 mdio_data = 0x12C;
53     u32 v;
54     int i;
55 
56- v = (1 << 30); /* Start of Transaction */
57- v |= (1 << 28); /* Write Transaction */
58- v |= (1 << 17); /* Turnaround */
59- v |= (0x1F << 18);
60+ v = BCMA_CORE_PCI_MDIODATA_START;
61+ v |= BCMA_CORE_PCI_MDIODATA_WRITE;
62+ v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
63+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
64+ v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
65+ BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
66+ v |= BCMA_CORE_PCI_MDIODATA_TA;
67     v |= (phy << 4);
68- pcicore_write32(pc, mdio_data, v);
69+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
70 
71     udelay(10);
72     for (i = 0; i < 200; i++) {
73- v = pcicore_read32(pc, mdio_control);
74- if (v & 0x100 /* Trans complete */)
75+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
76+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
77             break;
78         msleep(1);
79     }
80@@ -57,79 +59,84 @@ static void bcma_pcie_mdio_set_phy(struc
81 
82 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
83 {
84- const u16 mdio_control = 0x128;
85- const u16 mdio_data = 0x12C;
86     int max_retries = 10;
87     u16 ret = 0;
88     u32 v;
89     int i;
90 
91- v = 0x80; /* Enable Preamble Sequence */
92- v |= 0x2; /* MDIO Clock Divisor */
93- pcicore_write32(pc, mdio_control, v);
94+ /* enable mdio access to SERDES */
95+ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
96+ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
97+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
98 
99     if (pc->core->id.rev >= 10) {
100         max_retries = 200;
101         bcma_pcie_mdio_set_phy(pc, device);
102+ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
103+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
104+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
105+ } else {
106+ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
107+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
108     }
109 
110- v = (1 << 30); /* Start of Transaction */
111- v |= (1 << 29); /* Read Transaction */
112- v |= (1 << 17); /* Turnaround */
113- if (pc->core->id.rev < 10)
114- v |= (u32)device << 22;
115- v |= (u32)address << 18;
116- pcicore_write32(pc, mdio_data, v);
117+ v = BCMA_CORE_PCI_MDIODATA_START;
118+ v |= BCMA_CORE_PCI_MDIODATA_READ;
119+ v |= BCMA_CORE_PCI_MDIODATA_TA;
120+
121+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
122     /* Wait for the device to complete the transaction */
123     udelay(10);
124     for (i = 0; i < max_retries; i++) {
125- v = pcicore_read32(pc, mdio_control);
126- if (v & 0x100 /* Trans complete */) {
127+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
128+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
129             udelay(10);
130- ret = pcicore_read32(pc, mdio_data);
131+ ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
132             break;
133         }
134         msleep(1);
135     }
136- pcicore_write32(pc, mdio_control, 0);
137+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
138     return ret;
139 }
140 
141 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
142                 u8 address, u16 data)
143 {
144- const u16 mdio_control = 0x128;
145- const u16 mdio_data = 0x12C;
146     int max_retries = 10;
147     u32 v;
148     int i;
149 
150- v = 0x80; /* Enable Preamble Sequence */
151- v |= 0x2; /* MDIO Clock Divisor */
152- pcicore_write32(pc, mdio_control, v);
153+ /* enable mdio access to SERDES */
154+ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
155+ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
156+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
157 
158     if (pc->core->id.rev >= 10) {
159         max_retries = 200;
160         bcma_pcie_mdio_set_phy(pc, device);
161+ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
162+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
163+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
164+ } else {
165+ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
166+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
167     }
168 
169- v = (1 << 30); /* Start of Transaction */
170- v |= (1 << 28); /* Write Transaction */
171- v |= (1 << 17); /* Turnaround */
172- if (pc->core->id.rev < 10)
173- v |= (u32)device << 22;
174- v |= (u32)address << 18;
175+ v = BCMA_CORE_PCI_MDIODATA_START;
176+ v |= BCMA_CORE_PCI_MDIODATA_WRITE;
177+ v |= BCMA_CORE_PCI_MDIODATA_TA;
178     v |= data;
179- pcicore_write32(pc, mdio_data, v);
180+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
181     /* Wait for the device to complete the transaction */
182     udelay(10);
183     for (i = 0; i < max_retries; i++) {
184- v = pcicore_read32(pc, mdio_control);
185- if (v & 0x100 /* Trans complete */)
186+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
187+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
188             break;
189         msleep(1);
190     }
191- pcicore_write32(pc, mdio_control, 0);
192+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
193 }
194 
195 /**************************************************
196@@ -138,20 +145,29 @@ static void bcma_pcie_mdio_write(struct
197 
198 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
199 {
200- return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
201+ u32 tmp;
202+
203+ tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
204+ if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
205+ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
206+ BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
207+ else
208+ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
209 }
210 
211 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
212 {
213- const u8 serdes_pll_device = 0x1D;
214- const u8 serdes_rx_device = 0x1F;
215     u16 tmp;
216 
217- bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
218- bcma_pcicore_polarity_workaround(pc));
219- tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
220- if (tmp & 0x4000)
221- bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
222+ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
223+ BCMA_CORE_PCI_SERDES_RX_CTRL,
224+ bcma_pcicore_polarity_workaround(pc));
225+ tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
226+ BCMA_CORE_PCI_SERDES_PLL_CTRL);
227+ if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
228+ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
229+ BCMA_CORE_PCI_SERDES_PLL_CTRL,
230+ tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
231 }
232 
233 /**************************************************
234--- a/include/linux/bcma/bcma_driver_pci.h
235+++ b/include/linux/bcma/bcma_driver_pci.h
236@@ -53,6 +53,35 @@ struct pci_dev;
237 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
238 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
239 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
240+#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
241+#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
242+#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
243+#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
244+#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
245+#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
246+#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
247+#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
248+#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
249+#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
250+#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
251+#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
252+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
253+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
254+#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
255+#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
256+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
257+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
258+#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
259+#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
260+#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
261+#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
262+#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
263+#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
264+#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
265+#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
266+#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
267+#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
268+#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
269 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
270 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
271 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
272@@ -72,6 +101,62 @@ struct pci_dev;
273 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
274 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
275 
276+/* PCIE protocol PHY diagnostic registers */
277+#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
278+#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
279+#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
280+#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
281+#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
282+#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
283+#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
284+#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
285+#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
286+#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
287+#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
288+#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
289+#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
290+#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
291+#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
292+#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
293+#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
294+
295+/* PCIE protocol DLLP diagnostic registers */
296+#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
297+#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
298+#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
299+#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
300+#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
301+#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
302+#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
303+#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
304+#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
305+#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
306+#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
307+#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
308+#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
309+#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
310+#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
311+#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
312+#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
313+#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
314+#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
315+#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
316+#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
317+#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
318+#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
319+
320+/* SERDES RX registers */
321+#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
322+#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
323+#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
324+#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
325+#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
326+#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
327+
328+/* SERDES PLL registers */
329+#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
330+#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
331+
332 /* PCIcore specific boardflags */
333 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
334 
335

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