Root/target/linux/brcm63xx/patches-3.2/240-spi.patch

1--- a/arch/mips/bcm63xx/cpu.c
2+++ b/arch/mips/bcm63xx/cpu.c
3@@ -58,6 +58,7 @@ static const unsigned long bcm96338_regs
4 
5 static const int bcm96338_irqs[] = {
6     [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
7+ [IRQ_SPI] = BCM_6338_SPI_IRQ,
8     [IRQ_UART0] = BCM_6338_UART0_IRQ,
9     [IRQ_DSL] = BCM_6338_DSL_IRQ,
10     [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
11@@ -132,6 +133,7 @@ static const unsigned long bcm96348_regs
12 
13 static const int bcm96348_irqs[] = {
14     [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
15+ [IRQ_SPI] = BCM_6348_SPI_IRQ,
16     [IRQ_UART0] = BCM_6348_UART0_IRQ,
17     [IRQ_DSL] = BCM_6348_DSL_IRQ,
18     [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
19@@ -175,6 +177,7 @@ static const unsigned long bcm96358_regs
20 
21 static const int bcm96358_irqs[] = {
22     [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
23+ [IRQ_SPI] = BCM_6358_SPI_IRQ,
24     [IRQ_UART0] = BCM_6358_UART0_IRQ,
25     [IRQ_UART1] = BCM_6358_UART1_IRQ,
26     [IRQ_DSL] = BCM_6358_DSL_IRQ,
27--- /dev/null
28+++ b/arch/mips/bcm63xx/dev-spi.c
29@@ -0,0 +1,99 @@
30+/*
31+ * This file is subject to the terms and conditions of the GNU General Public
32+ * License. See the file "COPYING" in the main directory of this archive
33+ * for more details.
34+ *
35+ * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
36+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
37+ */
38+
39+#include <linux/init.h>
40+#include <linux/kernel.h>
41+#include <linux/platform_device.h>
42+#include <linux/export.h>
43+
44+#include <bcm63xx_cpu.h>
45+#include <bcm63xx_dev_spi.h>
46+#include <bcm63xx_regs.h>
47+
48+#ifdef BCMCPU_RUNTIME_DETECT
49+/*
50+ * register offsets
51+ */
52+static const unsigned long bcm96338_regs_spi[] = {
53+ __GEN_SPI_REGS_TABLE(6338)
54+};
55+
56+static const unsigned long bcm96348_regs_spi[] = {
57+ __GEN_SPI_REGS_TABLE(6348)
58+};
59+
60+static const unsigned long bcm96358_regs_spi[] = {
61+ __GEN_SPI_REGS_TABLE(6358)
62+};
63+
64+const unsigned long *bcm63xx_regs_spi;
65+EXPORT_SYMBOL(bcm63xx_regs_spi);
66+
67+static __init void bcm63xx_spi_regs_init(void)
68+{
69+ if (BCMCPU_IS_6338())
70+ bcm63xx_regs_spi = bcm96338_regs_spi;
71+ if (BCMCPU_IS_6348())
72+ bcm63xx_regs_spi = bcm96348_regs_spi;
73+ if (BCMCPU_IS_6358())
74+ bcm63xx_regs_spi = bcm96358_regs_spi;
75+}
76+#else
77+static __init void bcm63xx_spi_regs_init(void) { }
78+#endif
79+
80+static struct resource spi_resources[] = {
81+ {
82+ .start = -1, /* filled at runtime */
83+ .end = -1, /* filled at runtime */
84+ .flags = IORESOURCE_MEM,
85+ },
86+ {
87+ .start = -1, /* filled at runtime */
88+ .flags = IORESOURCE_IRQ,
89+ },
90+};
91+
92+static struct bcm63xx_spi_pdata spi_pdata = {
93+ .bus_num = 0,
94+ .num_chipselect = 8,
95+ .speed_hz = 50000000, /* Fclk */
96+};
97+
98+static struct platform_device bcm63xx_spi_device = {
99+ .name = "bcm63xx-spi",
100+ .id = 0,
101+ .num_resources = ARRAY_SIZE(spi_resources),
102+ .resource = spi_resources,
103+ .dev = {
104+ .platform_data = &spi_pdata,
105+ },
106+};
107+
108+int __init bcm63xx_spi_register(void)
109+{
110+ spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
111+ spi_resources[0].end = spi_resources[0].start;
112+ spi_resources[0].end += RSET_SPI_SIZE - 1;
113+ spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
114+
115+ if (BCMCPU_IS_6345())
116+ return -ENODEV;
117+
118+ /* Fill in platform data */
119+ if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
120+ spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
121+
122+ if (BCMCPU_IS_6358())
123+ spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
124+
125+ bcm63xx_spi_regs_init();
126+
127+ return platform_device_register(&bcm63xx_spi_device);
128+}
129--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
130+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
131@@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
132 #define RSET_WDT_SIZE 12
133 #define RSET_ENET_SIZE 2048
134 #define RSET_ENETDMA_SIZE 2048
135+#define RSET_SPI_SIZE 256
136 #define RSET_UART_SIZE 24
137 #define RSET_UDC_SIZE 256
138 #define RSET_OHCI_SIZE 256
139@@ -214,7 +215,7 @@ enum bcm63xx_regs_set {
140 #define BCM_6358_UART0_BASE (0xfffe0100)
141 #define BCM_6358_UART1_BASE (0xfffe0120)
142 #define BCM_6358_GPIO_BASE (0xfffe0080)
143-#define BCM_6358_SPI_BASE (0xdeadbeef)
144+#define BCM_6358_SPI_BASE (0xfffe0800)
145 #define BCM_6358_UDC0_BASE (0xfffe0400)
146 #define BCM_6358_OHCI0_BASE (0xfffe1400)
147 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
148@@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
149  */
150 enum bcm63xx_irq {
151     IRQ_TIMER = 0,
152+ IRQ_SPI,
153     IRQ_UART0,
154     IRQ_UART1,
155     IRQ_DSL,
156@@ -507,6 +509,7 @@ enum bcm63xx_irq {
157  * 6348 irqs
158  */
159 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
160+#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
161 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
162 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
163 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
164@@ -531,6 +534,7 @@ enum bcm63xx_irq {
165  * 6358 irqs
166  */
167 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
168+#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
169 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
170 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
171 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
172--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
173+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
174@@ -804,4 +804,116 @@
175 #define DMIPSPLLCFG_N2_SHIFT 29
176 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
177 
178+/*************************************************************************
179+ * _REG relative to RSET_SPI
180+ *************************************************************************/
181+
182+/* BCM 6338 SPI core */
183+#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
184+#define SPI_BCM_6338_SPI_INT_STATUS 0x02
185+#define SPI_BCM_6338_SPI_INT_MASK_ST 0x03
186+#define SPI_BCM_6338_SPI_INT_MASK 0x04
187+#define SPI_BCM_6338_SPI_ST 0x05
188+#define SPI_BCM_6338_SPI_CLK_CFG 0x06
189+#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
190+#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
191+#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
192+#define SPI_BCM_6338_SPI_MSG_CTL 0x40
193+#define SPI_BCM_6338_SPI_MSG_DATA 0x41
194+#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
195+#define SPI_BCM_6338_SPI_RX_DATA 0x80
196+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
197+
198+/* BCM 6348 SPI core */
199+#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
200+#define SPI_BCM_6348_SPI_INT_STATUS 0x02
201+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
202+#define SPI_BCM_6348_SPI_INT_MASK 0x04
203+#define SPI_BCM_6348_SPI_ST 0x05
204+#define SPI_BCM_6348_SPI_CLK_CFG 0x06
205+#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
206+#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
207+#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
208+#define SPI_BCM_6348_SPI_MSG_CTL 0x40
209+#define SPI_BCM_6348_SPI_MSG_DATA 0x41
210+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
211+#define SPI_BCM_6348_SPI_RX_DATA 0x80
212+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
213+
214+/* BCM 6358 SPI core */
215+#define SPI_BCM_6358_SPI_MSG_CTL 0x00 /* 16-bits register */
216+
217+#define SPI_BCM_6358_SPI_MSG_DATA 0x02
218+#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
219+
220+#define SPI_BCM_6358_SPI_RX_DATA 0x400
221+#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
222+
223+#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
224+
225+#define SPI_BCM_6358_SPI_INT_STATUS 0x702
226+#define SPI_BCM_6358_SPI_INT_MASK_ST 0x703
227+
228+#define SPI_BCM_6358_SPI_INT_MASK 0x704
229+
230+#define SPI_BCM_6358_SPI_ST 0x705
231+
232+#define SPI_BCM_6358_SPI_CLK_CFG 0x706
233+
234+#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
235+#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
236+#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
237+
238+/* Shared SPI definitions */
239+
240+/* Message configuration */
241+#define SPI_FD_RW 0x00
242+#define SPI_HD_W 0x01
243+#define SPI_HD_R 0x02
244+#define SPI_BYTE_CNT_SHIFT 0
245+#define SPI_MSG_TYPE_SHIFT 14
246+
247+/* Command */
248+#define SPI_CMD_NOOP 0x00
249+#define SPI_CMD_SOFT_RESET 0x01
250+#define SPI_CMD_HARD_RESET 0x02
251+#define SPI_CMD_START_IMMEDIATE 0x03
252+#define SPI_CMD_COMMAND_SHIFT 0
253+#define SPI_CMD_COMMAND_MASK 0x000f
254+#define SPI_CMD_DEVICE_ID_SHIFT 4
255+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
256+#define SPI_CMD_ONE_BYTE_SHIFT 11
257+#define SPI_CMD_ONE_WIRE_SHIFT 12
258+#define SPI_DEV_ID_0 0
259+#define SPI_DEV_ID_1 1
260+#define SPI_DEV_ID_2 2
261+#define SPI_DEV_ID_3 3
262+
263+/* Interrupt mask */
264+#define SPI_INTR_CMD_DONE 0x01
265+#define SPI_INTR_RX_OVERFLOW 0x02
266+#define SPI_INTR_TX_UNDERFLOW 0x04
267+#define SPI_INTR_TX_OVERFLOW 0x08
268+#define SPI_INTR_RX_UNDERFLOW 0x10
269+#define SPI_INTR_CLEAR_ALL 0x1f
270+
271+/* Status */
272+#define SPI_RX_EMPTY 0x02
273+#define SPI_CMD_BUSY 0x04
274+#define SPI_SERIAL_BUSY 0x08
275+
276+/* Clock configuration */
277+#define SPI_CLK_20MHZ 0x00
278+#define SPI_CLK_0_391MHZ 0x01
279+#define SPI_CLK_0_781MHZ 0x02 /* default */
280+#define SPI_CLK_1_563MHZ 0x03
281+#define SPI_CLK_3_125MHZ 0x04
282+#define SPI_CLK_6_250MHZ 0x05
283+#define SPI_CLK_12_50MHZ 0x06
284+#define SPI_CLK_25MHZ 0x07
285+#define SPI_CLK_MASK 0x07
286+#define SPI_SSOFFTIME_MASK 0x38
287+#define SPI_SSOFFTIME_SHIFT 3
288+#define SPI_BYTE_SWAP 0x80
289+
290 #endif /* BCM63XX_REGS_H_ */
291--- /dev/null
292+++ b/drivers/spi/bcm63xx_spi.c
293@@ -0,0 +1,496 @@
294+/*
295+ * Broadcom BCM63xx SPI controller support
296+ *
297+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
298+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
299+ *
300+ * This program is free software; you can redistribute it and/or
301+ * modify it under the terms of the GNU General Public License
302+ * as published by the Free Software Foundation; either version 2
303+ * of the License, or (at your option) any later version.
304+ *
305+ * This program is distributed in the hope that it will be useful,
306+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
307+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
308+ * GNU General Public License for more details.
309+ *
310+ * You should have received a copy of the GNU General Public License
311+ * along with this program; if not, write to the
312+ * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
313+ */
314+
315+#include <linux/kernel.h>
316+#include <linux/init.h>
317+#include <linux/clk.h>
318+#include <linux/module.h>
319+#include <linux/platform_device.h>
320+#include <linux/delay.h>
321+#include <linux/interrupt.h>
322+#include <linux/spi/spi.h>
323+#include <linux/completion.h>
324+#include <linux/err.h>
325+
326+#include <bcm63xx_dev_spi.h>
327+
328+#define PFX KBUILD_MODNAME
329+#define DRV_VER "0.1.2"
330+
331+struct bcm63xx_spi {
332+ spinlock_t lock;
333+ int stopping;
334+ struct completion done;
335+
336+ void __iomem *regs;
337+ int irq;
338+
339+ /* Platform data */
340+ u32 speed_hz;
341+ unsigned fifo_size;
342+
343+ /* Data buffers */
344+ const unsigned char *tx_ptr;
345+ unsigned char *rx_ptr;
346+
347+ /* data iomem */
348+ u8 __iomem *tx_io;
349+ const u8 __iomem *rx_io;
350+
351+ int remaining_bytes;
352+
353+ struct clk *clk;
354+ struct platform_device *pdev;
355+};
356+
357+static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
358+ unsigned int offset)
359+{
360+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
361+}
362+
363+static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
364+ unsigned int offset)
365+{
366+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
367+}
368+
369+static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
370+ u8 value, unsigned int offset)
371+{
372+ bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
373+}
374+
375+static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
376+ u16 value, unsigned int offset)
377+{
378+ bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
379+}
380+
381+static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
382+ struct spi_transfer *t)
383+{
384+ u8 bits_per_word;
385+ u8 clk_cfg;
386+ u32 hz;
387+ unsigned int div;
388+
389+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
390+
391+ bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
392+ hz = (t) ? t->speed_hz : spi->max_speed_hz;
393+ if (bits_per_word != 8) {
394+ dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
395+ __func__, bits_per_word);
396+ return -EINVAL;
397+ }
398+
399+ if (spi->chip_select > spi->master->num_chipselect) {
400+ dev_err(&spi->dev, "%s, unsupported slave %d\n",
401+ __func__, spi->chip_select);
402+ return -EINVAL;
403+ }
404+
405+ /* Check clock setting */
406+ div = (bs->speed_hz / hz);
407+ switch (div) {
408+ case 2:
409+ clk_cfg = SPI_CLK_25MHZ;
410+ break;
411+ case 4:
412+ clk_cfg = SPI_CLK_12_50MHZ;
413+ break;
414+ case 8:
415+ clk_cfg = SPI_CLK_6_250MHZ;
416+ break;
417+ case 16:
418+ clk_cfg = SPI_CLK_3_125MHZ;
419+ break;
420+ case 32:
421+ clk_cfg = SPI_CLK_1_563MHZ;
422+ break;
423+ case 64:
424+ clk_cfg = SPI_CLK_0_781MHZ;
425+ break;
426+ case 128:
427+ default:
428+ /* Set to slowest mode for compatibility */
429+ clk_cfg = SPI_CLK_0_391MHZ;
430+ break;
431+ }
432+
433+ bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
434+ dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
435+ div, hz, clk_cfg);
436+
437+ return 0;
438+}
439+
440+/* the spi->mode bits understood by this driver: */
441+#define MODEBITS (SPI_CPOL | SPI_CPHA)
442+
443+static int bcm63xx_spi_setup(struct spi_device *spi)
444+{
445+ struct bcm63xx_spi *bs;
446+ int ret;
447+
448+ bs = spi_master_get_devdata(spi->master);
449+
450+ if (bs->stopping)
451+ return -ESHUTDOWN;
452+
453+ if (!spi->bits_per_word)
454+ spi->bits_per_word = 8;
455+
456+ if (spi->mode & ~MODEBITS) {
457+ dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
458+ __func__, spi->mode & ~MODEBITS);
459+ return -EINVAL;
460+ }
461+
462+ ret = bcm63xx_spi_setup_transfer(spi, NULL);
463+ if (ret < 0) {
464+ dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
465+ spi->mode & ~MODEBITS);
466+ return ret;
467+ }
468+
469+ dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
470+ __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
471+
472+ return 0;
473+}
474+
475+/* Fill the TX FIFO with as many bytes as possible */
476+static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
477+{
478+ u8 size;
479+
480+ /* Fill the Tx FIFO with as many bytes as possible */
481+ size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
482+ bs->fifo_size;
483+ memcpy_toio(bs->tx_io, bs->tx_ptr, size);
484+ bs->remaining_bytes -= size;
485+}
486+
487+static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
488+{
489+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
490+ u16 msg_ctl;
491+ u16 cmd;
492+
493+ dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
494+ t->tx_buf, t->rx_buf, t->len);
495+
496+ /* Transmitter is inhibited */
497+ bs->tx_ptr = t->tx_buf;
498+ bs->rx_ptr = t->rx_buf;
499+ init_completion(&bs->done);
500+
501+ if (t->tx_buf) {
502+ bs->remaining_bytes = t->len;
503+ bcm63xx_spi_fill_tx_fifo(bs);
504+ }
505+
506+ /* Enable the command done interrupt which
507+ * we use to determine completion of a command */
508+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
509+
510+ /* Fill in the Message control register */
511+ msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
512+
513+ if (t->rx_buf && t->tx_buf)
514+ msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
515+ else if (t->rx_buf)
516+ msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
517+ else if (t->tx_buf)
518+ msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
519+
520+ bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
521+
522+ /* Issue the transfer */
523+ cmd = SPI_CMD_START_IMMEDIATE;
524+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
525+ cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
526+ bcm_spi_writew(bs, cmd, SPI_CMD);
527+ wait_for_completion(&bs->done);
528+
529+ /* Disable the CMD_DONE interrupt */
530+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
531+
532+ return t->len - bs->remaining_bytes;
533+}
534+
535+static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
536+{
537+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
538+ struct spi_transfer *t;
539+ int ret = 0;
540+
541+ if (unlikely(list_empty(&m->transfers)))
542+ return -EINVAL;
543+
544+ if (bs->stopping)
545+ return -ESHUTDOWN;
546+
547+ list_for_each_entry(t, &m->transfers, transfer_list) {
548+ ret += bcm63xx_txrx_bufs(spi, t);
549+ }
550+
551+ m->complete(m->context);
552+
553+ return ret;
554+}
555+
556+/* This driver supports single master mode only. Hence
557+ * CMD_DONE is the only interrupt we care about
558+ */
559+static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
560+{
561+ struct spi_master *master = (struct spi_master *)dev_id;
562+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
563+ u8 intr;
564+ u16 cmd;
565+
566+ /* Read interupts and clear them immediately */
567+ intr = bcm_spi_readb(bs, SPI_INT_STATUS);
568+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
569+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
570+
571+ /* A tansfer completed */
572+ if (intr & SPI_INTR_CMD_DONE) {
573+ u8 rx_tail;
574+
575+ rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
576+
577+ /* Read out all the data */
578+ if (rx_tail)
579+ memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
580+
581+ /* See if there is more data to send */
582+ if (bs->remaining_bytes > 0) {
583+ bcm63xx_spi_fill_tx_fifo(bs);
584+
585+ /* Start the transfer */
586+ bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
587+ SPI_MSG_CTL);
588+ cmd = bcm_spi_readw(bs, SPI_CMD);
589+ cmd |= SPI_CMD_START_IMMEDIATE;
590+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
591+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
592+ bcm_spi_writew(bs, cmd, SPI_CMD);
593+ } else {
594+ complete(&bs->done);
595+ }
596+ }
597+
598+ return IRQ_HANDLED;
599+}
600+
601+
602+static int __init bcm63xx_spi_probe(struct platform_device *pdev)
603+{
604+ struct resource *r;
605+ struct device *dev = &pdev->dev;
606+ struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
607+ int irq;
608+ struct spi_master *master;
609+ struct clk *clk;
610+ struct bcm63xx_spi *bs;
611+ int ret;
612+
613+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
614+ if (!r) {
615+ dev_err(dev, "no iomem\n");
616+ ret = -ENXIO;
617+ goto out;
618+ }
619+
620+ irq = platform_get_irq(pdev, 0);
621+ if (irq < 0) {
622+ dev_err(dev, "no irq\n");
623+ ret = -ENXIO;
624+ goto out;
625+ }
626+
627+ clk = clk_get(dev, "spi");
628+ if (IS_ERR(clk)) {
629+ dev_err(dev, "no clock for device\n");
630+ ret = -ENODEV;
631+ goto out;
632+ }
633+
634+ master = spi_alloc_master(dev, sizeof(*bs));
635+ if (!master) {
636+ dev_err(dev, "out of memory\n");
637+ ret = -ENOMEM;
638+ goto out_free;
639+ }
640+
641+ bs = spi_master_get_devdata(master);
642+ init_completion(&bs->done);
643+
644+ platform_set_drvdata(pdev, master);
645+ bs->pdev = pdev;
646+
647+ if (!request_mem_region(r->start, r->end - r->start, PFX)) {
648+ dev_err(dev, "iomem request failed\n");
649+ ret = -ENXIO;
650+ goto out_put_master;
651+ }
652+
653+ bs->regs = ioremap_nocache(r->start, r->end - r->start);
654+ if (!bs->regs) {
655+ dev_err(dev, "unable to ioremap regs\n");
656+ ret = -ENOMEM;
657+ goto out_put_master;
658+ }
659+ bs->irq = irq;
660+ bs->clk = clk;
661+ bs->fifo_size = pdata->fifo_size;
662+
663+ ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
664+ if (ret) {
665+ dev_err(dev, "unable to request irq\n");
666+ goto out_unmap;
667+ }
668+
669+ master->bus_num = pdata->bus_num;
670+ master->num_chipselect = pdata->num_chipselect;
671+ master->setup = bcm63xx_spi_setup;
672+ master->transfer = bcm63xx_transfer;
673+ bs->speed_hz = pdata->speed_hz;
674+ bs->stopping = 0;
675+ bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
676+ bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
677+ spin_lock_init(&bs->lock);
678+
679+ /* Initialize hardware */
680+ clk_enable(bs->clk);
681+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
682+
683+ /* register and we are done */
684+ ret = spi_register_master(master);
685+ if (ret) {
686+ dev_err(dev, "spi register failed\n");
687+ goto out_reset_hw;
688+ }
689+
690+ dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
691+ r->start, irq, bs->fifo_size, DRV_VER);
692+
693+ return 0;
694+
695+out_reset_hw:
696+ clk_disable(clk);
697+ free_irq(irq, master);
698+out_unmap:
699+ iounmap(bs->regs);
700+out_put_master:
701+ spi_master_put(master);
702+out_free:
703+ clk_put(clk);
704+out:
705+ return ret;
706+}
707+
708+static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
709+{
710+ struct spi_master *master = platform_get_drvdata(pdev);
711+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
712+ struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
713+
714+ /* reset spi block */
715+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
716+ spin_lock(&bs->lock);
717+ bs->stopping = 1;
718+
719+ /* HW shutdown */
720+ clk_disable(bs->clk);
721+ clk_put(bs->clk);
722+
723+ spin_unlock(&bs->lock);
724+
725+ free_irq(bs->irq, master);
726+ iounmap(bs->regs);
727+ release_mem_region(r->start, r->end - r->start);
728+ platform_set_drvdata(pdev, 0);
729+ spi_unregister_master(master);
730+
731+ return 0;
732+}
733+
734+#ifdef CONFIG_PM
735+static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
736+{
737+ struct spi_master *master = platform_get_drvdata(pdev);
738+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
739+
740+ clk_disable(bs->clk);
741+
742+ return 0;
743+}
744+
745+static int bcm63xx_spi_resume(struct platform_device *pdev)
746+{
747+ struct spi_master *master = platform_get_drvdata(pdev);
748+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
749+
750+ clk_enable(bs->clk);
751+
752+ return 0;
753+}
754+#else
755+#define bcm63xx_spi_suspend NULL
756+#define bcm63xx_spi_resume NULL
757+#endif
758+
759+static struct platform_driver bcm63xx_spi_driver = {
760+ .driver = {
761+ .name = "bcm63xx-spi",
762+ .owner = THIS_MODULE,
763+ },
764+ .probe = bcm63xx_spi_probe,
765+ .remove = __exit_p(bcm63xx_spi_remove),
766+ .suspend = bcm63xx_spi_suspend,
767+ .resume = bcm63xx_spi_resume,
768+};
769+
770+
771+static int __init bcm63xx_spi_init(void)
772+{
773+ return platform_driver_register(&bcm63xx_spi_driver);
774+}
775+
776+static void __exit bcm63xx_spi_exit(void)
777+{
778+ platform_driver_unregister(&bcm63xx_spi_driver);
779+}
780+
781+module_init(bcm63xx_spi_init);
782+module_exit(bcm63xx_spi_exit);
783+
784+MODULE_ALIAS("platform:bcm63xx_spi");
785+MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
786+MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
787+MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
788+MODULE_LICENSE("GPL");
789+MODULE_VERSION(DRV_VER);
790--- a/drivers/spi/Kconfig
791+++ b/drivers/spi/Kconfig
792@@ -74,6 +74,12 @@ config SPI_ATMEL
793       This selects a driver for the Atmel SPI Controller, present on
794       many AT32 (AVR32) and AT91 (ARM) chips.
795 
796+config SPI_BCM63XX
797+ tristate "Broadcom BCM63xx SPI controller"
798+ depends on BCM63XX
799+ help
800+ This is the SPI controller master driver for Broadcom BCM63xx SoC.
801+
802 config SPI_BFIN
803     tristate "SPI controller driver for ADI Blackfin5xx"
804     depends on BLACKFIN
805--- a/drivers/spi/Makefile
806+++ b/drivers/spi/Makefile
807@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.
808 obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
809 obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
810 obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
811+obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
812 obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
813 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
814 obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
815--- /dev/null
816+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
817@@ -0,0 +1,85 @@
818+#ifndef BCM63XX_DEV_SPI_H
819+#define BCM63XX_DEV_SPI_H
820+
821+#include <linux/types.h>
822+#include <bcm63xx_io.h>
823+#include <bcm63xx_regs.h>
824+
825+int __init bcm63xx_spi_register(void);
826+
827+struct bcm63xx_spi_pdata {
828+ unsigned int fifo_size;
829+ int bus_num;
830+ int num_chipselect;
831+ u32 speed_hz;
832+};
833+
834+enum bcm63xx_regs_spi {
835+ SPI_CMD,
836+ SPI_INT_STATUS,
837+ SPI_INT_MASK_ST,
838+ SPI_INT_MASK,
839+ SPI_ST,
840+ SPI_CLK_CFG,
841+ SPI_FILL_BYTE,
842+ SPI_MSG_TAIL,
843+ SPI_RX_TAIL,
844+ SPI_MSG_CTL,
845+ SPI_MSG_DATA,
846+ SPI_RX_DATA,
847+};
848+
849+#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
850+ case SPI_## __rset: \
851+ return SPI_BCM_## __cpu ##_SPI_## __rset;
852+
853+#define __GEN_SPI_RSET(__cpu) \
854+ switch (reg) { \
855+ __GEN_SPI_RSET_BASE(__cpu, CMD) \
856+ __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
857+ __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
858+ __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
859+ __GEN_SPI_RSET_BASE(__cpu, ST) \
860+ __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
861+ __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
862+ __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
863+ __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
864+ __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
865+ __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
866+ __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
867+ }
868+
869+#define __GEN_SPI_REGS_TABLE(__cpu) \
870+ [SPI_CMD] = SPI_BCM_## __cpu ##_SPI_CMD, \
871+ [SPI_INT_STATUS] = SPI_BCM_## __cpu ##_SPI_INT_STATUS, \
872+ [SPI_INT_MASK_ST] = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST, \
873+ [SPI_INT_MASK] = SPI_BCM_## __cpu ##_SPI_INT_MASK, \
874+ [SPI_ST] = SPI_BCM_## __cpu ##_SPI_ST, \
875+ [SPI_CLK_CFG] = SPI_BCM_## __cpu ##_SPI_CLK_CFG, \
876+ [SPI_FILL_BYTE] = SPI_BCM_## __cpu ##_SPI_FILL_BYTE, \
877+ [SPI_MSG_TAIL] = SPI_BCM_## __cpu ##_SPI_MSG_TAIL, \
878+ [SPI_RX_TAIL] = SPI_BCM_## __cpu ##_SPI_RX_TAIL, \
879+ [SPI_MSG_CTL] = SPI_BCM_## __cpu ##_SPI_MSG_CTL, \
880+ [SPI_MSG_DATA] = SPI_BCM_## __cpu ##_SPI_MSG_DATA, \
881+ [SPI_RX_DATA] = SPI_BCM_## __cpu ##_SPI_RX_DATA,
882+
883+static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
884+{
885+#ifdef BCMCPU_RUNTIME_DETECT
886+ extern const unsigned long *bcm63xx_regs_spi;
887+ return bcm63xx_regs_spi[reg];
888+#else
889+#ifdef CONFIG_BCM63XX_CPU_6338
890+ __GEN_SPI_RSET(6338)
891+#endif
892+#ifdef CONFIG_BCM63XX_CPU_6348
893+ __GEN_SPI_RSET(6348)
894+#endif
895+#ifdef CONFIG_BCM63XX_CPU_6358
896+ __GEN_SPI_RSET(6358)
897+#endif
898+#endif
899+ return 0;
900+}
901+
902+#endif /* BCM63XX_DEV_SPI_H */
903--- a/arch/mips/bcm63xx/Makefile
904+++ b/arch/mips/bcm63xx/Makefile
905@@ -1,6 +1,6 @@
906 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
907            dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
908- dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
909+ dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
910 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
911 
912 obj-y += boards/
913--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
914+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
915@@ -31,6 +31,7 @@
916 #include <bcm63xx_dev_usb_ohci.h>
917 #include <bcm63xx_dev_usb_ehci.h>
918 #include <bcm63xx_dev_usb_udc.h>
919+#include <bcm63xx_dev_spi.h>
920 #include <board_bcm963xx.h>
921 
922 #define PFX "board_bcm963xx: "
923@@ -934,6 +935,8 @@ int __init board_register_devices(void)
924     if (board.num_spis)
925         spi_register_board_info(board.spis, board.num_spis);
926 
927+ bcm63xx_spi_register();
928+
929     /* read base address of boot chip select (0) */
930     val = bcm_mpi_readl(MPI_CSBASE_REG(0));
931     val &= MPI_CSBASE_BASE_MASK;
932

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