| 1 | --- a/drivers/ssb/main.c |
| 2 | +++ b/drivers/ssb/main.c |
| 3 | @@ -3,7 +3,7 @@ |
| 4 | * Subsystem core |
| 5 | * |
| 6 | * Copyright 2005, Broadcom Corporation |
| 7 | - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> |
| 8 | + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
| 9 | * |
| 10 | * Licensed under the GNU/GPL. See COPYING for details. |
| 11 | */ |
| 12 | @@ -12,6 +12,7 @@ |
| 13 | |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/io.h> |
| 16 | +#include <linux/module.h> |
| 17 | #include <linux/ssb/ssb.h> |
| 18 | #include <linux/ssb/ssb_regs.h> |
| 19 | #include <linux/ssb/ssb_driver_gige.h> |
| 20 | @@ -384,6 +385,35 @@ static int ssb_device_uevent(struct devi |
| 21 | ssb_dev->id.revision); |
| 22 | } |
| 23 | |
| 24 | +#define ssb_config_attr(attrib, field, format_string) \ |
| 25 | +static ssize_t \ |
| 26 | +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ |
| 27 | +{ \ |
| 28 | + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ |
| 29 | +} |
| 30 | + |
| 31 | +ssb_config_attr(core_num, core_index, "%u\n") |
| 32 | +ssb_config_attr(coreid, id.coreid, "0x%04x\n") |
| 33 | +ssb_config_attr(vendor, id.vendor, "0x%04x\n") |
| 34 | +ssb_config_attr(revision, id.revision, "%u\n") |
| 35 | +ssb_config_attr(irq, irq, "%u\n") |
| 36 | +static ssize_t |
| 37 | +name_show(struct device *dev, struct device_attribute *attr, char *buf) |
| 38 | +{ |
| 39 | + return sprintf(buf, "%s\n", |
| 40 | + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); |
| 41 | +} |
| 42 | + |
| 43 | +static struct device_attribute ssb_device_attrs[] = { |
| 44 | + __ATTR_RO(name), |
| 45 | + __ATTR_RO(core_num), |
| 46 | + __ATTR_RO(coreid), |
| 47 | + __ATTR_RO(vendor), |
| 48 | + __ATTR_RO(revision), |
| 49 | + __ATTR_RO(irq), |
| 50 | + __ATTR_NULL, |
| 51 | +}; |
| 52 | + |
| 53 | static struct bus_type ssb_bustype = { |
| 54 | .name = "ssb", |
| 55 | .match = ssb_bus_match, |
| 56 | @@ -393,6 +423,7 @@ static struct bus_type ssb_bustype = { |
| 57 | .suspend = ssb_device_suspend, |
| 58 | .resume = ssb_device_resume, |
| 59 | .uevent = ssb_device_uevent, |
| 60 | + .dev_attrs = ssb_device_attrs, |
| 61 | }; |
| 62 | |
| 63 | static void ssb_buses_lock(void) |
| 64 | @@ -528,7 +559,7 @@ error: |
| 65 | } |
| 66 | |
| 67 | /* Needs ssb_buses_lock() */ |
| 68 | -static int ssb_attach_queued_buses(void) |
| 69 | +static int __devinit ssb_attach_queued_buses(void) |
| 70 | { |
| 71 | struct ssb_bus *bus, *n; |
| 72 | int err = 0; |
| 73 | @@ -739,9 +770,9 @@ out: |
| 74 | return err; |
| 75 | } |
| 76 | |
| 77 | -static int ssb_bus_register(struct ssb_bus *bus, |
| 78 | - ssb_invariants_func_t get_invariants, |
| 79 | - unsigned long baseaddr) |
| 80 | +static int __devinit ssb_bus_register(struct ssb_bus *bus, |
| 81 | + ssb_invariants_func_t get_invariants, |
| 82 | + unsigned long baseaddr) |
| 83 | { |
| 84 | int err; |
| 85 | |
| 86 | @@ -822,8 +853,8 @@ err_disable_xtal: |
| 87 | } |
| 88 | |
| 89 | #ifdef CONFIG_SSB_PCIHOST |
| 90 | -int ssb_bus_pcibus_register(struct ssb_bus *bus, |
| 91 | - struct pci_dev *host_pci) |
| 92 | +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus, |
| 93 | + struct pci_dev *host_pci) |
| 94 | { |
| 95 | int err; |
| 96 | |
| 97 | @@ -846,9 +877,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register); |
| 98 | #endif /* CONFIG_SSB_PCIHOST */ |
| 99 | |
| 100 | #ifdef CONFIG_SSB_PCMCIAHOST |
| 101 | -int ssb_bus_pcmciabus_register(struct ssb_bus *bus, |
| 102 | - struct pcmcia_device *pcmcia_dev, |
| 103 | - unsigned long baseaddr) |
| 104 | +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus, |
| 105 | + struct pcmcia_device *pcmcia_dev, |
| 106 | + unsigned long baseaddr) |
| 107 | { |
| 108 | int err; |
| 109 | |
| 110 | @@ -868,8 +899,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register |
| 111 | #endif /* CONFIG_SSB_PCMCIAHOST */ |
| 112 | |
| 113 | #ifdef CONFIG_SSB_SDIOHOST |
| 114 | -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, |
| 115 | - unsigned int quirks) |
| 116 | +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus, |
| 117 | + struct sdio_func *func, |
| 118 | + unsigned int quirks) |
| 119 | { |
| 120 | int err; |
| 121 | |
| 122 | @@ -889,9 +921,9 @@ int ssb_bus_sdiobus_register(struct ssb_ |
| 123 | EXPORT_SYMBOL(ssb_bus_sdiobus_register); |
| 124 | #endif /* CONFIG_SSB_PCMCIAHOST */ |
| 125 | |
| 126 | -int ssb_bus_ssbbus_register(struct ssb_bus *bus, |
| 127 | - unsigned long baseaddr, |
| 128 | - ssb_invariants_func_t get_invariants) |
| 129 | +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus, |
| 130 | + unsigned long baseaddr, |
| 131 | + ssb_invariants_func_t get_invariants) |
| 132 | { |
| 133 | int err; |
| 134 | |
| 135 | @@ -972,8 +1004,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 |
| 136 | switch (plltype) { |
| 137 | case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ |
| 138 | if (m & SSB_CHIPCO_CLK_T6_MMASK) |
| 139 | - return SSB_CHIPCO_CLK_T6_M0; |
| 140 | - return SSB_CHIPCO_CLK_T6_M1; |
| 141 | + return SSB_CHIPCO_CLK_T6_M1; |
| 142 | + return SSB_CHIPCO_CLK_T6_M0; |
| 143 | case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ |
| 144 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ |
| 145 | case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ |
| 146 | @@ -1088,23 +1120,22 @@ static u32 ssb_tmslow_reject_bitmask(str |
| 147 | { |
| 148 | u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; |
| 149 | |
| 150 | - /* The REJECT bit changed position in TMSLOW between |
| 151 | - * Backplane revisions. */ |
| 152 | + /* The REJECT bit seems to be different for Backplane rev 2.3 */ |
| 153 | switch (rev) { |
| 154 | case SSB_IDLOW_SSBREV_22: |
| 155 | - return SSB_TMSLOW_REJECT_22; |
| 156 | + case SSB_IDLOW_SSBREV_24: |
| 157 | + case SSB_IDLOW_SSBREV_26: |
| 158 | + return SSB_TMSLOW_REJECT; |
| 159 | case SSB_IDLOW_SSBREV_23: |
| 160 | return SSB_TMSLOW_REJECT_23; |
| 161 | - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */ |
| 162 | - case SSB_IDLOW_SSBREV_25: /* same here */ |
| 163 | - case SSB_IDLOW_SSBREV_26: /* same here */ |
| 164 | + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ |
| 165 | case SSB_IDLOW_SSBREV_27: /* same here */ |
| 166 | - return SSB_TMSLOW_REJECT_23; /* this is a guess */ |
| 167 | + return SSB_TMSLOW_REJECT; /* this is a guess */ |
| 168 | default: |
| 169 | printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); |
| 170 | WARN_ON(1); |
| 171 | } |
| 172 | - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23); |
| 173 | + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23); |
| 174 | } |
| 175 | |
| 176 | int ssb_device_is_enabled(struct ssb_device *dev) |
| 177 | @@ -1163,10 +1194,10 @@ void ssb_device_enable(struct ssb_device |
| 178 | } |
| 179 | EXPORT_SYMBOL(ssb_device_enable); |
| 180 | |
| 181 | -/* Wait for a bit in a register to get set or unset. |
| 182 | +/* Wait for bitmask in a register to get set or cleared. |
| 183 | * timeout is in units of ten-microseconds */ |
| 184 | -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask, |
| 185 | - int timeout, int set) |
| 186 | +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, |
| 187 | + int timeout, int set) |
| 188 | { |
| 189 | int i; |
| 190 | u32 val; |
| 191 | @@ -1174,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic |
| 192 | for (i = 0; i < timeout; i++) { |
| 193 | val = ssb_read32(dev, reg); |
| 194 | if (set) { |
| 195 | - if (val & bitmask) |
| 196 | + if ((val & bitmask) == bitmask) |
| 197 | return 0; |
| 198 | } else { |
| 199 | if (!(val & bitmask)) |
| 200 | @@ -1191,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic |
| 201 | |
| 202 | void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) |
| 203 | { |
| 204 | - u32 reject; |
| 205 | + u32 reject, val; |
| 206 | |
| 207 | if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) |
| 208 | return; |
| 209 | |
| 210 | reject = ssb_tmslow_reject_bitmask(dev); |
| 211 | - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); |
| 212 | - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1); |
| 213 | - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); |
| 214 | - ssb_write32(dev, SSB_TMSLOW, |
| 215 | - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | |
| 216 | - reject | SSB_TMSLOW_RESET | |
| 217 | - core_specific_flags); |
| 218 | - ssb_flush_tmslow(dev); |
| 219 | + |
| 220 | + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { |
| 221 | + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); |
| 222 | + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); |
| 223 | + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); |
| 224 | + |
| 225 | + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { |
| 226 | + val = ssb_read32(dev, SSB_IMSTATE); |
| 227 | + val |= SSB_IMSTATE_REJECT; |
| 228 | + ssb_write32(dev, SSB_IMSTATE, val); |
| 229 | + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, |
| 230 | + 0); |
| 231 | + } |
| 232 | + |
| 233 | + ssb_write32(dev, SSB_TMSLOW, |
| 234 | + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | |
| 235 | + reject | SSB_TMSLOW_RESET | |
| 236 | + core_specific_flags); |
| 237 | + ssb_flush_tmslow(dev); |
| 238 | + |
| 239 | + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { |
| 240 | + val = ssb_read32(dev, SSB_IMSTATE); |
| 241 | + val &= ~SSB_IMSTATE_REJECT; |
| 242 | + ssb_write32(dev, SSB_IMSTATE, val); |
| 243 | + } |
| 244 | + } |
| 245 | |
| 246 | ssb_write32(dev, SSB_TMSLOW, |
| 247 | reject | SSB_TMSLOW_RESET | |
| 248 | @@ -1213,13 +1262,34 @@ void ssb_device_disable(struct ssb_devic |
| 249 | } |
| 250 | EXPORT_SYMBOL(ssb_device_disable); |
| 251 | |
| 252 | +/* Some chipsets need routing known for PCIe and 64-bit DMA */ |
| 253 | +static bool ssb_dma_translation_special_bit(struct ssb_device *dev) |
| 254 | +{ |
| 255 | + u16 chip_id = dev->bus->chip_id; |
| 256 | + |
| 257 | + if (dev->id.coreid == SSB_DEV_80211) { |
| 258 | + return (chip_id == 0x4322 || chip_id == 43221 || |
| 259 | + chip_id == 43231 || chip_id == 43222); |
| 260 | + } |
| 261 | + |
| 262 | + return 0; |
| 263 | +} |
| 264 | + |
| 265 | u32 ssb_dma_translation(struct ssb_device *dev) |
| 266 | { |
| 267 | switch (dev->bus->bustype) { |
| 268 | case SSB_BUSTYPE_SSB: |
| 269 | return 0; |
| 270 | case SSB_BUSTYPE_PCI: |
| 271 | - return SSB_PCI_DMA; |
| 272 | + if (pci_is_pcie(dev->bus->host_pci) && |
| 273 | + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { |
| 274 | + return SSB_PCIE_DMA_H32; |
| 275 | + } else { |
| 276 | + if (ssb_dma_translation_special_bit(dev)) |
| 277 | + return SSB_PCIE_DMA_H32; |
| 278 | + else |
| 279 | + return SSB_PCI_DMA; |
| 280 | + } |
| 281 | default: |
| 282 | __ssb_dma_not_implemented(dev); |
| 283 | } |
| 284 | @@ -1262,20 +1332,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown); |
| 285 | |
| 286 | int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) |
| 287 | { |
| 288 | - struct ssb_chipcommon *cc; |
| 289 | int err; |
| 290 | enum ssb_clkmode mode; |
| 291 | |
| 292 | err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); |
| 293 | if (err) |
| 294 | goto error; |
| 295 | - cc = &bus->chipco; |
| 296 | - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; |
| 297 | - ssb_chipco_set_clockmode(cc, mode); |
| 298 | |
| 299 | #ifdef CONFIG_SSB_DEBUG |
| 300 | bus->powered_up = 1; |
| 301 | #endif |
| 302 | + |
| 303 | + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; |
| 304 | + ssb_chipco_set_clockmode(&bus->chipco, mode); |
| 305 | + |
| 306 | return 0; |
| 307 | error: |
| 308 | ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); |
| 309 | @@ -1283,6 +1353,37 @@ error: |
| 310 | } |
| 311 | EXPORT_SYMBOL(ssb_bus_powerup); |
| 312 | |
| 313 | +static void ssb_broadcast_value(struct ssb_device *dev, |
| 314 | + u32 address, u32 data) |
| 315 | +{ |
| 316 | +#ifdef CONFIG_SSB_DRIVER_PCICORE |
| 317 | + /* This is used for both, PCI and ChipCommon core, so be careful. */ |
| 318 | + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); |
| 319 | + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); |
| 320 | +#endif |
| 321 | + |
| 322 | + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address); |
| 323 | + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */ |
| 324 | + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data); |
| 325 | + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */ |
| 326 | +} |
| 327 | + |
| 328 | +void ssb_commit_settings(struct ssb_bus *bus) |
| 329 | +{ |
| 330 | + struct ssb_device *dev; |
| 331 | + |
| 332 | +#ifdef CONFIG_SSB_DRIVER_PCICORE |
| 333 | + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; |
| 334 | +#else |
| 335 | + dev = bus->chipco.dev; |
| 336 | +#endif |
| 337 | + if (WARN_ON(!dev)) |
| 338 | + return; |
| 339 | + /* This forces an update of the cached registers. */ |
| 340 | + ssb_broadcast_value(dev, 0xFD8, 0); |
| 341 | +} |
| 342 | +EXPORT_SYMBOL(ssb_commit_settings); |
| 343 | + |
| 344 | u32 ssb_admatch_base(u32 adm) |
| 345 | { |
| 346 | u32 base = 0; |
| 347 | --- a/drivers/ssb/pci.c |
| 348 | +++ b/drivers/ssb/pci.c |
| 349 | @@ -1,7 +1,7 @@ |
| 350 | /* |
| 351 | * Sonics Silicon Backplane PCI-Hostbus related functions. |
| 352 | * |
| 353 | - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de> |
| 354 | + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch> |
| 355 | * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> |
| 356 | * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> |
| 357 | * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> |
| 358 | @@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss |
| 359 | out->antenna_gain.ghz5.a3 = gain; |
| 360 | } |
| 361 | |
| 362 | +/* Revs 4 5 and 8 have partially shared layout */ |
| 363 | +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in) |
| 364 | +{ |
| 365 | + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, |
| 366 | + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT); |
| 367 | + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, |
| 368 | + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT); |
| 369 | + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, |
| 370 | + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT); |
| 371 | + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, |
| 372 | + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT); |
| 373 | + |
| 374 | + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, |
| 375 | + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT); |
| 376 | + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, |
| 377 | + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT); |
| 378 | + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, |
| 379 | + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT); |
| 380 | + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, |
| 381 | + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT); |
| 382 | + |
| 383 | + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, |
| 384 | + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT); |
| 385 | + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, |
| 386 | + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT); |
| 387 | + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, |
| 388 | + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT); |
| 389 | + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, |
| 390 | + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT); |
| 391 | + |
| 392 | + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, |
| 393 | + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT); |
| 394 | + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, |
| 395 | + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT); |
| 396 | + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, |
| 397 | + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT); |
| 398 | + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, |
| 399 | + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT); |
| 400 | +} |
| 401 | + |
| 402 | static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) |
| 403 | { |
| 404 | int i; |
| 405 | @@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb |
| 406 | SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0); |
| 407 | SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0); |
| 408 | SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0); |
| 409 | + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0); |
| 410 | + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0); |
| 411 | } else { |
| 412 | SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0); |
| 413 | SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0); |
| 414 | SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0); |
| 415 | + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0); |
| 416 | + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0); |
| 417 | } |
| 418 | SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A, |
| 419 | SSB_SPROM4_ANTAVAIL_A_SHIFT); |
| 420 | @@ -471,13 +515,21 @@ static void sprom_extract_r45(struct ssb |
| 421 | memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, |
| 422 | sizeof(out->antenna_gain.ghz5)); |
| 423 | |
| 424 | + sprom_extract_r458(out, in); |
| 425 | + |
| 426 | /* TODO - get remaining rev 4 stuff needed */ |
| 427 | } |
| 428 | |
| 429 | static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) |
| 430 | { |
| 431 | int i; |
| 432 | - u16 v; |
| 433 | + u16 v, o; |
| 434 | + u16 pwr_info_offset[] = { |
| 435 | + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1, |
| 436 | + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3 |
| 437 | + }; |
| 438 | + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) != |
| 439 | + ARRAY_SIZE(out->core_pwr_info)); |
| 440 | |
| 441 | /* extract the MAC address */ |
| 442 | for (i = 0; i < 3; i++) { |
| 443 | @@ -561,6 +613,63 @@ static void sprom_extract_r8(struct ssb_ |
| 444 | memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, |
| 445 | sizeof(out->antenna_gain.ghz5)); |
| 446 | |
| 447 | + /* Extract cores power info info */ |
| 448 | + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) { |
| 449 | + o = pwr_info_offset[i]; |
| 450 | + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI, |
| 451 | + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT); |
| 452 | + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI, |
| 453 | + SSB_SPROM8_2G_MAXP, 0); |
| 454 | + |
| 455 | + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0); |
| 456 | + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0); |
| 457 | + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0); |
| 458 | + |
| 459 | + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI, |
| 460 | + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT); |
| 461 | + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI, |
| 462 | + SSB_SPROM8_5G_MAXP, 0); |
| 463 | + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP, |
| 464 | + SSB_SPROM8_5GH_MAXP, 0); |
| 465 | + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP, |
| 466 | + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT); |
| 467 | + |
| 468 | + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0); |
| 469 | + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0); |
| 470 | + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0); |
| 471 | + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0); |
| 472 | + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0); |
| 473 | + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0); |
| 474 | + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0); |
| 475 | + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0); |
| 476 | + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0); |
| 477 | + } |
| 478 | + |
| 479 | + /* Extract FEM info */ |
| 480 | + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, |
| 481 | + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); |
| 482 | + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, |
| 483 | + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); |
| 484 | + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, |
| 485 | + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); |
| 486 | + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, |
| 487 | + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); |
| 488 | + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, |
| 489 | + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); |
| 490 | + |
| 491 | + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, |
| 492 | + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); |
| 493 | + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, |
| 494 | + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); |
| 495 | + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, |
| 496 | + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); |
| 497 | + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, |
| 498 | + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); |
| 499 | + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, |
| 500 | + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); |
| 501 | + |
| 502 | + sprom_extract_r458(out, in); |
| 503 | + |
| 504 | /* TODO - get remaining rev 8 stuff needed */ |
| 505 | } |
| 506 | |
| 507 | @@ -573,37 +682,34 @@ static int sprom_extract(struct ssb_bus |
| 508 | ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); |
| 509 | memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ |
| 510 | memset(out->et1mac, 0xFF, 6); |
| 511 | + |
| 512 | if ((bus->chip_id & 0xFF00) == 0x4400) { |
| 513 | /* Workaround: The BCM44XX chip has a stupid revision |
| 514 | * number stored in the SPROM. |
| 515 | * Always extract r1. */ |
| 516 | out->revision = 1; |
| 517 | + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision); |
| 518 | + } |
| 519 | + |
| 520 | + switch (out->revision) { |
| 521 | + case 1: |
| 522 | + case 2: |
| 523 | + case 3: |
| 524 | sprom_extract_r123(out, in); |
| 525 | - } else if (bus->chip_id == 0x4321) { |
| 526 | - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */ |
| 527 | - out->revision = 4; |
| 528 | + break; |
| 529 | + case 4: |
| 530 | + case 5: |
| 531 | sprom_extract_r45(out, in); |
| 532 | - } else { |
| 533 | - switch (out->revision) { |
| 534 | - case 1: |
| 535 | - case 2: |
| 536 | - case 3: |
| 537 | - sprom_extract_r123(out, in); |
| 538 | - break; |
| 539 | - case 4: |
| 540 | - case 5: |
| 541 | - sprom_extract_r45(out, in); |
| 542 | - break; |
| 543 | - case 8: |
| 544 | - sprom_extract_r8(out, in); |
| 545 | - break; |
| 546 | - default: |
| 547 | - ssb_printk(KERN_WARNING PFX "Unsupported SPROM" |
| 548 | - " revision %d detected. Will extract" |
| 549 | - " v1\n", out->revision); |
| 550 | - out->revision = 1; |
| 551 | - sprom_extract_r123(out, in); |
| 552 | - } |
| 553 | + break; |
| 554 | + case 8: |
| 555 | + sprom_extract_r8(out, in); |
| 556 | + break; |
| 557 | + default: |
| 558 | + ssb_printk(KERN_WARNING PFX "Unsupported SPROM" |
| 559 | + " revision %d detected. Will extract" |
| 560 | + " v1\n", out->revision); |
| 561 | + out->revision = 1; |
| 562 | + sprom_extract_r123(out, in); |
| 563 | } |
| 564 | |
| 565 | if (out->boardflags_lo == 0xFFFF) |
| 566 | @@ -617,15 +723,14 @@ static int sprom_extract(struct ssb_bus |
| 567 | static int ssb_pci_sprom_get(struct ssb_bus *bus, |
| 568 | struct ssb_sprom *sprom) |
| 569 | { |
| 570 | - const struct ssb_sprom *fallback; |
| 571 | - int err = -ENOMEM; |
| 572 | + int err; |
| 573 | u16 *buf; |
| 574 | |
| 575 | if (!ssb_is_sprom_available(bus)) { |
| 576 | ssb_printk(KERN_ERR PFX "No SPROM available!\n"); |
| 577 | return -ENODEV; |
| 578 | } |
| 579 | - if (bus->chipco.dev) { /* can be unavailible! */ |
| 580 | + if (bus->chipco.dev) { /* can be unavailable! */ |
| 581 | /* |
| 582 | * get SPROM offset: SSB_SPROM_BASE1 except for |
| 583 | * chipcommon rev >= 31 or chip ID is 0x4312 and |
| 584 | @@ -645,7 +750,7 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 585 | |
| 586 | buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); |
| 587 | if (!buf) |
| 588 | - goto out; |
| 589 | + return -ENOMEM; |
| 590 | bus->sprom_size = SSB_SPROMSIZE_WORDS_R123; |
| 591 | sprom_do_read(bus, buf); |
| 592 | err = sprom_check_crc(buf, bus->sprom_size); |
| 593 | @@ -655,17 +760,24 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 594 | buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), |
| 595 | GFP_KERNEL); |
| 596 | if (!buf) |
| 597 | - goto out; |
| 598 | + return -ENOMEM; |
| 599 | bus->sprom_size = SSB_SPROMSIZE_WORDS_R4; |
| 600 | sprom_do_read(bus, buf); |
| 601 | err = sprom_check_crc(buf, bus->sprom_size); |
| 602 | if (err) { |
| 603 | /* All CRC attempts failed. |
| 604 | * Maybe there is no SPROM on the device? |
| 605 | - * If we have a fallback, use that. */ |
| 606 | - fallback = ssb_get_fallback_sprom(); |
| 607 | - if (fallback) { |
| 608 | - memcpy(sprom, fallback, sizeof(*sprom)); |
| 609 | + * Now we ask the arch code if there is some sprom |
| 610 | + * available for this device in some other storage */ |
| 611 | + err = ssb_fill_sprom_with_fallback(bus, sprom); |
| 612 | + if (err) { |
| 613 | + ssb_printk(KERN_WARNING PFX "WARNING: Using" |
| 614 | + " fallback SPROM failed (err %d)\n", |
| 615 | + err); |
| 616 | + } else { |
| 617 | + ssb_dprintk(KERN_DEBUG PFX "Using SPROM" |
| 618 | + " revision %d provided by" |
| 619 | + " platform.\n", sprom->revision); |
| 620 | err = 0; |
| 621 | goto out_free; |
| 622 | } |
| 623 | @@ -677,19 +789,15 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 624 | |
| 625 | out_free: |
| 626 | kfree(buf); |
| 627 | -out: |
| 628 | return err; |
| 629 | } |
| 630 | |
| 631 | static void ssb_pci_get_boardinfo(struct ssb_bus *bus, |
| 632 | struct ssb_boardinfo *bi) |
| 633 | { |
| 634 | - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID, |
| 635 | - &bi->vendor); |
| 636 | - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID, |
| 637 | - &bi->type); |
| 638 | - pci_read_config_word(bus->host_pci, PCI_REVISION_ID, |
| 639 | - &bi->rev); |
| 640 | + bi->vendor = bus->host_pci->subsystem_vendor; |
| 641 | + bi->type = bus->host_pci->subsystem_device; |
| 642 | + bi->rev = bus->host_pci->revision; |
| 643 | } |
| 644 | |
| 645 | int ssb_pci_get_invariants(struct ssb_bus *bus, |
| 646 | --- a/drivers/ssb/pcihost_wrapper.c |
| 647 | +++ b/drivers/ssb/pcihost_wrapper.c |
| 648 | @@ -6,7 +6,7 @@ |
| 649 | * Copyright (c) 2005 Stefano Brivio <st3@riseup.net> |
| 650 | * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> |
| 651 | * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> |
| 652 | - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de> |
| 653 | + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch> |
| 654 | * |
| 655 | * Licensed under the GNU/GPL. See COPYING for details. |
| 656 | */ |
| 657 | @@ -53,12 +53,13 @@ static int ssb_pcihost_resume(struct pci |
| 658 | # define ssb_pcihost_resume NULL |
| 659 | #endif /* CONFIG_PM */ |
| 660 | |
| 661 | -static int ssb_pcihost_probe(struct pci_dev *dev, |
| 662 | - const struct pci_device_id *id) |
| 663 | +static int __devinit ssb_pcihost_probe(struct pci_dev *dev, |
| 664 | + const struct pci_device_id *id) |
| 665 | { |
| 666 | struct ssb_bus *ssb; |
| 667 | int err = -ENOMEM; |
| 668 | const char *name; |
| 669 | + u32 val; |
| 670 | |
| 671 | ssb = kzalloc(sizeof(*ssb), GFP_KERNEL); |
| 672 | if (!ssb) |
| 673 | @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_ |
| 674 | goto err_pci_disable; |
| 675 | pci_set_master(dev); |
| 676 | |
| 677 | + /* Disable the RETRY_TIMEOUT register (0x41) to keep |
| 678 | + * PCI Tx retries from interfering with C3 CPU state */ |
| 679 | + pci_read_config_dword(dev, 0x40, &val); |
| 680 | + if ((val & 0x0000ff00) != 0) |
| 681 | + pci_write_config_dword(dev, 0x40, val & 0xffff00ff); |
| 682 | + |
| 683 | err = ssb_bus_pcibus_register(ssb, dev); |
| 684 | if (err) |
| 685 | goto err_pci_release_regions; |
| 686 | @@ -103,7 +110,7 @@ static void ssb_pcihost_remove(struct pc |
| 687 | pci_set_drvdata(dev, NULL); |
| 688 | } |
| 689 | |
| 690 | -int ssb_pcihost_register(struct pci_driver *driver) |
| 691 | +int __devinit ssb_pcihost_register(struct pci_driver *driver) |
| 692 | { |
| 693 | driver->probe = ssb_pcihost_probe; |
| 694 | driver->remove = ssb_pcihost_remove; |
| 695 | --- a/drivers/ssb/scan.c |
| 696 | +++ b/drivers/ssb/scan.c |
| 697 | @@ -2,7 +2,7 @@ |
| 698 | * Sonics Silicon Backplane |
| 699 | * Bus scanning |
| 700 | * |
| 701 | - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de> |
| 702 | + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch> |
| 703 | * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> |
| 704 | * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> |
| 705 | * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> |
| 706 | @@ -259,7 +259,10 @@ static int we_support_multiple_80211_cor |
| 707 | #ifdef CONFIG_SSB_PCIHOST |
| 708 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
| 709 | if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && |
| 710 | - bus->host_pci->device == 0x4324) |
| 711 | + ((bus->host_pci->device == 0x4313) || |
| 712 | + (bus->host_pci->device == 0x431A) || |
| 713 | + (bus->host_pci->device == 0x4321) || |
| 714 | + (bus->host_pci->device == 0x4324))) |
| 715 | return 1; |
| 716 | } |
| 717 | #endif /* CONFIG_SSB_PCIHOST */ |
| 718 | @@ -308,8 +311,7 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 719 | } else { |
| 720 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
| 721 | bus->chip_id = pcidev_to_chipid(bus->host_pci); |
| 722 | - pci_read_config_word(bus->host_pci, PCI_REVISION_ID, |
| 723 | - &bus->chip_rev); |
| 724 | + bus->chip_rev = bus->host_pci->revision; |
| 725 | bus->chip_package = 0; |
| 726 | } else { |
| 727 | bus->chip_id = 0x4710; |
| 728 | @@ -406,10 +408,10 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 729 | /* Ignore PCI cores on PCI-E cards. |
| 730 | * Ignore PCI-E cores on PCI cards. */ |
| 731 | if (dev->id.coreid == SSB_DEV_PCI) { |
| 732 | - if (bus->host_pci->is_pcie) |
| 733 | + if (pci_is_pcie(bus->host_pci)) |
| 734 | continue; |
| 735 | } else { |
| 736 | - if (!bus->host_pci->is_pcie) |
| 737 | + if (!pci_is_pcie(bus->host_pci)) |
| 738 | continue; |
| 739 | } |
| 740 | } |
| 741 | @@ -421,6 +423,16 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 742 | bus->pcicore.dev = dev; |
| 743 | #endif /* CONFIG_SSB_DRIVER_PCICORE */ |
| 744 | break; |
| 745 | + case SSB_DEV_ETHERNET: |
| 746 | + if (bus->bustype == SSB_BUSTYPE_PCI) { |
| 747 | + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && |
| 748 | + (bus->host_pci->device & 0xFF00) == 0x4300) { |
| 749 | + /* This is a dangling ethernet core on a |
| 750 | + * wireless device. Ignore it. */ |
| 751 | + continue; |
| 752 | + } |
| 753 | + } |
| 754 | + break; |
| 755 | default: |
| 756 | break; |
| 757 | } |
| 758 | --- a/include/linux/ssb/ssb.h |
| 759 | +++ b/include/linux/ssb/ssb.h |
| 760 | @@ -16,6 +16,12 @@ struct pcmcia_device; |
| 761 | struct ssb_bus; |
| 762 | struct ssb_driver; |
| 763 | |
| 764 | +struct ssb_sprom_core_pwr_info { |
| 765 | + u8 itssi_2g, itssi_5g; |
| 766 | + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh; |
| 767 | + u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3]; |
| 768 | +}; |
| 769 | + |
| 770 | struct ssb_sprom { |
| 771 | u8 revision; |
| 772 | u8 il0mac[6]; /* MAC address for 802.11b/g */ |
| 773 | @@ -25,8 +31,10 @@ struct ssb_sprom { |
| 774 | u8 et1phyaddr; /* MII address for enet1 */ |
| 775 | u8 et0mdcport; /* MDIO for enet0 */ |
| 776 | u8 et1mdcport; /* MDIO for enet1 */ |
| 777 | - u8 board_rev; /* Board revision number from SPROM. */ |
| 778 | + u16 board_rev; /* Board revision number from SPROM. */ |
| 779 | u8 country_code; /* Country Code */ |
| 780 | + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ |
| 781 | + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ |
| 782 | u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ |
| 783 | u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */ |
| 784 | u16 pa0b0; |
| 785 | @@ -55,6 +63,10 @@ struct ssb_sprom { |
| 786 | u8 tri5gl; /* 5.2GHz TX isolation */ |
| 787 | u8 tri5g; /* 5.3GHz TX isolation */ |
| 788 | u8 tri5gh; /* 5.8GHz TX isolation */ |
| 789 | + u8 txpid2g[4]; /* 2GHz TX power index */ |
| 790 | + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ |
| 791 | + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ |
| 792 | + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ |
| 793 | u8 rxpo2g; /* 2GHz RX power offset */ |
| 794 | u8 rxpo5g; /* 5GHz RX power offset */ |
| 795 | u8 rssisav2g; /* 2GHz RSSI params */ |
| 796 | @@ -76,6 +88,8 @@ struct ssb_sprom { |
| 797 | u16 boardflags2_hi; /* Board flags (bits 48-63) */ |
| 798 | /* TODO store board flags in a single u64 */ |
| 799 | |
| 800 | + struct ssb_sprom_core_pwr_info core_pwr_info[4]; |
| 801 | + |
| 802 | /* Antenna gain values for up to 4 antennas |
| 803 | * on each band. Values in dBm/4 (Q5.2). Negative gain means the |
| 804 | * loss in the connectors is bigger than the gain. */ |
| 805 | @@ -88,6 +102,15 @@ struct ssb_sprom { |
| 806 | } ghz5; /* 5GHz band */ |
| 807 | } antenna_gain; |
| 808 | |
| 809 | + struct { |
| 810 | + struct { |
| 811 | + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; |
| 812 | + } ghz2; |
| 813 | + struct { |
| 814 | + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; |
| 815 | + } ghz5; |
| 816 | + } fem; |
| 817 | + |
| 818 | /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ |
| 819 | }; |
| 820 | |
| 821 | @@ -95,7 +118,7 @@ struct ssb_sprom { |
| 822 | struct ssb_boardinfo { |
| 823 | u16 vendor; |
| 824 | u16 type; |
| 825 | - u16 rev; |
| 826 | + u8 rev; |
| 827 | }; |
| 828 | |
| 829 | |
| 830 | @@ -225,10 +248,9 @@ struct ssb_driver { |
| 831 | #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv) |
| 832 | |
| 833 | extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner); |
| 834 | -static inline int ssb_driver_register(struct ssb_driver *drv) |
| 835 | -{ |
| 836 | - return __ssb_driver_register(drv, THIS_MODULE); |
| 837 | -} |
| 838 | +#define ssb_driver_register(drv) \ |
| 839 | + __ssb_driver_register(drv, THIS_MODULE) |
| 840 | + |
| 841 | extern void ssb_driver_unregister(struct ssb_driver *drv); |
| 842 | |
| 843 | |
| 844 | @@ -304,7 +326,7 @@ struct ssb_bus { |
| 845 | |
| 846 | /* ID information about the Chip. */ |
| 847 | u16 chip_id; |
| 848 | - u16 chip_rev; |
| 849 | + u8 chip_rev; |
| 850 | u16 sprom_offset; |
| 851 | u16 sprom_size; /* number of words in sprom */ |
| 852 | u8 chip_package; |
| 853 | @@ -400,7 +422,9 @@ extern bool ssb_is_sprom_available(struc |
| 854 | |
| 855 | /* Set a fallback SPROM. |
| 856 | * See kdoc at the function definition for complete documentation. */ |
| 857 | -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom); |
| 858 | +extern int ssb_arch_register_fallback_sprom( |
| 859 | + int (*sprom_callback)(struct ssb_bus *bus, |
| 860 | + struct ssb_sprom *out)); |
| 861 | |
| 862 | /* Suspend a SSB bus. |
| 863 | * Call this from the parent bus suspend routine. */ |
| 864 | @@ -514,6 +538,7 @@ extern int ssb_bus_may_powerdown(struct |
| 865 | * Otherwise static always-on powercontrol will be used. */ |
| 866 | extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl); |
| 867 | |
| 868 | +extern void ssb_commit_settings(struct ssb_bus *bus); |
| 869 | |
| 870 | /* Various helper functions */ |
| 871 | extern u32 ssb_admatch_base(u32 adm); |
| 872 | --- a/include/linux/ssb/ssb_driver_gige.h |
| 873 | +++ b/include/linux/ssb/ssb_driver_gige.h |
| 874 | @@ -96,16 +96,21 @@ static inline bool ssb_gige_must_flush_p |
| 875 | return 0; |
| 876 | } |
| 877 | |
| 878 | -extern char * nvram_get(const char *name); |
| 879 | +#ifdef CONFIG_BCM47XX |
| 880 | +#include <asm/mach-bcm47xx/nvram.h> |
| 881 | /* Get the device MAC address */ |
| 882 | static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr) |
| 883 | { |
| 884 | -#ifdef CONFIG_BCM47XX |
| 885 | - char *res = nvram_get("et0macaddr"); |
| 886 | - if (res) |
| 887 | - memcpy(macaddr, res, 6); |
| 888 | -#endif |
| 889 | + char buf[20]; |
| 890 | + if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0) |
| 891 | + return; |
| 892 | + nvram_parse_macaddr(buf, macaddr); |
| 893 | } |
| 894 | +#else |
| 895 | +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr) |
| 896 | +{ |
| 897 | +} |
| 898 | +#endif |
| 899 | |
| 900 | extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev, |
| 901 | struct pci_dev *pdev); |
| 902 | --- a/include/linux/ssb/ssb_regs.h |
| 903 | +++ b/include/linux/ssb/ssb_regs.h |
| 904 | @@ -85,6 +85,8 @@ |
| 905 | #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */ |
| 906 | #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */ |
| 907 | #define SSB_IMSTATE_TO 0x00040000 /* Timeout */ |
| 908 | +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */ |
| 909 | +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */ |
| 910 | #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */ |
| 911 | #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ |
| 912 | #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ |
| 913 | @@ -95,7 +97,7 @@ |
| 914 | #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ |
| 915 | #define SSB_TMSLOW 0x0F98 /* SB Target State Low */ |
| 916 | #define SSB_TMSLOW_RESET 0x00000001 /* Reset */ |
| 917 | -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */ |
| 918 | +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */ |
| 919 | #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */ |
| 920 | #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */ |
| 921 | #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ |
| 922 | @@ -267,6 +269,8 @@ |
| 923 | /* SPROM Revision 4 */ |
| 924 | #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ |
| 925 | #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ |
| 926 | +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */ |
| 927 | +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */ |
| 928 | #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */ |
| 929 | #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */ |
| 930 | #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */ |
| 931 | @@ -298,6 +302,46 @@ |
| 932 | #define SSB_SPROM4_AGAIN2_SHIFT 0 |
| 933 | #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ |
| 934 | #define SSB_SPROM4_AGAIN3_SHIFT 8 |
| 935 | +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */ |
| 936 | +#define SSB_SPROM4_TXPID2G0 0x00FF |
| 937 | +#define SSB_SPROM4_TXPID2G0_SHIFT 0 |
| 938 | +#define SSB_SPROM4_TXPID2G1 0xFF00 |
| 939 | +#define SSB_SPROM4_TXPID2G1_SHIFT 8 |
| 940 | +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */ |
| 941 | +#define SSB_SPROM4_TXPID2G2 0x00FF |
| 942 | +#define SSB_SPROM4_TXPID2G2_SHIFT 0 |
| 943 | +#define SSB_SPROM4_TXPID2G3 0xFF00 |
| 944 | +#define SSB_SPROM4_TXPID2G3_SHIFT 8 |
| 945 | +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */ |
| 946 | +#define SSB_SPROM4_TXPID5G0 0x00FF |
| 947 | +#define SSB_SPROM4_TXPID5G0_SHIFT 0 |
| 948 | +#define SSB_SPROM4_TXPID5G1 0xFF00 |
| 949 | +#define SSB_SPROM4_TXPID5G1_SHIFT 8 |
| 950 | +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */ |
| 951 | +#define SSB_SPROM4_TXPID5G2 0x00FF |
| 952 | +#define SSB_SPROM4_TXPID5G2_SHIFT 0 |
| 953 | +#define SSB_SPROM4_TXPID5G3 0xFF00 |
| 954 | +#define SSB_SPROM4_TXPID5G3_SHIFT 8 |
| 955 | +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */ |
| 956 | +#define SSB_SPROM4_TXPID5GL0 0x00FF |
| 957 | +#define SSB_SPROM4_TXPID5GL0_SHIFT 0 |
| 958 | +#define SSB_SPROM4_TXPID5GL1 0xFF00 |
| 959 | +#define SSB_SPROM4_TXPID5GL1_SHIFT 8 |
| 960 | +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */ |
| 961 | +#define SSB_SPROM4_TXPID5GL2 0x00FF |
| 962 | +#define SSB_SPROM4_TXPID5GL2_SHIFT 0 |
| 963 | +#define SSB_SPROM4_TXPID5GL3 0xFF00 |
| 964 | +#define SSB_SPROM4_TXPID5GL3_SHIFT 8 |
| 965 | +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */ |
| 966 | +#define SSB_SPROM4_TXPID5GH0 0x00FF |
| 967 | +#define SSB_SPROM4_TXPID5GH0_SHIFT 0 |
| 968 | +#define SSB_SPROM4_TXPID5GH1 0xFF00 |
| 969 | +#define SSB_SPROM4_TXPID5GH1_SHIFT 8 |
| 970 | +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */ |
| 971 | +#define SSB_SPROM4_TXPID5GH2 0x00FF |
| 972 | +#define SSB_SPROM4_TXPID5GH2_SHIFT 0 |
| 973 | +#define SSB_SPROM4_TXPID5GH3 0xFF00 |
| 974 | +#define SSB_SPROM4_TXPID5GH3_SHIFT 8 |
| 975 | #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ |
| 976 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ |
| 977 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 978 | @@ -317,6 +361,8 @@ |
| 979 | #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */ |
| 980 | #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */ |
| 981 | #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */ |
| 982 | +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */ |
| 983 | +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */ |
| 984 | #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */ |
| 985 | #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */ |
| 986 | #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ |
| 987 | @@ -386,6 +432,56 @@ |
| 988 | #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ |
| 989 | #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ |
| 990 | #define SSB_SPROM8_RXPO5G_SHIFT 8 |
| 991 | +#define SSB_SPROM8_FEM2G 0x00AE |
| 992 | +#define SSB_SPROM8_FEM5G 0x00B0 |
| 993 | +#define SSB_SROM8_FEM_TSSIPOS 0x0001 |
| 994 | +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0 |
| 995 | +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006 |
| 996 | +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1 |
| 997 | +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8 |
| 998 | +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3 |
| 999 | +#define SSB_SROM8_FEM_TR_ISO 0x0700 |
| 1000 | +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8 |
| 1001 | +#define SSB_SROM8_FEM_ANTSWLUT 0xF800 |
| 1002 | +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11 |
| 1003 | +#define SSB_SPROM8_THERMAL 0x00B2 |
| 1004 | +#define SSB_SPROM8_MPWR_RAWTS 0x00B4 |
| 1005 | +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6 |
| 1006 | +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8 |
| 1007 | +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA |
| 1008 | + |
| 1009 | +/* There are 4 blocks with power info sharing the same layout */ |
| 1010 | +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0 |
| 1011 | +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0 |
| 1012 | +#define SSB_SROM8_PWR_INFO_CORE2 0x0100 |
| 1013 | +#define SSB_SROM8_PWR_INFO_CORE3 0x0120 |
| 1014 | + |
| 1015 | +#define SSB_SROM8_2G_MAXP_ITSSI 0x00 |
| 1016 | +#define SSB_SPROM8_2G_MAXP 0x00FF |
| 1017 | +#define SSB_SPROM8_2G_ITSSI 0xFF00 |
| 1018 | +#define SSB_SPROM8_2G_ITSSI_SHIFT 8 |
| 1019 | +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */ |
| 1020 | +#define SSB_SROM8_2G_PA_1 0x04 |
| 1021 | +#define SSB_SROM8_2G_PA_2 0x06 |
| 1022 | +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */ |
| 1023 | +#define SSB_SPROM8_5G_MAXP 0x00FF |
| 1024 | +#define SSB_SPROM8_5G_ITSSI 0xFF00 |
| 1025 | +#define SSB_SPROM8_5G_ITSSI_SHIFT 8 |
| 1026 | +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */ |
| 1027 | +#define SSB_SPROM8_5GH_MAXP 0x00FF |
| 1028 | +#define SSB_SPROM8_5GL_MAXP 0xFF00 |
| 1029 | +#define SSB_SPROM8_5GL_MAXP_SHIFT 8 |
| 1030 | +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */ |
| 1031 | +#define SSB_SROM8_5G_PA_1 0x0E |
| 1032 | +#define SSB_SROM8_5G_PA_2 0x10 |
| 1033 | +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */ |
| 1034 | +#define SSB_SROM8_5GL_PA_1 0x14 |
| 1035 | +#define SSB_SROM8_5GL_PA_2 0x16 |
| 1036 | +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */ |
| 1037 | +#define SSB_SROM8_5GH_PA_1 0x1A |
| 1038 | +#define SSB_SROM8_5GH_PA_2 0x1C |
| 1039 | + |
| 1040 | +/* TODO: Make it deprecated */ |
| 1041 | #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ |
| 1042 | #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ |
| 1043 | #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 1044 | @@ -410,12 +506,53 @@ |
| 1045 | #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */ |
| 1046 | #define SSB_SPROM8_PA1HIB1 0x00DA |
| 1047 | #define SSB_SPROM8_PA1HIB2 0x00DC |
| 1048 | + |
| 1049 | #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */ |
| 1050 | #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */ |
| 1051 | #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */ |
| 1052 | #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */ |
| 1053 | #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */ |
| 1054 | |
| 1055 | +/* Values for boardflags_lo read from SPROM */ |
| 1056 | +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ |
| 1057 | +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ |
| 1058 | +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ |
| 1059 | +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ |
| 1060 | +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ |
| 1061 | +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ |
| 1062 | +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ |
| 1063 | +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */ |
| 1064 | +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */ |
| 1065 | +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ |
| 1066 | +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */ |
| 1067 | +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */ |
| 1068 | +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */ |
| 1069 | +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */ |
| 1070 | +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ |
| 1071 | +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ |
| 1072 | + |
| 1073 | +/* Values for boardflags_hi read from SPROM */ |
| 1074 | +#define SSB_BFH_NOPA 0x0001 /* has no PA */ |
| 1075 | +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */ |
| 1076 | +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */ |
| 1077 | +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */ |
| 1078 | +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ |
| 1079 | +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */ |
| 1080 | +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */ |
| 1081 | + |
| 1082 | +/* Values for boardflags2_lo read from SPROM */ |
| 1083 | +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ |
| 1084 | +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ |
| 1085 | +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ |
| 1086 | +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ |
| 1087 | +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ |
| 1088 | +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ |
| 1089 | +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ |
| 1090 | +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ |
| 1091 | +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ |
| 1092 | +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ |
| 1093 | +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ |
| 1094 | + |
| 1095 | /* Values for SSB_SPROM1_BINF_CCODE */ |
| 1096 | enum { |
| 1097 | SSB_SPROM1CCODE_WORLD = 0, |
| 1098 | --- a/drivers/ssb/driver_chipcommon.c |
| 1099 | +++ b/drivers/ssb/driver_chipcommon.c |
| 1100 | @@ -3,7 +3,7 @@ |
| 1101 | * Broadcom ChipCommon core driver |
| 1102 | * |
| 1103 | * Copyright 2005, Broadcom Corporation |
| 1104 | - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> |
| 1105 | + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
| 1106 | * |
| 1107 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1108 | */ |
| 1109 | @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb |
| 1110 | if (!ccdev) |
| 1111 | return; |
| 1112 | bus = ccdev->bus; |
| 1113 | + |
| 1114 | + /* We support SLOW only on 6..9 */ |
| 1115 | + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW) |
| 1116 | + mode = SSB_CLKMODE_DYNAMIC; |
| 1117 | + |
| 1118 | + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) |
| 1119 | + return; /* PMU controls clockmode, separated function needed */ |
| 1120 | + SSB_WARN_ON(ccdev->id.revision >= 20); |
| 1121 | + |
| 1122 | /* chipcommon cores prior to rev6 don't support dynamic clock control */ |
| 1123 | if (ccdev->id.revision < 6) |
| 1124 | return; |
| 1125 | - /* chipcommon cores rev10 are a whole new ball game */ |
| 1126 | + |
| 1127 | + /* ChipCommon cores rev10+ need testing */ |
| 1128 | if (ccdev->id.revision >= 10) |
| 1129 | return; |
| 1130 | + |
| 1131 | if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) |
| 1132 | return; |
| 1133 | |
| 1134 | switch (mode) { |
| 1135 | - case SSB_CLKMODE_SLOW: |
| 1136 | + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */ |
| 1137 | tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 1138 | tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 1139 | chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 1140 | break; |
| 1141 | case SSB_CLKMODE_FAST: |
| 1142 | - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ |
| 1143 | - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 1144 | - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 1145 | - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; |
| 1146 | - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 1147 | + if (ccdev->id.revision < 10) { |
| 1148 | + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ |
| 1149 | + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 1150 | + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 1151 | + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; |
| 1152 | + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 1153 | + } else { |
| 1154 | + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, |
| 1155 | + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) | |
| 1156 | + SSB_CHIPCO_SYSCLKCTL_FORCEHT)); |
| 1157 | + /* udelay(150); TODO: not available in early init */ |
| 1158 | + } |
| 1159 | break; |
| 1160 | case SSB_CLKMODE_DYNAMIC: |
| 1161 | - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 1162 | - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 1163 | - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; |
| 1164 | - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; |
| 1165 | - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) |
| 1166 | - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; |
| 1167 | - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 1168 | - |
| 1169 | - /* for dynamic control, we have to release our xtal_pu "force on" */ |
| 1170 | - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) |
| 1171 | - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); |
| 1172 | + if (ccdev->id.revision < 10) { |
| 1173 | + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 1174 | + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 1175 | + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; |
| 1176 | + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; |
| 1177 | + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != |
| 1178 | + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) |
| 1179 | + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; |
| 1180 | + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 1181 | + |
| 1182 | + /* For dynamic control, we have to release our xtal_pu |
| 1183 | + * "force on" */ |
| 1184 | + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) |
| 1185 | + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); |
| 1186 | + } else { |
| 1187 | + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, |
| 1188 | + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & |
| 1189 | + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT)); |
| 1190 | + } |
| 1191 | break; |
| 1192 | default: |
| 1193 | SSB_WARN_ON(1); |
| 1194 | @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip |
| 1195 | if (cc->dev->id.revision >= 11) |
| 1196 | cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); |
| 1197 | ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); |
| 1198 | + |
| 1199 | + if (cc->dev->id.revision >= 20) { |
| 1200 | + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0); |
| 1201 | + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0); |
| 1202 | + } |
| 1203 | + |
| 1204 | ssb_pmu_init(cc); |
| 1205 | chipco_powercontrol_init(cc); |
| 1206 | ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); |
| 1207 | --- a/drivers/ssb/driver_chipcommon_pmu.c |
| 1208 | +++ b/drivers/ssb/driver_chipcommon_pmu.c |
| 1209 | @@ -2,7 +2,7 @@ |
| 1210 | * Sonics Silicon Backplane |
| 1211 | * Broadcom ChipCommon Power Management Unit driver |
| 1212 | * |
| 1213 | - * Copyright 2009, Michael Buesch <mb@bu3sch.de> |
| 1214 | + * Copyright 2009, Michael Buesch <m@bues.ch> |
| 1215 | * Copyright 2007, Broadcom Corporation |
| 1216 | * |
| 1217 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1218 | @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc |
| 1219 | u32 min_msk = 0, max_msk = 0; |
| 1220 | unsigned int i; |
| 1221 | const struct pmu_res_updown_tab_entry *updown_tab = NULL; |
| 1222 | - unsigned int updown_tab_size; |
| 1223 | + unsigned int updown_tab_size = 0; |
| 1224 | const struct pmu_res_depend_tab_entry *depend_tab = NULL; |
| 1225 | - unsigned int depend_tab_size; |
| 1226 | + unsigned int depend_tab_size = 0; |
| 1227 | |
| 1228 | switch (bus->chip_id) { |
| 1229 | case 0x4312: |
| 1230 | + min_msk = 0xCBB; |
| 1231 | + break; |
| 1232 | case 0x4322: |
| 1233 | /* We keep the default settings: |
| 1234 | * min_msk = 0xCBB |
| 1235 | --- a/drivers/ssb/driver_gige.c |
| 1236 | +++ b/drivers/ssb/driver_gige.c |
| 1237 | @@ -3,7 +3,7 @@ |
| 1238 | * Broadcom Gigabit Ethernet core driver |
| 1239 | * |
| 1240 | * Copyright 2008, Broadcom Corporation |
| 1241 | - * Copyright 2008, Michael Buesch <mb@bu3sch.de> |
| 1242 | + * Copyright 2008, Michael Buesch <m@bues.ch> |
| 1243 | * |
| 1244 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1245 | */ |
| 1246 | @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige |
| 1247 | gige_write32(dev, SSB_GIGE_PCICFG + offset, value); |
| 1248 | } |
| 1249 | |
| 1250 | -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
| 1251 | - int reg, int size, u32 *val) |
| 1252 | +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus, |
| 1253 | + unsigned int devfn, int reg, |
| 1254 | + int size, u32 *val) |
| 1255 | { |
| 1256 | struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops); |
| 1257 | unsigned long flags; |
| 1258 | @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru |
| 1259 | return PCIBIOS_SUCCESSFUL; |
| 1260 | } |
| 1261 | |
| 1262 | -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
| 1263 | - int reg, int size, u32 val) |
| 1264 | +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus, |
| 1265 | + unsigned int devfn, int reg, |
| 1266 | + int size, u32 val) |
| 1267 | { |
| 1268 | struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops); |
| 1269 | unsigned long flags; |
| 1270 | @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str |
| 1271 | return PCIBIOS_SUCCESSFUL; |
| 1272 | } |
| 1273 | |
| 1274 | -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id) |
| 1275 | +static int __devinit ssb_gige_probe(struct ssb_device *sdev, |
| 1276 | + const struct ssb_device_id *id) |
| 1277 | { |
| 1278 | struct ssb_gige *dev; |
| 1279 | u32 base, tmslow, tmshigh; |
| 1280 | --- a/drivers/ssb/driver_pcicore.c |
| 1281 | +++ b/drivers/ssb/driver_pcicore.c |
| 1282 | @@ -3,7 +3,7 @@ |
| 1283 | * Broadcom PCI-core driver |
| 1284 | * |
| 1285 | * Copyright 2005, Broadcom Corporation |
| 1286 | - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> |
| 1287 | + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
| 1288 | * |
| 1289 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1290 | */ |
| 1291 | @@ -15,6 +15,11 @@ |
| 1292 | |
| 1293 | #include "ssb_private.h" |
| 1294 | |
| 1295 | +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address); |
| 1296 | +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data); |
| 1297 | +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address); |
| 1298 | +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
| 1299 | + u8 address, u16 data); |
| 1300 | |
| 1301 | static inline |
| 1302 | u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) |
| 1303 | @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st |
| 1304 | return ssb_mips_irq(extpci_core->dev) + 2; |
| 1305 | } |
| 1306 | |
| 1307 | -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) |
| 1308 | +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) |
| 1309 | { |
| 1310 | u32 val; |
| 1311 | |
| 1312 | @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st |
| 1313 | register_pci_controller(&ssb_pcicore_controller); |
| 1314 | } |
| 1315 | |
| 1316 | -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) |
| 1317 | +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc) |
| 1318 | { |
| 1319 | struct ssb_bus *bus = pc->dev->bus; |
| 1320 | u16 chipid_top; |
| 1321 | @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct |
| 1322 | } |
| 1323 | #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ |
| 1324 | |
| 1325 | +/************************************************** |
| 1326 | + * Workarounds. |
| 1327 | + **************************************************/ |
| 1328 | + |
| 1329 | +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc) |
| 1330 | +{ |
| 1331 | + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0)); |
| 1332 | + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) { |
| 1333 | + tmp &= ~0xF000; |
| 1334 | + tmp |= (pc->dev->core_index << 12); |
| 1335 | + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp); |
| 1336 | + } |
| 1337 | +} |
| 1338 | + |
| 1339 | +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc) |
| 1340 | +{ |
| 1341 | + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; |
| 1342 | +} |
| 1343 | + |
| 1344 | +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc) |
| 1345 | +{ |
| 1346 | + const u8 serdes_pll_device = 0x1D; |
| 1347 | + const u8 serdes_rx_device = 0x1F; |
| 1348 | + u16 tmp; |
| 1349 | + |
| 1350 | + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, |
| 1351 | + ssb_pcicore_polarity_workaround(pc)); |
| 1352 | + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); |
| 1353 | + if (tmp & 0x4000) |
| 1354 | + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); |
| 1355 | +} |
| 1356 | + |
| 1357 | +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc) |
| 1358 | +{ |
| 1359 | + struct ssb_device *pdev = pc->dev; |
| 1360 | + struct ssb_bus *bus = pdev->bus; |
| 1361 | + u32 tmp; |
| 1362 | + |
| 1363 | + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
| 1364 | + tmp |= SSB_PCICORE_SBTOPCI_PREF; |
| 1365 | + tmp |= SSB_PCICORE_SBTOPCI_BURST; |
| 1366 | + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
| 1367 | + |
| 1368 | + if (pdev->id.revision < 5) { |
| 1369 | + tmp = ssb_read32(pdev, SSB_IMCFGLO); |
| 1370 | + tmp &= ~SSB_IMCFGLO_SERTO; |
| 1371 | + tmp |= 2; |
| 1372 | + tmp &= ~SSB_IMCFGLO_REQTO; |
| 1373 | + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; |
| 1374 | + ssb_write32(pdev, SSB_IMCFGLO, tmp); |
| 1375 | + ssb_commit_settings(bus); |
| 1376 | + } else if (pdev->id.revision >= 11) { |
| 1377 | + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
| 1378 | + tmp |= SSB_PCICORE_SBTOPCI_MRM; |
| 1379 | + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
| 1380 | + } |
| 1381 | +} |
| 1382 | + |
| 1383 | +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc) |
| 1384 | +{ |
| 1385 | + u32 tmp; |
| 1386 | + u8 rev = pc->dev->id.revision; |
| 1387 | + |
| 1388 | + if (rev == 0 || rev == 1) { |
| 1389 | + /* TLP Workaround register. */ |
| 1390 | + tmp = ssb_pcie_read(pc, 0x4); |
| 1391 | + tmp |= 0x8; |
| 1392 | + ssb_pcie_write(pc, 0x4, tmp); |
| 1393 | + } |
| 1394 | + if (rev == 1) { |
| 1395 | + /* DLLP Link Control register. */ |
| 1396 | + tmp = ssb_pcie_read(pc, 0x100); |
| 1397 | + tmp |= 0x40; |
| 1398 | + ssb_pcie_write(pc, 0x100, tmp); |
| 1399 | + } |
| 1400 | + |
| 1401 | + if (rev == 0) { |
| 1402 | + const u8 serdes_rx_device = 0x1F; |
| 1403 | + |
| 1404 | + ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 1405 | + 2 /* Timer */, 0x8128); |
| 1406 | + ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 1407 | + 6 /* CDR */, 0x0100); |
| 1408 | + ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 1409 | + 7 /* CDR BW */, 0x1466); |
| 1410 | + } else if (rev == 3 || rev == 4 || rev == 5) { |
| 1411 | + /* TODO: DLLP Power Management Threshold */ |
| 1412 | + ssb_pcicore_serdes_workaround(pc); |
| 1413 | + /* TODO: ASPM */ |
| 1414 | + } else if (rev == 7) { |
| 1415 | + /* TODO: No PLL down */ |
| 1416 | + } |
| 1417 | + |
| 1418 | + if (rev >= 6) { |
| 1419 | + /* Miscellaneous Configuration Fixup */ |
| 1420 | + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5)); |
| 1421 | + if (!(tmp & 0x8000)) |
| 1422 | + pcicore_write16(pc, SSB_PCICORE_SPROM(5), |
| 1423 | + tmp | 0x8000); |
| 1424 | + } |
| 1425 | +} |
| 1426 | |
| 1427 | /************************************************** |
| 1428 | * Generic and Clientmode operation code. |
| 1429 | **************************************************/ |
| 1430 | |
| 1431 | -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) |
| 1432 | +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) |
| 1433 | { |
| 1434 | + struct ssb_device *pdev = pc->dev; |
| 1435 | + struct ssb_bus *bus = pdev->bus; |
| 1436 | + |
| 1437 | + if (bus->bustype == SSB_BUSTYPE_PCI) |
| 1438 | + ssb_pcicore_fix_sprom_core_index(pc); |
| 1439 | + |
| 1440 | /* Disable PCI interrupts. */ |
| 1441 | - ssb_write32(pc->dev, SSB_INTVEC, 0); |
| 1442 | + ssb_write32(pdev, SSB_INTVEC, 0); |
| 1443 | + |
| 1444 | + /* Additional PCIe always once-executed workarounds */ |
| 1445 | + if (pc->dev->id.coreid == SSB_DEV_PCIE) { |
| 1446 | + ssb_pcicore_serdes_workaround(pc); |
| 1447 | + /* TODO: ASPM */ |
| 1448 | + /* TODO: Clock Request Update */ |
| 1449 | + } |
| 1450 | } |
| 1451 | |
| 1452 | -void ssb_pcicore_init(struct ssb_pcicore *pc) |
| 1453 | +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc) |
| 1454 | { |
| 1455 | struct ssb_device *dev = pc->dev; |
| 1456 | - struct ssb_bus *bus; |
| 1457 | |
| 1458 | if (!dev) |
| 1459 | return; |
| 1460 | - bus = dev->bus; |
| 1461 | if (!ssb_device_is_enabled(dev)) |
| 1462 | ssb_device_enable(dev, 0); |
| 1463 | |
| 1464 | @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc |
| 1465 | pcicore_write32(pc, 0x134, data); |
| 1466 | } |
| 1467 | |
| 1468 | -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
| 1469 | - u8 address, u16 data) |
| 1470 | +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) |
| 1471 | +{ |
| 1472 | + const u16 mdio_control = 0x128; |
| 1473 | + const u16 mdio_data = 0x12C; |
| 1474 | + u32 v; |
| 1475 | + int i; |
| 1476 | + |
| 1477 | + v = (1 << 30); /* Start of Transaction */ |
| 1478 | + v |= (1 << 28); /* Write Transaction */ |
| 1479 | + v |= (1 << 17); /* Turnaround */ |
| 1480 | + v |= (0x1F << 18); |
| 1481 | + v |= (phy << 4); |
| 1482 | + pcicore_write32(pc, mdio_data, v); |
| 1483 | + |
| 1484 | + udelay(10); |
| 1485 | + for (i = 0; i < 200; i++) { |
| 1486 | + v = pcicore_read32(pc, mdio_control); |
| 1487 | + if (v & 0x100 /* Trans complete */) |
| 1488 | + break; |
| 1489 | + msleep(1); |
| 1490 | + } |
| 1491 | +} |
| 1492 | + |
| 1493 | +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) |
| 1494 | { |
| 1495 | const u16 mdio_control = 0x128; |
| 1496 | const u16 mdio_data = 0x12C; |
| 1497 | + int max_retries = 10; |
| 1498 | + u16 ret = 0; |
| 1499 | u32 v; |
| 1500 | int i; |
| 1501 | |
| 1502 | @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s |
| 1503 | v |= 0x2; /* MDIO Clock Divisor */ |
| 1504 | pcicore_write32(pc, mdio_control, v); |
| 1505 | |
| 1506 | + if (pc->dev->id.revision >= 10) { |
| 1507 | + max_retries = 200; |
| 1508 | + ssb_pcie_mdio_set_phy(pc, device); |
| 1509 | + } |
| 1510 | + |
| 1511 | v = (1 << 30); /* Start of Transaction */ |
| 1512 | - v |= (1 << 28); /* Write Transaction */ |
| 1513 | + v |= (1 << 29); /* Read Transaction */ |
| 1514 | v |= (1 << 17); /* Turnaround */ |
| 1515 | - v |= (u32)device << 22; |
| 1516 | + if (pc->dev->id.revision < 10) |
| 1517 | + v |= (u32)device << 22; |
| 1518 | v |= (u32)address << 18; |
| 1519 | - v |= data; |
| 1520 | pcicore_write32(pc, mdio_data, v); |
| 1521 | /* Wait for the device to complete the transaction */ |
| 1522 | udelay(10); |
| 1523 | - for (i = 0; i < 10; i++) { |
| 1524 | + for (i = 0; i < max_retries; i++) { |
| 1525 | v = pcicore_read32(pc, mdio_control); |
| 1526 | - if (v & 0x100 /* Trans complete */) |
| 1527 | + if (v & 0x100 /* Trans complete */) { |
| 1528 | + udelay(10); |
| 1529 | + ret = pcicore_read32(pc, mdio_data); |
| 1530 | break; |
| 1531 | + } |
| 1532 | msleep(1); |
| 1533 | } |
| 1534 | pcicore_write32(pc, mdio_control, 0); |
| 1535 | + return ret; |
| 1536 | } |
| 1537 | |
| 1538 | -static void ssb_broadcast_value(struct ssb_device *dev, |
| 1539 | - u32 address, u32 data) |
| 1540 | +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
| 1541 | + u8 address, u16 data) |
| 1542 | { |
| 1543 | - /* This is used for both, PCI and ChipCommon core, so be careful. */ |
| 1544 | - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); |
| 1545 | - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); |
| 1546 | + const u16 mdio_control = 0x128; |
| 1547 | + const u16 mdio_data = 0x12C; |
| 1548 | + int max_retries = 10; |
| 1549 | + u32 v; |
| 1550 | + int i; |
| 1551 | |
| 1552 | - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); |
| 1553 | - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ |
| 1554 | - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); |
| 1555 | - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ |
| 1556 | -} |
| 1557 | + v = 0x80; /* Enable Preamble Sequence */ |
| 1558 | + v |= 0x2; /* MDIO Clock Divisor */ |
| 1559 | + pcicore_write32(pc, mdio_control, v); |
| 1560 | |
| 1561 | -static void ssb_commit_settings(struct ssb_bus *bus) |
| 1562 | -{ |
| 1563 | - struct ssb_device *dev; |
| 1564 | + if (pc->dev->id.revision >= 10) { |
| 1565 | + max_retries = 200; |
| 1566 | + ssb_pcie_mdio_set_phy(pc, device); |
| 1567 | + } |
| 1568 | |
| 1569 | - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; |
| 1570 | - if (WARN_ON(!dev)) |
| 1571 | - return; |
| 1572 | - /* This forces an update of the cached registers. */ |
| 1573 | - ssb_broadcast_value(dev, 0xFD8, 0); |
| 1574 | + v = (1 << 30); /* Start of Transaction */ |
| 1575 | + v |= (1 << 28); /* Write Transaction */ |
| 1576 | + v |= (1 << 17); /* Turnaround */ |
| 1577 | + if (pc->dev->id.revision < 10) |
| 1578 | + v |= (u32)device << 22; |
| 1579 | + v |= (u32)address << 18; |
| 1580 | + v |= data; |
| 1581 | + pcicore_write32(pc, mdio_data, v); |
| 1582 | + /* Wait for the device to complete the transaction */ |
| 1583 | + udelay(10); |
| 1584 | + for (i = 0; i < max_retries; i++) { |
| 1585 | + v = pcicore_read32(pc, mdio_control); |
| 1586 | + if (v & 0x100 /* Trans complete */) |
| 1587 | + break; |
| 1588 | + msleep(1); |
| 1589 | + } |
| 1590 | + pcicore_write32(pc, mdio_control, 0); |
| 1591 | } |
| 1592 | |
| 1593 | int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, |
| 1594 | @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc |
| 1595 | if (pc->setup_done) |
| 1596 | goto out; |
| 1597 | if (pdev->id.coreid == SSB_DEV_PCI) { |
| 1598 | - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
| 1599 | - tmp |= SSB_PCICORE_SBTOPCI_PREF; |
| 1600 | - tmp |= SSB_PCICORE_SBTOPCI_BURST; |
| 1601 | - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
| 1602 | - |
| 1603 | - if (pdev->id.revision < 5) { |
| 1604 | - tmp = ssb_read32(pdev, SSB_IMCFGLO); |
| 1605 | - tmp &= ~SSB_IMCFGLO_SERTO; |
| 1606 | - tmp |= 2; |
| 1607 | - tmp &= ~SSB_IMCFGLO_REQTO; |
| 1608 | - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; |
| 1609 | - ssb_write32(pdev, SSB_IMCFGLO, tmp); |
| 1610 | - ssb_commit_settings(bus); |
| 1611 | - } else if (pdev->id.revision >= 11) { |
| 1612 | - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
| 1613 | - tmp |= SSB_PCICORE_SBTOPCI_MRM; |
| 1614 | - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
| 1615 | - } |
| 1616 | + ssb_pcicore_pci_setup_workarounds(pc); |
| 1617 | } else { |
| 1618 | WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); |
| 1619 | - //TODO: Better make defines for all these magic PCIE values. |
| 1620 | - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) { |
| 1621 | - /* TLP Workaround register. */ |
| 1622 | - tmp = ssb_pcie_read(pc, 0x4); |
| 1623 | - tmp |= 0x8; |
| 1624 | - ssb_pcie_write(pc, 0x4, tmp); |
| 1625 | - } |
| 1626 | - if (pdev->id.revision == 0) { |
| 1627 | - const u8 serdes_rx_device = 0x1F; |
| 1628 | - |
| 1629 | - ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 1630 | - 2 /* Timer */, 0x8128); |
| 1631 | - ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 1632 | - 6 /* CDR */, 0x0100); |
| 1633 | - ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 1634 | - 7 /* CDR BW */, 0x1466); |
| 1635 | - } else if (pdev->id.revision == 1) { |
| 1636 | - /* DLLP Link Control register. */ |
| 1637 | - tmp = ssb_pcie_read(pc, 0x100); |
| 1638 | - tmp |= 0x40; |
| 1639 | - ssb_pcie_write(pc, 0x100, tmp); |
| 1640 | - } |
| 1641 | + ssb_pcicore_pcie_setup_workarounds(pc); |
| 1642 | } |
| 1643 | pc->setup_done = 1; |
| 1644 | out: |
| 1645 | --- a/drivers/ssb/sprom.c |
| 1646 | +++ b/drivers/ssb/sprom.c |
| 1647 | @@ -2,7 +2,7 @@ |
| 1648 | * Sonics Silicon Backplane |
| 1649 | * Common SPROM support routines |
| 1650 | * |
| 1651 | - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de> |
| 1652 | + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch> |
| 1653 | * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> |
| 1654 | * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> |
| 1655 | * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> |
| 1656 | @@ -17,7 +17,7 @@ |
| 1657 | #include <linux/slab.h> |
| 1658 | |
| 1659 | |
| 1660 | -static const struct ssb_sprom *fallback_sprom; |
| 1661 | +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out); |
| 1662 | |
| 1663 | |
| 1664 | static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len, |
| 1665 | @@ -145,36 +145,43 @@ out: |
| 1666 | } |
| 1667 | |
| 1668 | /** |
| 1669 | - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found. |
| 1670 | + * ssb_arch_register_fallback_sprom - Registers a method providing a |
| 1671 | + * fallback SPROM if no SPROM is found. |
| 1672 | * |
| 1673 | - * @sprom: The SPROM data structure to register. |
| 1674 | + * @sprom_callback: The callback function. |
| 1675 | * |
| 1676 | - * With this function the architecture implementation may register a fallback |
| 1677 | - * SPROM data structure. The fallback is only used for PCI based SSB devices, |
| 1678 | - * where no valid SPROM can be found in the shadow registers. |
| 1679 | + * With this function the architecture implementation may register a |
| 1680 | + * callback handler which fills the SPROM data structure. The fallback is |
| 1681 | + * only used for PCI based SSB devices, where no valid SPROM can be found |
| 1682 | + * in the shadow registers. |
| 1683 | + * |
| 1684 | + * This function is useful for weird architectures that have a half-assed |
| 1685 | + * SSB device hardwired to their PCI bus. |
| 1686 | + * |
| 1687 | + * Note that it does only work with PCI attached SSB devices. PCMCIA |
| 1688 | + * devices currently don't use this fallback. |
| 1689 | + * Architectures must provide the SPROM for native SSB devices anyway, so |
| 1690 | + * the fallback also isn't used for native devices. |
| 1691 | * |
| 1692 | - * This function is useful for weird architectures that have a half-assed SSB device |
| 1693 | - * hardwired to their PCI bus. |
| 1694 | - * |
| 1695 | - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently |
| 1696 | - * don't use this fallback. |
| 1697 | - * Architectures must provide the SPROM for native SSB devices anyway, |
| 1698 | - * so the fallback also isn't used for native devices. |
| 1699 | - * |
| 1700 | - * This function is available for architecture code, only. So it is not exported. |
| 1701 | + * This function is available for architecture code, only. So it is not |
| 1702 | + * exported. |
| 1703 | */ |
| 1704 | -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom) |
| 1705 | +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus, |
| 1706 | + struct ssb_sprom *out)) |
| 1707 | { |
| 1708 | - if (fallback_sprom) |
| 1709 | + if (get_fallback_sprom) |
| 1710 | return -EEXIST; |
| 1711 | - fallback_sprom = sprom; |
| 1712 | + get_fallback_sprom = sprom_callback; |
| 1713 | |
| 1714 | return 0; |
| 1715 | } |
| 1716 | |
| 1717 | -const struct ssb_sprom *ssb_get_fallback_sprom(void) |
| 1718 | +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out) |
| 1719 | { |
| 1720 | - return fallback_sprom; |
| 1721 | + if (!get_fallback_sprom) |
| 1722 | + return -ENOENT; |
| 1723 | + |
| 1724 | + return get_fallback_sprom(bus, out); |
| 1725 | } |
| 1726 | |
| 1727 | /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ |
| 1728 | @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b |
| 1729 | /* this routine differs from specs as we do not access SPROM directly |
| 1730 | on PCMCIA */ |
| 1731 | if (bus->bustype == SSB_BUSTYPE_PCI && |
| 1732 | - bus->chipco.dev && /* can be unavailible! */ |
| 1733 | + bus->chipco.dev && /* can be unavailable! */ |
| 1734 | bus->chipco.dev->id.revision >= 31) |
| 1735 | return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM; |
| 1736 | |
| 1737 | --- a/drivers/ssb/ssb_private.h |
| 1738 | +++ b/drivers/ssb/ssb_private.h |
| 1739 | @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_ |
| 1740 | const char *buf, size_t count, |
| 1741 | int (*sprom_check_crc)(const u16 *sprom, size_t size), |
| 1742 | int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom)); |
| 1743 | -extern const struct ssb_sprom *ssb_get_fallback_sprom(void); |
| 1744 | +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, |
| 1745 | + struct ssb_sprom *out); |
| 1746 | |
| 1747 | |
| 1748 | /* core.c */ |
| 1749 | --- a/include/linux/ssb/ssb_driver_chipcommon.h |
| 1750 | +++ b/include/linux/ssb/ssb_driver_chipcommon.h |
| 1751 | @@ -8,7 +8,7 @@ |
| 1752 | * gpio interface, extbus, and support for serial and parallel flashes. |
| 1753 | * |
| 1754 | * Copyright 2005, Broadcom Corporation |
| 1755 | - * Copyright 2006, Michael Buesch <mb@bu3sch.de> |
| 1756 | + * Copyright 2006, Michael Buesch <m@bues.ch> |
| 1757 | * |
| 1758 | * Licensed under the GPL version 2. See COPYING for details. |
| 1759 | */ |
| 1760 | @@ -123,6 +123,8 @@ |
| 1761 | #define SSB_CHIPCO_FLASHDATA 0x0048 |
| 1762 | #define SSB_CHIPCO_BCAST_ADDR 0x0050 |
| 1763 | #define SSB_CHIPCO_BCAST_DATA 0x0054 |
| 1764 | +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */ |
| 1765 | +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */ |
| 1766 | #define SSB_CHIPCO_GPIOIN 0x0060 |
| 1767 | #define SSB_CHIPCO_GPIOOUT 0x0064 |
| 1768 | #define SSB_CHIPCO_GPIOOUTEN 0x0068 |
| 1769 | @@ -131,6 +133,9 @@ |
| 1770 | #define SSB_CHIPCO_GPIOIRQ 0x0074 |
| 1771 | #define SSB_CHIPCO_WATCHDOG 0x0080 |
| 1772 | #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ |
| 1773 | +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF |
| 1774 | +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0 |
| 1775 | +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000 |
| 1776 | #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16 |
| 1777 | #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ |
| 1778 | #define SSB_CHIPCO_CLOCK_N 0x0090 |
| 1779 | @@ -189,8 +194,10 @@ |
| 1780 | #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */ |
| 1781 | #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ |
| 1782 | #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ |
| 1783 | -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */ |
| 1784 | -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */ |
| 1785 | +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */ |
| 1786 | +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */ |
| 1787 | +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */ |
| 1788 | +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */ |
| 1789 | #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ |
| 1790 | #define SSB_CHIPCO_UART0_DATA 0x0300 |
| 1791 | #define SSB_CHIPCO_UART0_IMR 0x0304 |
| 1792 | --- a/drivers/ssb/b43_pci_bridge.c |
| 1793 | +++ b/drivers/ssb/b43_pci_bridge.c |
| 1794 | @@ -5,12 +5,13 @@ |
| 1795 | * because of its small size we include it in the SSB core |
| 1796 | * instead of creating a standalone module. |
| 1797 | * |
| 1798 | - * Copyright 2007 Michael Buesch <mb@bu3sch.de> |
| 1799 | + * Copyright 2007 Michael Buesch <m@bues.ch> |
| 1800 | * |
| 1801 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1802 | */ |
| 1803 | |
| 1804 | #include <linux/pci.h> |
| 1805 | +#include <linux/module.h> |
| 1806 | #include <linux/ssb/ssb.h> |
| 1807 | |
| 1808 | #include "ssb_private.h" |
| 1809 | --- a/drivers/ssb/driver_extif.c |
| 1810 | +++ b/drivers/ssb/driver_extif.c |
| 1811 | @@ -3,7 +3,7 @@ |
| 1812 | * Broadcom EXTIF core driver |
| 1813 | * |
| 1814 | * Copyright 2005, Broadcom Corporation |
| 1815 | - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> |
| 1816 | + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
| 1817 | * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org> |
| 1818 | * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net> |
| 1819 | * |
| 1820 | --- a/drivers/ssb/driver_mipscore.c |
| 1821 | +++ b/drivers/ssb/driver_mipscore.c |
| 1822 | @@ -3,7 +3,7 @@ |
| 1823 | * Broadcom MIPS core driver |
| 1824 | * |
| 1825 | * Copyright 2005, Broadcom Corporation |
| 1826 | - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> |
| 1827 | + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
| 1828 | * |
| 1829 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1830 | */ |
| 1831 | --- a/drivers/ssb/embedded.c |
| 1832 | +++ b/drivers/ssb/embedded.c |
| 1833 | @@ -3,7 +3,7 @@ |
| 1834 | * Embedded systems support code |
| 1835 | * |
| 1836 | * Copyright 2005-2008, Broadcom Corporation |
| 1837 | - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de> |
| 1838 | + * Copyright 2006-2008, Michael Buesch <m@bues.ch> |
| 1839 | * |
| 1840 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1841 | */ |
| 1842 | --- a/drivers/ssb/pcmcia.c |
| 1843 | +++ b/drivers/ssb/pcmcia.c |
| 1844 | @@ -3,7 +3,7 @@ |
| 1845 | * PCMCIA-Hostbus related functions |
| 1846 | * |
| 1847 | * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> |
| 1848 | - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de> |
| 1849 | + * Copyright 2007-2008 Michael Buesch <m@bues.ch> |
| 1850 | * |
| 1851 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1852 | */ |
| 1853 | --- a/drivers/ssb/sdio.c |
| 1854 | +++ b/drivers/ssb/sdio.c |
| 1855 | @@ -6,7 +6,7 @@ |
| 1856 | * |
| 1857 | * Based on drivers/ssb/pcmcia.c |
| 1858 | * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> |
| 1859 | - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de> |
| 1860 | + * Copyright 2007-2008 Michael Buesch <m@bues.ch> |
| 1861 | * |
| 1862 | * Licensed under the GNU/GPL. See COPYING for details. |
| 1863 | * |
| 1864 | |
