Root/target/linux/generic/patches-3.1/020-ssb_update.patch

1--- a/drivers/ssb/b43_pci_bridge.c
2+++ b/drivers/ssb/b43_pci_bridge.c
3@@ -11,6 +11,7 @@
4  */
5 
6 #include <linux/pci.h>
7+#include <linux/module.h>
8 #include <linux/ssb/ssb.h>
9 
10 #include "ssb_private.h"
11--- a/drivers/ssb/main.c
12+++ b/drivers/ssb/main.c
13@@ -12,6 +12,7 @@
14 
15 #include <linux/delay.h>
16 #include <linux/io.h>
17+#include <linux/module.h>
18 #include <linux/ssb/ssb.h>
19 #include <linux/ssb/ssb_regs.h>
20 #include <linux/ssb/ssb_driver_gige.h>
21@@ -1260,16 +1261,34 @@ void ssb_device_disable(struct ssb_devic
22 }
23 EXPORT_SYMBOL(ssb_device_disable);
24 
25+/* Some chipsets need routing known for PCIe and 64-bit DMA */
26+static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
27+{
28+ u16 chip_id = dev->bus->chip_id;
29+
30+ if (dev->id.coreid == SSB_DEV_80211) {
31+ return (chip_id == 0x4322 || chip_id == 43221 ||
32+ chip_id == 43231 || chip_id == 43222);
33+ }
34+
35+ return 0;
36+}
37+
38 u32 ssb_dma_translation(struct ssb_device *dev)
39 {
40     switch (dev->bus->bustype) {
41     case SSB_BUSTYPE_SSB:
42         return 0;
43     case SSB_BUSTYPE_PCI:
44- if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
45+ if (pci_is_pcie(dev->bus->host_pci) &&
46+ ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
47             return SSB_PCIE_DMA_H32;
48- else
49- return SSB_PCI_DMA;
50+ } else {
51+ if (ssb_dma_translation_special_bit(dev))
52+ return SSB_PCIE_DMA_H32;
53+ else
54+ return SSB_PCI_DMA;
55+ }
56     default:
57         __ssb_dma_not_implemented(dev);
58     }
59--- a/drivers/ssb/pci.c
60+++ b/drivers/ssb/pci.c
61@@ -523,7 +523,13 @@ static void sprom_extract_r45(struct ssb
62 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
63 {
64     int i;
65- u16 v;
66+ u16 v, o;
67+ u16 pwr_info_offset[] = {
68+ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
69+ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
70+ };
71+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
72+ ARRAY_SIZE(out->core_pwr_info));
73 
74     /* extract the MAC address */
75     for (i = 0; i < 3; i++) {
76@@ -607,6 +613,61 @@ static void sprom_extract_r8(struct ssb_
77     memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
78            sizeof(out->antenna_gain.ghz5));
79 
80+ /* Extract cores power info info */
81+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
82+ o = pwr_info_offset[i];
83+ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
84+ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
85+ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
86+ SSB_SPROM8_2G_MAXP, 0);
87+
88+ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
89+ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
90+ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
91+
92+ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
93+ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
94+ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
95+ SSB_SPROM8_5G_MAXP, 0);
96+ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
97+ SSB_SPROM8_5GH_MAXP, 0);
98+ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
99+ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
100+
101+ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
102+ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
103+ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
104+ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
105+ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
106+ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
107+ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
108+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
109+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
110+ }
111+
112+ /* Extract FEM info */
113+ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
114+ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
115+ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
116+ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
117+ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
118+ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
119+ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
120+ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
121+ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
122+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
123+
124+ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
125+ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
126+ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
127+ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
128+ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
129+ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
130+ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
131+ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
132+ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
133+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
134+
135     sprom_extract_r458(out, in);
136 
137     /* TODO - get remaining rev 8 stuff needed */
138--- a/include/linux/ssb/ssb.h
139+++ b/include/linux/ssb/ssb.h
140@@ -16,6 +16,12 @@ struct pcmcia_device;
141 struct ssb_bus;
142 struct ssb_driver;
143 
144+struct ssb_sprom_core_pwr_info {
145+ u8 itssi_2g, itssi_5g;
146+ u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
147+ u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
148+};
149+
150 struct ssb_sprom {
151     u8 revision;
152     u8 il0mac[6]; /* MAC address for 802.11b/g */
153@@ -25,7 +31,7 @@ struct ssb_sprom {
154     u8 et1phyaddr; /* MII address for enet1 */
155     u8 et0mdcport; /* MDIO for enet0 */
156     u8 et1mdcport; /* MDIO for enet1 */
157- u8 board_rev; /* Board revision number from SPROM. */
158+ u16 board_rev; /* Board revision number from SPROM. */
159     u8 country_code; /* Country Code */
160     u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
161     u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
162@@ -82,6 +88,8 @@ struct ssb_sprom {
163     u16 boardflags2_hi; /* Board flags (bits 48-63) */
164     /* TODO store board flags in a single u64 */
165 
166+ struct ssb_sprom_core_pwr_info core_pwr_info[4];
167+
168     /* Antenna gain values for up to 4 antennas
169      * on each band. Values in dBm/4 (Q5.2). Negative gain means the
170      * loss in the connectors is bigger than the gain. */
171@@ -94,6 +102,15 @@ struct ssb_sprom {
172         } ghz5; /* 5GHz band */
173     } antenna_gain;
174 
175+ struct {
176+ struct {
177+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
178+ } ghz2;
179+ struct {
180+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
181+ } ghz5;
182+ } fem;
183+
184     /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
185 };
186 
187@@ -231,10 +248,9 @@ struct ssb_driver {
188 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
189 
190 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
191-static inline int ssb_driver_register(struct ssb_driver *drv)
192-{
193- return __ssb_driver_register(drv, THIS_MODULE);
194-}
195+#define ssb_driver_register(drv) \
196+ __ssb_driver_register(drv, THIS_MODULE)
197+
198 extern void ssb_driver_unregister(struct ssb_driver *drv);
199 
200 
201--- a/include/linux/ssb/ssb_regs.h
202+++ b/include/linux/ssb/ssb_regs.h
203@@ -432,6 +432,56 @@
204 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
205 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
206 #define SSB_SPROM8_RXPO5G_SHIFT 8
207+#define SSB_SPROM8_FEM2G 0x00AE
208+#define SSB_SPROM8_FEM5G 0x00B0
209+#define SSB_SROM8_FEM_TSSIPOS 0x0001
210+#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
211+#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
212+#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
213+#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
214+#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
215+#define SSB_SROM8_FEM_TR_ISO 0x0700
216+#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
217+#define SSB_SROM8_FEM_ANTSWLUT 0xF800
218+#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
219+#define SSB_SPROM8_THERMAL 0x00B2
220+#define SSB_SPROM8_MPWR_RAWTS 0x00B4
221+#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
222+#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
223+#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
224+
225+/* There are 4 blocks with power info sharing the same layout */
226+#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
227+#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
228+#define SSB_SROM8_PWR_INFO_CORE2 0x0100
229+#define SSB_SROM8_PWR_INFO_CORE3 0x0120
230+
231+#define SSB_SROM8_2G_MAXP_ITSSI 0x00
232+#define SSB_SPROM8_2G_MAXP 0x00FF
233+#define SSB_SPROM8_2G_ITSSI 0xFF00
234+#define SSB_SPROM8_2G_ITSSI_SHIFT 8
235+#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
236+#define SSB_SROM8_2G_PA_1 0x04
237+#define SSB_SROM8_2G_PA_2 0x06
238+#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
239+#define SSB_SPROM8_5G_MAXP 0x00FF
240+#define SSB_SPROM8_5G_ITSSI 0xFF00
241+#define SSB_SPROM8_5G_ITSSI_SHIFT 8
242+#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
243+#define SSB_SPROM8_5GH_MAXP 0x00FF
244+#define SSB_SPROM8_5GL_MAXP 0xFF00
245+#define SSB_SPROM8_5GL_MAXP_SHIFT 8
246+#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
247+#define SSB_SROM8_5G_PA_1 0x0E
248+#define SSB_SROM8_5G_PA_2 0x10
249+#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
250+#define SSB_SROM8_5GL_PA_1 0x14
251+#define SSB_SROM8_5GL_PA_2 0x16
252+#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
253+#define SSB_SROM8_5GH_PA_1 0x1A
254+#define SSB_SROM8_5GH_PA_2 0x1C
255+
256+/* TODO: Make it deprecated */
257 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
258 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
259 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
260@@ -456,12 +506,53 @@
261 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
262 #define SSB_SPROM8_PA1HIB1 0x00DA
263 #define SSB_SPROM8_PA1HIB2 0x00DC
264+
265 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
266 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
267 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
268 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
269 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
270 
271+/* Values for boardflags_lo read from SPROM */
272+#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
273+#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
274+#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
275+#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
276+#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
277+#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
278+#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
279+#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
280+#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
281+#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
282+#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
283+#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
284+#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
285+#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
286+#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
287+#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
288+
289+/* Values for boardflags_hi read from SPROM */
290+#define SSB_BFH_NOPA 0x0001 /* has no PA */
291+#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
292+#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
293+#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
294+#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
295+#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
296+#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
297+
298+/* Values for boardflags2_lo read from SPROM */
299+#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
300+#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
301+#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
302+#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
303+#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
304+#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
305+#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
306+#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
307+#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
308+#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
309+#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
310+
311 /* Values for SSB_SPROM1_BINF_CCODE */
312 enum {
313     SSB_SPROM1CCODE_WORLD = 0,
314

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