Root/target/linux/generic/patches-3.2/020-ssb_update.patch

1--- a/drivers/ssb/pci.c
2+++ b/drivers/ssb/pci.c
3@@ -523,7 +523,13 @@ static void sprom_extract_r45(struct ssb
4 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
5 {
6     int i;
7- u16 v;
8+ u16 v, o;
9+ u16 pwr_info_offset[] = {
10+ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
11+ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
12+ };
13+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
14+ ARRAY_SIZE(out->core_pwr_info));
15 
16     /* extract the MAC address */
17     for (i = 0; i < 3; i++) {
18@@ -607,6 +613,61 @@ static void sprom_extract_r8(struct ssb_
19     memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
20            sizeof(out->antenna_gain.ghz5));
21 
22+ /* Extract cores power info info */
23+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
24+ o = pwr_info_offset[i];
25+ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
26+ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
27+ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
28+ SSB_SPROM8_2G_MAXP, 0);
29+
30+ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
31+ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
32+ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
33+
34+ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
35+ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
36+ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
37+ SSB_SPROM8_5G_MAXP, 0);
38+ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
39+ SSB_SPROM8_5GH_MAXP, 0);
40+ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
41+ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
42+
43+ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
44+ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
45+ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
46+ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
47+ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
48+ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
49+ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
50+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
51+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
52+ }
53+
54+ /* Extract FEM info */
55+ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
56+ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
57+ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
58+ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
59+ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
60+ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
61+ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
62+ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
63+ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
64+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
65+
66+ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
67+ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
68+ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
69+ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
70+ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
71+ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
72+ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
73+ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
74+ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
75+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
76+
77     sprom_extract_r458(out, in);
78 
79     /* TODO - get remaining rev 8 stuff needed */
80--- a/include/linux/ssb/ssb.h
81+++ b/include/linux/ssb/ssb.h
82@@ -16,6 +16,12 @@ struct pcmcia_device;
83 struct ssb_bus;
84 struct ssb_driver;
85 
86+struct ssb_sprom_core_pwr_info {
87+ u8 itssi_2g, itssi_5g;
88+ u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
89+ u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
90+};
91+
92 struct ssb_sprom {
93     u8 revision;
94     u8 il0mac[6]; /* MAC address for 802.11b/g */
95@@ -82,6 +88,8 @@ struct ssb_sprom {
96     u16 boardflags2_hi; /* Board flags (bits 48-63) */
97     /* TODO store board flags in a single u64 */
98 
99+ struct ssb_sprom_core_pwr_info core_pwr_info[4];
100+
101     /* Antenna gain values for up to 4 antennas
102      * on each band. Values in dBm/4 (Q5.2). Negative gain means the
103      * loss in the connectors is bigger than the gain. */
104@@ -94,6 +102,15 @@ struct ssb_sprom {
105         } ghz5; /* 5GHz band */
106     } antenna_gain;
107 
108+ struct {
109+ struct {
110+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
111+ } ghz2;
112+ struct {
113+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
114+ } ghz5;
115+ } fem;
116+
117     /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
118 };
119 
120--- a/include/linux/ssb/ssb_regs.h
121+++ b/include/linux/ssb/ssb_regs.h
122@@ -432,6 +432,56 @@
123 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
124 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
125 #define SSB_SPROM8_RXPO5G_SHIFT 8
126+#define SSB_SPROM8_FEM2G 0x00AE
127+#define SSB_SPROM8_FEM5G 0x00B0
128+#define SSB_SROM8_FEM_TSSIPOS 0x0001
129+#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
130+#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
131+#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
132+#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
133+#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
134+#define SSB_SROM8_FEM_TR_ISO 0x0700
135+#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
136+#define SSB_SROM8_FEM_ANTSWLUT 0xF800
137+#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
138+#define SSB_SPROM8_THERMAL 0x00B2
139+#define SSB_SPROM8_MPWR_RAWTS 0x00B4
140+#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
141+#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
142+#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
143+
144+/* There are 4 blocks with power info sharing the same layout */
145+#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
146+#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
147+#define SSB_SROM8_PWR_INFO_CORE2 0x0100
148+#define SSB_SROM8_PWR_INFO_CORE3 0x0120
149+
150+#define SSB_SROM8_2G_MAXP_ITSSI 0x00
151+#define SSB_SPROM8_2G_MAXP 0x00FF
152+#define SSB_SPROM8_2G_ITSSI 0xFF00
153+#define SSB_SPROM8_2G_ITSSI_SHIFT 8
154+#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
155+#define SSB_SROM8_2G_PA_1 0x04
156+#define SSB_SROM8_2G_PA_2 0x06
157+#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
158+#define SSB_SPROM8_5G_MAXP 0x00FF
159+#define SSB_SPROM8_5G_ITSSI 0xFF00
160+#define SSB_SPROM8_5G_ITSSI_SHIFT 8
161+#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
162+#define SSB_SPROM8_5GH_MAXP 0x00FF
163+#define SSB_SPROM8_5GL_MAXP 0xFF00
164+#define SSB_SPROM8_5GL_MAXP_SHIFT 8
165+#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
166+#define SSB_SROM8_5G_PA_1 0x0E
167+#define SSB_SROM8_5G_PA_2 0x10
168+#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
169+#define SSB_SROM8_5GL_PA_1 0x14
170+#define SSB_SROM8_5GL_PA_2 0x16
171+#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
172+#define SSB_SROM8_5GH_PA_1 0x1A
173+#define SSB_SROM8_5GH_PA_2 0x1C
174+
175+/* TODO: Make it deprecated */
176 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
177 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
178 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
179@@ -456,6 +506,7 @@
180 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
181 #define SSB_SPROM8_PA1HIB1 0x00DA
182 #define SSB_SPROM8_PA1HIB2 0x00DC
183+
184 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
185 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
186 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
187@@ -464,6 +515,46 @@
188 
189 /* Values for boardflags_lo read from SPROM */
190 #define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
191+#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
192+#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
193+#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
194+#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
195+#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
196+#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
197+#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
198+#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
199+#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
200+#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
201+#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
202+#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
203+#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
204+#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
205+#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
206+
207+/* Values for boardflags_hi read from SPROM */
208+#define SSB_BFH_NOPA 0x0001 /* has no PA */
209+#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
210+#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
211+#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
212+#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
213+#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
214+#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
215+
216+/* Values for boardflags2_lo read from SPROM */
217+#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
218+#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
219+#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
220+#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
221+#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
222+#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
223+#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
224+#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
225+#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
226+#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
227+#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
228+
229+/* Values for boardflags_lo read from SPROM */
230+#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
231 #define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
232 #define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
233 #define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
234

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive