Root/target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch

1From 92b24777385cd8388e0fa8b9f1d24e5bc4466641 Mon Sep 17 00:00:00 2001
2From: John Crispin <blogic@openwrt.org>
3Date: Sat, 13 Aug 2011 13:59:50 +0200
4Subject: [PATCH 12/22] MIPS: lantiq: make GPIO3 work on AR9
5
6There are 3 16bit and 1 8bit gpio ports on AR9. The gpio driver needs a hack
7at 2 places to make the different register layout of the GPIO3 work properly
8with the driver. Before only GPIO0-2 were supported. As the GPIO number scheme
9clashes with the new size, we also move the other gpio chips to new offsets.
10
11Signed-off-by: John Crispin <blogic@openwrt.org>
12Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
13---
14 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +
15 arch/mips/lantiq/xway/devices.c | 3 +
16 arch/mips/lantiq/xway/gpio.c | 62 ++++++++++++++++----
17 arch/mips/lantiq/xway/gpio_ebu.c | 3 +-
18 arch/mips/lantiq/xway/gpio_stp.c | 3 +-
19 5 files changed, 57 insertions(+), 16 deletions(-)
20
21--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
22+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
23@@ -121,7 +121,9 @@
24 #define LTQ_GPIO0_BASE_ADDR 0x1E100B10
25 #define LTQ_GPIO1_BASE_ADDR 0x1E100B40
26 #define LTQ_GPIO2_BASE_ADDR 0x1E100B70
27+#define LTQ_GPIO3_BASE_ADDR 0x1E100BA0
28 #define LTQ_GPIO_SIZE 0x30
29+#define LTQ_GPIO3_SIZE 0x10
30 
31 /* SSC */
32 #define LTQ_SSC_BASE_ADDR 0x1e100800
33--- a/arch/mips/lantiq/xway/devices.c
34+++ b/arch/mips/lantiq/xway/devices.c
35@@ -34,6 +34,7 @@ static struct resource ltq_gpio_resource
36     MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
37     MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
38     MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
39+ MEM_RES("gpio3", LTQ_GPIO3_BASE_ADDR, LTQ_GPIO3_SIZE),
40 };
41 
42 void __init ltq_register_gpio(void)
43@@ -47,6 +48,8 @@ void __init ltq_register_gpio(void)
44     if (ltq_is_ar9() || ltq_is_vr9()) {
45         platform_device_register_simple("ltq_gpio", 2,
46             &ltq_gpio_resource[2], 1);
47+ platform_device_register_simple("ltq_gpio", 3,
48+ &ltq_gpio_resource[3], 1);
49     }
50 }
51 
52--- a/arch/mips/lantiq/xway/gpio.c
53+++ b/arch/mips/lantiq/xway/gpio.c
54@@ -23,9 +23,15 @@
55 #define LTQ_GPIO_OD 0x14
56 #define LTQ_GPIO_PUDSEL 0x1C
57 #define LTQ_GPIO_PUDEN 0x20
58+#define LTQ_GPIO3_OD 0x24
59+#define LTQ_GPIO3_ALTSEL1 0x24
60 
61+/* PORT3 only has 8 pins and its register layout
62+ is slightly different */
63 #define PINS_PER_PORT 16
64-#define MAX_PORTS 3
65+#define PINS_PORT3 8
66+#define MAX_PORTS 4
67+#define MAX_PIN 56
68 
69 #define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
70 #define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r)
71@@ -55,7 +61,7 @@ int ltq_gpio_request(unsigned int pin, u
72 {
73     int id = 0;
74 
75- if (pin >= (MAX_PORTS * PINS_PER_PORT))
76+ if (pin >= MAX_PIN)
77         return -EINVAL;
78     if (gpio_request(pin, name)) {
79         pr_err("failed to setup lantiq gpio: %s\n", name);
80@@ -75,12 +81,21 @@ int ltq_gpio_request(unsigned int pin, u
81     else
82         ltq_gpio_clearbit(ltq_gpio_port[id].membase,
83             LTQ_GPIO_ALTSEL0, pin);
84- if (alt1)
85- ltq_gpio_setbit(ltq_gpio_port[id].membase,
86- LTQ_GPIO_ALTSEL1, pin);
87- else
88- ltq_gpio_clearbit(ltq_gpio_port[id].membase,
89- LTQ_GPIO_ALTSEL1, pin);
90+ if (id == 3) {
91+ if (alt1)
92+ ltq_gpio_setbit(ltq_gpio_port[1].membase,
93+ LTQ_GPIO3_ALTSEL1, pin);
94+ else
95+ ltq_gpio_clearbit(ltq_gpio_port[1].membase,
96+ LTQ_GPIO3_ALTSEL1, pin);
97+ } else {
98+ if (alt1)
99+ ltq_gpio_setbit(ltq_gpio_port[id].membase,
100+ LTQ_GPIO_ALTSEL1, pin);
101+ else
102+ ltq_gpio_clearbit(ltq_gpio_port[id].membase,
103+ LTQ_GPIO_ALTSEL1, pin);
104+ }
105     return 0;
106 }
107 EXPORT_SYMBOL(ltq_gpio_request);
108@@ -106,7 +121,11 @@ static int ltq_gpio_direction_input(stru
109 {
110     struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
111 
112- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
113+ if (chip->ngpio == PINS_PORT3)
114+ ltq_gpio_clearbit(ltq_gpio_port[0].membase,
115+ LTQ_GPIO3_OD, offset);
116+ else
117+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
118     ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
119     ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
120     ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
121@@ -119,7 +138,10 @@ static int ltq_gpio_direction_output(str
122 {
123     struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
124 
125- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
126+ if (chip->ngpio == PINS_PORT3)
127+ ltq_gpio_setbit(ltq_gpio_port[0].membase, LTQ_GPIO3_OD, offset);
128+ else
129+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
130     ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
131     ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
132     ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
133@@ -133,7 +155,11 @@ static int ltq_gpio_req(struct gpio_chip
134     struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
135 
136     ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
137- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
138+ if (chip->ngpio == PINS_PORT3)
139+ ltq_gpio_clearbit(ltq_gpio_port[1].membase,
140+ LTQ_GPIO3_ALTSEL1, offset);
141+ else
142+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
143     return 0;
144 }
145 
146@@ -146,6 +172,15 @@ static int ltq_gpio_probe(struct platfor
147             pdev->id);
148         return -EINVAL;
149     }
150+
151+ /* dirty hack - The registers of port3 are not mapped linearly.
152+ Port 3 may only load if Port 1/2 are mapped */
153+ if ((pdev->id == 3) && (!ltq_gpio_port[1].membase || !ltq_gpio_port[2].membase)) {
154+ dev_err(&pdev->dev,
155+ "ports 1/2 need to be loaded before port 3 works\n");
156+ return -ENOMEM;
157+ }
158+
159     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
160     if (!res) {
161         dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
162@@ -175,7 +210,10 @@ static int ltq_gpio_probe(struct platfor
163     ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
164     ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
165     ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
166- ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
167+ if (pdev->id == 3)
168+ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PORT3;
169+ else
170+ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
171     platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
172     return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
173 }
174--- a/arch/mips/lantiq/xway/gpio_ebu.c
175+++ b/arch/mips/lantiq/xway/gpio_ebu.c
176@@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = {
177     .label = "ltq_ebu",
178     .direction_output = ltq_ebu_direction_output,
179     .set = ltq_ebu_set,
180- .base = 72,
181+ .base = 100,
182     .ngpio = 16,
183- .can_sleep = 1,
184     .owner = THIS_MODULE,
185 };
186 
187--- a/arch/mips/lantiq/xway/gpio_stp.c
188+++ b/arch/mips/lantiq/xway/gpio_stp.c
189@@ -72,9 +72,8 @@ static struct gpio_chip ltq_stp_chip = {
190     .label = "ltq_stp",
191     .direction_output = ltq_stp_direction_output,
192     .set = ltq_stp_set,
193- .base = 48,
194+ .base = 200,
195     .ngpio = 24,
196- .can_sleep = 1,
197     .owner = THIS_MODULE,
198 };
199 
200

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