| 1 | --- a/arch/mips/lantiq/falcon/prom.c |
| 2 | +++ b/arch/mips/lantiq/falcon/prom.c |
| 3 | @@ -14,6 +14,9 @@ |
| 4 | #include "../prom.h" |
| 5 | |
| 6 | #define SOC_FALCON "Falcon" |
| 7 | +#define SOC_FALCON_D "Falcon-D" |
| 8 | +#define SOC_FALCON_V "Falcon-V" |
| 9 | +#define SOC_FALCON_M "Falcon-M" |
| 10 | |
| 11 | #define PART_SHIFT 12 |
| 12 | #define PART_MASK 0x0FFFF000 |
| 13 | @@ -21,6 +24,8 @@ |
| 14 | #define REV_MASK 0xF0000000 |
| 15 | #define SREV_SHIFT 22 |
| 16 | #define SREV_MASK 0x03C00000 |
| 17 | +#define TYPE_SHIFT 26 |
| 18 | +#define TYPE_MASK 0x3C000000 |
| 19 | |
| 20 | #define MUXC_SIF_RX_PIN 112 |
| 21 | #define MUXC_SIF_TX_PIN 113 |
| 22 | @@ -54,14 +59,30 @@ ltq_soc_setup(void) |
| 23 | void __init |
| 24 | ltq_soc_detect(struct ltq_soc_info *i) |
| 25 | { |
| 26 | + u32 type; |
| 27 | i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; |
| 28 | i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; |
| 29 | - i->srev = (ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT; |
| 30 | + i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT); |
| 31 | sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), |
| 32 | - i->rev & 0x7, i->srev & 0x3); |
| 33 | + i->rev & 0x7, (i->srev & 0x3) + 1); |
| 34 | + |
| 35 | switch (i->partnum) { |
| 36 | case SOC_ID_FALCON: |
| 37 | - i->name = SOC_FALCON; |
| 38 | + type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT; |
| 39 | + switch (type) { |
| 40 | + case 0: |
| 41 | + i->name = SOC_FALCON_D; |
| 42 | + break; |
| 43 | + case 1: |
| 44 | + i->name = SOC_FALCON_V; |
| 45 | + break; |
| 46 | + case 2: |
| 47 | + i->name = SOC_FALCON_M; |
| 48 | + break; |
| 49 | + default: |
| 50 | + i->name = SOC_FALCON; |
| 51 | + break; |
| 52 | + } |
| 53 | i->type = SOC_TYPE_FALCON; |
| 54 | break; |
| 55 | |
| 56 | --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h |
| 57 | +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h |
| 58 | @@ -78,6 +78,7 @@ |
| 59 | #define LTQ_STATUS_BASE_ADDR 0x1E802000 |
| 60 | |
| 61 | #define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) |
| 62 | +#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) |
| 63 | #define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) |
| 64 | |
| 65 | /* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ |
| 66 | |
