| 1 | --- a/arch/arm/mach-omap2/board-n8x0.c |
| 2 | +++ b/arch/arm/mach-omap2/board-n8x0.c |
| 3 | @@ -24,6 +24,7 @@ |
| 4 | #include <linux/spi/spi.h> |
| 5 | #include <linux/usb/musb.h> |
| 6 | #include <sound/tlv320aic3x.h> |
| 7 | +#include <linux/spi/tsc2005.h> |
| 8 | |
| 9 | #include <asm/mach/arch.h> |
| 10 | #include <asm/mach-types.h> |
| 11 | @@ -43,6 +44,66 @@ static int slot1_cover_open; |
| 12 | static int slot2_cover_open; |
| 13 | static struct device *mmc_device; |
| 14 | |
| 15 | +#define RX51_TSC2005_RESET_GPIO 94 |
| 16 | +#define RX51_TSC2005_IRQ_GPIO 106 |
| 17 | + |
| 18 | +#ifdef CONFIG_TOUCHSCREEN_TSC2005 |
| 19 | +static struct tsc2005_platform_data tsc2005_config; |
| 20 | +static void rx51_tsc2005_set_reset(bool enable) |
| 21 | +{ |
| 22 | + gpio_set_value(RX51_TSC2005_RESET_GPIO, enable); |
| 23 | +} |
| 24 | + |
| 25 | +static struct omap2_mcspi_device_config tsc2005_mcspi_config = { |
| 26 | + .turbo_mode = 0, |
| 27 | + .single_channel = 1, |
| 28 | +}; |
| 29 | +#endif |
| 30 | + |
| 31 | +static void __init tsc2005_set_config(void) |
| 32 | +{ |
| 33 | + const struct omap_lcd_config *conf; |
| 34 | + |
| 35 | + conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config); |
| 36 | + if (conf != NULL) { |
| 37 | +#ifdef CONFIG_TOUCHSCREEN_TSC2005 |
| 38 | + if (strcmp(conf->panel_name, "lph8923") == 0) { |
| 39 | + tsc2005_config.ts_x_plate_ohm = 180; |
| 40 | + tsc2005_config.ts_pressure_max = 2048; |
| 41 | + tsc2005_config.ts_pressure_fudge = 2; |
| 42 | + tsc2005_config.ts_x_max = 4096; |
| 43 | + tsc2005_config.ts_x_fudge = 4; |
| 44 | + tsc2005_config.ts_y_max = 4096; |
| 45 | + tsc2005_config.ts_y_fudge = 7; |
| 46 | + tsc2005_config.set_reset = rx51_tsc2005_set_reset; |
| 47 | + } else if (strcmp(conf->panel_name, "ls041y3") == 0) { |
| 48 | + tsc2005_config.ts_x_plate_ohm = 280; |
| 49 | + tsc2005_config.ts_pressure_max = 2048; |
| 50 | + tsc2005_config.ts_pressure_fudge = 2; |
| 51 | + tsc2005_config.ts_x_max = 4096; |
| 52 | + tsc2005_config.ts_x_fudge = 4; |
| 53 | + tsc2005_config.ts_y_max = 4096; |
| 54 | + tsc2005_config.ts_y_fudge = 7; |
| 55 | + tsc2005_config.set_reset = rx51_tsc2005_set_reset; |
| 56 | + } else { |
| 57 | + printk(KERN_ERR "Unknown panel type, set default " |
| 58 | + "touchscreen configuration\n"); |
| 59 | + tsc2005_config.ts_x_plate_ohm = 200; |
| 60 | + } |
| 61 | +#endif |
| 62 | + } |
| 63 | +} |
| 64 | + |
| 65 | +static struct omap2_mcspi_device_config mipid_mcspi_config = { |
| 66 | + .turbo_mode = 0, |
| 67 | + .single_channel = 1, |
| 68 | +}; |
| 69 | + |
| 70 | +extern struct mipid_platform_data n8x0_mipid_platform_data; |
| 71 | + |
| 72 | +extern void n8x0_mipid_init(void); |
| 73 | +extern void n8x0_blizzard_init(void); |
| 74 | + |
| 75 | #define TUSB6010_ASYNC_CS 1 |
| 76 | #define TUSB6010_SYNC_CS 4 |
| 77 | #define TUSB6010_GPIO_INT 58 |
| 78 | @@ -145,12 +206,29 @@ static struct omap2_mcspi_device_config |
| 79 | |
| 80 | static struct spi_board_info n800_spi_board_info[] __initdata = { |
| 81 | { |
| 82 | + .modalias = "lcd_mipid", |
| 83 | + .bus_num = 1, |
| 84 | + .chip_select = 1, |
| 85 | + .max_speed_hz = 4000000, |
| 86 | + .controller_data= &mipid_mcspi_config, |
| 87 | + .platform_data = &n8x0_mipid_platform_data, |
| 88 | + }, |
| 89 | + { |
| 90 | .modalias = "p54spi", |
| 91 | .bus_num = 2, |
| 92 | .chip_select = 0, |
| 93 | .max_speed_hz = 48000000, |
| 94 | .controller_data = &p54spi_mcspi_config, |
| 95 | }, |
| 96 | + { |
| 97 | + .modalias = "tsc2005", |
| 98 | + .bus_num = 1, |
| 99 | + .chip_select = 0, |
| 100 | + .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO), |
| 101 | + .max_speed_hz = 6000000, |
| 102 | + .controller_data = &tsc2005_mcspi_config, |
| 103 | + .platform_data = &tsc2005_config, |
| 104 | + }, |
| 105 | }; |
| 106 | |
| 107 | #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ |
| 108 | @@ -789,6 +867,7 @@ static void __init n8x0_init_machine(voi |
| 109 | n8x0_cbus_init(); |
| 110 | |
| 111 | /* FIXME: add n810 spi devices */ |
| 112 | + tsc2005_set_config(); |
| 113 | spi_register_board_info(n800_spi_board_info, |
| 114 | ARRAY_SIZE(n800_spi_board_info)); |
| 115 | omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, |
| 116 | @@ -798,6 +877,8 @@ static void __init n8x0_init_machine(voi |
| 117 | i2c_register_board_info(2, n810_i2c_board_info_2, |
| 118 | ARRAY_SIZE(n810_i2c_board_info_2)); |
| 119 | board_serial_init(); |
| 120 | + n8x0_mipid_init(); |
| 121 | + n8x0_blizzard_init(); |
| 122 | gpmc_onenand_init(board_onenand_data); |
| 123 | n8x0_mmc_init(); |
| 124 | n8x0_usb_init(); |
| 125 | --- /dev/null |
| 126 | +++ b/arch/arm/mach-omap2/board-n8x0-lcd.c |
| 127 | @@ -0,0 +1,231 @@ |
| 128 | +/* |
| 129 | + * linux/arch/arm/mach-omap2/board-n8x0.c |
| 130 | + * |
| 131 | + * Copyright (C) 2005-2009 Nokia Corporation |
| 132 | + * Author: Juha Yrjola <juha.yrjola@nokia.com> |
| 133 | + * |
| 134 | + * Modified from mach-omap2/board-generic.c |
| 135 | + * |
| 136 | + * This program is free software; you can redistribute it and/or modify |
| 137 | + * it under the terms of the GNU General Public License version 2 as |
| 138 | + * published by the Free Software Foundation. |
| 139 | + */ |
| 140 | + |
| 141 | +#include <linux/clk.h> |
| 142 | +#include <linux/delay.h> |
| 143 | +#include <linux/gpio.h> |
| 144 | +#include <linux/omapfb.h> |
| 145 | + |
| 146 | +#include <plat/lcd_mipid.h> |
| 147 | +#include <plat/blizzard.h> |
| 148 | + |
| 149 | +#include "../../../drivers/cbus/tahvo.h" |
| 150 | + |
| 151 | + |
| 152 | +struct tahvo_pwm_device { |
| 153 | + struct device *dev; |
| 154 | + int tahvo_7bit_backlight; |
| 155 | +}; |
| 156 | + |
| 157 | +static struct tahvo_pwm_device *tahvo_pwm; |
| 158 | + |
| 159 | +static unsigned int tahvo_pwm_get_backlight_level(struct tahvo_pwm_device *pd) |
| 160 | +{ |
| 161 | + unsigned int mask; |
| 162 | + |
| 163 | + if (pd->tahvo_7bit_backlight) |
| 164 | + mask = 0x7f; |
| 165 | + else |
| 166 | + mask = 0x0f; |
| 167 | + return tahvo_read_reg(pd->dev, TAHVO_REG_LEDPWMR) & mask; |
| 168 | +} |
| 169 | + |
| 170 | +static unsigned int tahvo_pwm_get_max_backlight_level(struct tahvo_pwm_device *pd) |
| 171 | +{ |
| 172 | + if (pd->tahvo_7bit_backlight) |
| 173 | + return 0x7f; |
| 174 | + return 0x0f; |
| 175 | +} |
| 176 | + |
| 177 | +static void tahvo_pwm_set_backlight_level(struct tahvo_pwm_device *pd, unsigned int level) |
| 178 | +{ |
| 179 | + unsigned int max_level; |
| 180 | + |
| 181 | + max_level = tahvo_pwm_get_max_backlight_level(pd); |
| 182 | + if (level > max_level) |
| 183 | + level = max_level; |
| 184 | + tahvo_write_reg(pd->dev, TAHVO_REG_LEDPWMR, level); |
| 185 | +} |
| 186 | + |
| 187 | +static int __init n8x0_tahvo_pwm_probe(struct platform_device *pdev) |
| 188 | +{ |
| 189 | + struct tahvo_pwm_device *pd; |
| 190 | + unsigned int rev, id; |
| 191 | + |
| 192 | + pd = kzalloc(sizeof(*pd), GFP_KERNEL); |
| 193 | + if (WARN_ON(!pd)) |
| 194 | + return -ENOMEM; |
| 195 | + pd->dev = &pdev->dev; |
| 196 | + |
| 197 | + rev = tahvo_read_reg(pd->dev, TAHVO_REG_ASICR); |
| 198 | + id = (rev >> 8) & 0xff; |
| 199 | + if (id == 0x03) { |
| 200 | + if ((rev & 0xff) >= 0x50) |
| 201 | + pd->tahvo_7bit_backlight = 1; |
| 202 | + } else if (id == 0x0b) |
| 203 | + pd->tahvo_7bit_backlight = 1; |
| 204 | + |
| 205 | + dev_set_drvdata(pd->dev, pd); |
| 206 | + tahvo_pwm = pd; |
| 207 | + |
| 208 | + return 0; |
| 209 | +} |
| 210 | + |
| 211 | +static struct platform_driver n8x0_tahvo_pwm_driver = { |
| 212 | + .driver = { |
| 213 | + .name = "tahvo-pwm", |
| 214 | + }, |
| 215 | +}; |
| 216 | + |
| 217 | +static int __init n8x0_tahvo_pwm_init(void) |
| 218 | +{ |
| 219 | + return platform_driver_probe(&n8x0_tahvo_pwm_driver, n8x0_tahvo_pwm_probe); |
| 220 | +} |
| 221 | +fs_initcall(n8x0_tahvo_pwm_init); |
| 222 | + |
| 223 | +static int n8x0_get_backlight_level(struct mipid_platform_data *pdata) |
| 224 | +{ |
| 225 | + return tahvo_pwm_get_backlight_level(tahvo_pwm); |
| 226 | +} |
| 227 | + |
| 228 | +static int n8x0_get_max_backlight_level(struct mipid_platform_data *pdata) |
| 229 | +{ |
| 230 | + return tahvo_pwm_get_max_backlight_level(tahvo_pwm); |
| 231 | +} |
| 232 | + |
| 233 | +static void n8x0_set_backlight_level(struct mipid_platform_data *pdata, int level) |
| 234 | +{ |
| 235 | + tahvo_pwm_set_backlight_level(tahvo_pwm, level); |
| 236 | +} |
| 237 | + |
| 238 | +#define N8X0_BLIZZARD_POWERDOWN_GPIO 15 |
| 239 | + |
| 240 | +// MIPID LCD Panel |
| 241 | + |
| 242 | +static void mipid_shutdown(struct mipid_platform_data *pdata) |
| 243 | +{ |
| 244 | + if (pdata->nreset_gpio != -1) { |
| 245 | + pr_info("shutdown LCD\n"); |
| 246 | + gpio_set_value(pdata->nreset_gpio, 0); |
| 247 | + msleep(120); |
| 248 | + } |
| 249 | +} |
| 250 | + |
| 251 | +struct mipid_platform_data n8x0_mipid_platform_data = { |
| 252 | + .shutdown = mipid_shutdown, |
| 253 | + .get_bklight_level = n8x0_get_backlight_level, |
| 254 | + .set_bklight_level = n8x0_set_backlight_level, |
| 255 | + .get_bklight_max = n8x0_get_max_backlight_level, |
| 256 | +}; |
| 257 | + |
| 258 | +void __init n8x0_mipid_init(void) |
| 259 | +{ |
| 260 | + const struct omap_lcd_config *conf; |
| 261 | + int err; |
| 262 | + |
| 263 | + conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config); |
| 264 | + if (conf != NULL) { |
| 265 | + n8x0_mipid_platform_data.nreset_gpio = conf->nreset_gpio; |
| 266 | + n8x0_mipid_platform_data.data_lines = conf->data_lines; |
| 267 | + if (conf->nreset_gpio != -1) { |
| 268 | + err = gpio_request(conf->nreset_gpio, "MIPID nreset"); |
| 269 | + if (err) { |
| 270 | + printk(KERN_ERR "N8x0 MIPID failed to request nreset GPIO %d\n", |
| 271 | + conf->nreset_gpio); |
| 272 | + } else { |
| 273 | + err = gpio_direction_output(conf->nreset_gpio, 1); |
| 274 | + if (err) { |
| 275 | + printk(KERN_ERR "N8x0 MIPID failed to set nreset GPIO %d\n", |
| 276 | + conf->nreset_gpio); |
| 277 | + } |
| 278 | + } |
| 279 | + } |
| 280 | + printk(KERN_INFO "N8x0 MIPID config loaded"); |
| 281 | + } |
| 282 | + else |
| 283 | + printk(KERN_INFO "N8x0 MIPID config not provided"); |
| 284 | +} |
| 285 | + |
| 286 | + |
| 287 | +// Epson Blizzard LCD Controller |
| 288 | + |
| 289 | +static struct { |
| 290 | + struct clk *sys_ck; |
| 291 | +} blizzard; |
| 292 | + |
| 293 | +static int blizzard_get_clocks(void) |
| 294 | +{ |
| 295 | + blizzard.sys_ck = clk_get(0, "osc_ck"); |
| 296 | + if (IS_ERR(blizzard.sys_ck)) { |
| 297 | + printk(KERN_ERR "can't get Blizzard clock\n"); |
| 298 | + return PTR_ERR(blizzard.sys_ck); |
| 299 | + } |
| 300 | + return 0; |
| 301 | +} |
| 302 | + |
| 303 | +static unsigned long blizzard_get_clock_rate(struct device *dev) |
| 304 | +{ |
| 305 | + return clk_get_rate(blizzard.sys_ck); |
| 306 | +} |
| 307 | + |
| 308 | +static void blizzard_enable_clocks(int enable) |
| 309 | +{ |
| 310 | + if (enable) |
| 311 | + clk_enable(blizzard.sys_ck); |
| 312 | + else |
| 313 | + clk_disable(blizzard.sys_ck); |
| 314 | +} |
| 315 | + |
| 316 | +static void blizzard_power_up(struct device *dev) |
| 317 | +{ |
| 318 | + /* Vcore to 1.475V */ |
| 319 | + tahvo_set_clear_reg_bits(tahvo_pwm->dev, 0x07, 0, 0xf); |
| 320 | + msleep(10); |
| 321 | + |
| 322 | + blizzard_enable_clocks(1); |
| 323 | + gpio_set_value(N8X0_BLIZZARD_POWERDOWN_GPIO, 1); |
| 324 | +} |
| 325 | + |
| 326 | +static void blizzard_power_down(struct device *dev) |
| 327 | +{ |
| 328 | + gpio_set_value(N8X0_BLIZZARD_POWERDOWN_GPIO, 0); |
| 329 | + blizzard_enable_clocks(0); |
| 330 | + |
| 331 | + /* Vcore to 1.005V */ |
| 332 | + tahvo_set_clear_reg_bits(tahvo_pwm->dev, 0x07, 0xf, 0); |
| 333 | +} |
| 334 | + |
| 335 | +static struct blizzard_platform_data n8x0_blizzard_data = { |
| 336 | + .power_up = blizzard_power_up, |
| 337 | + .power_down = blizzard_power_down, |
| 338 | + .get_clock_rate = blizzard_get_clock_rate, |
| 339 | + .te_connected = 1, |
| 340 | +}; |
| 341 | + |
| 342 | +void __init n8x0_blizzard_init(void) |
| 343 | +{ |
| 344 | + int r; |
| 345 | + |
| 346 | + r = gpio_request(N8X0_BLIZZARD_POWERDOWN_GPIO, "Blizzard pd"); |
| 347 | + if (r < 0) |
| 348 | + { |
| 349 | + printk(KERN_ERR "Can't get N8x0 Blizzard powerdown GPIO %d\n", N8X0_BLIZZARD_POWERDOWN_GPIO); |
| 350 | + return; |
| 351 | + } |
| 352 | + gpio_direction_output(N8X0_BLIZZARD_POWERDOWN_GPIO, 1); |
| 353 | + |
| 354 | + blizzard_get_clocks(); |
| 355 | + omapfb_set_ctrl_platform_data(&n8x0_blizzard_data); |
| 356 | + |
| 357 | + printk(KERN_INFO "N8x0 Blizzard initialized"); |
| 358 | +} |
| 359 | --- a/arch/arm/mach-omap2/Makefile |
| 360 | +++ b/arch/arm/mach-omap2/Makefile |
| 361 | @@ -209,6 +209,7 @@ obj-$(CONFIG_MACH_OMAP_3430SDP) += boar |
| 362 | hsmmc.o \ |
| 363 | board-flash.o |
| 364 | obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o |
| 365 | +obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0-lcd.o |
| 366 | obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \ |
| 367 | sdram-nokia.o \ |
| 368 | hsmmc.o |
| 369 | |
