Root/target/linux/xburst/patches-3.2/0002-Add-jz4740-udc-driver.patch

1From 537082e01849ca85227c5b462b8ac9aceb11b77a Mon Sep 17 00:00:00 2001
2From: Lars-Peter Clausen <lars@metafoo.de>
3Date: Sat, 24 Apr 2010 12:18:46 +0200
4Subject: [PATCH 02/28] Add jz4740 udc driver
5
6History:
7- driver by Ingenic
8- patch by Lars-Peter Clausen.
9- updated to 3.1 by Maarten ter Huurne
10---
11 drivers/usb/gadget/Kconfig | 8 +
12 drivers/usb/gadget/Makefile | 1 +
13 drivers/usb/gadget/gadget_chips.h | 3 +
14 drivers/usb/gadget/jz4740_udc.c | 2199 +++++++++++++++++++++++++++++++++++++
15 drivers/usb/gadget/jz4740_udc.h | 101 ++
16 5 files changed, 2312 insertions(+), 0 deletions(-)
17 create mode 100644 drivers/usb/gadget/jz4740_udc.c
18 create mode 100644 drivers/usb/gadget/jz4740_udc.h
19
20diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
21index 23a4473..89b7d28 100644
22--- a/drivers/usb/gadget/Kconfig
23+++ b/drivers/usb/gadget/Kconfig
24@@ -178,6 +178,14 @@ config USB_FUSB300
25     help
26        Faraday usb device controller FUSB300 driver
27 
28+config USB_JZ4740
29+ tristate "JZ4740 UDC"
30+ depends on MACH_JZ4740
31+ select USB_GADGET_DUALSPEED
32+ help
33+ Select this to support the Ingenic JZ4740 processor
34+ high speed USB device controller.
35+
36 config USB_OMAP
37     tristate "OMAP USB Device Controller"
38     depends on ARCH_OMAP
39diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
40index b54ac61..2d65f6e 100644
41--- a/drivers/usb/gadget/Makefile
42+++ b/drivers/usb/gadget/Makefile
43@@ -31,6 +31,7 @@ obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
44 mv_udc-y := mv_udc_core.o
45 obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
46 obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
47+obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
48 
49 #
50 # USB gadget drivers
51diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
52index a8855d0..99f1580 100644
53--- a/drivers/usb/gadget/gadget_chips.h
54+++ b/drivers/usb/gadget/gadget_chips.h
55@@ -36,6 +36,7 @@
56 #define gadget_is_fsl_usb2(g) (!strcmp("fsl-usb2-udc", (g)->name))
57 #define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name))
58 #define gadget_is_imx(g) (!strcmp("imx_udc", (g)->name))
59+#define gadget_is_jz4740(g) (!strcmp("ingenic_hsusb", (g)->name))
60 #define gadget_is_langwell(g) (!strcmp("langwell_udc", (g)->name))
61 #define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name))
62 #define gadget_is_musbhdrc(g) (!strcmp("musb-hdrc", (g)->name))
63@@ -118,6 +119,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
64         return 0x31;
65     else if (gadget_is_dwc3(gadget))
66         return 0x32;
67+ else if (gadget_is_jz4740(gadget))
68+ return 0x33;
69 
70     return -ENOENT;
71 }
72diff --git a/drivers/usb/gadget/jz4740_udc.c b/drivers/usb/gadget/jz4740_udc.c
73new file mode 100644
74index 0000000..8d36434
75--- /dev/null
76+++ b/drivers/usb/gadget/jz4740_udc.c
77@@ -0,0 +1,2199 @@
78+/*
79+ * linux/drivers/usb/gadget/jz4740_udc.c
80+ *
81+ * Ingenic JZ4740 on-chip high speed USB device controller
82+ *
83+ * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
84+ * Author: <jlwei@ingenic.cn>
85+ *
86+ * This program is free software; you can redistribute it and/or modify
87+ * it under the terms of the GNU General Public License as published by
88+ * the Free Software Foundation; either version 2 of the License, or
89+ * (at your option) any later version.
90+ */
91+
92+/*
93+ * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
94+ *
95+ * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
96+ * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
97+ */
98+
99+#include <linux/kernel.h>
100+#include <linux/module.h>
101+#include <linux/platform_device.h>
102+#include <linux/delay.h>
103+#include <linux/ioport.h>
104+#include <linux/slab.h>
105+#include <linux/errno.h>
106+#include <linux/init.h>
107+#include <linux/list.h>
108+#include <linux/interrupt.h>
109+#include <linux/proc_fs.h>
110+#include <linux/usb.h>
111+#include <linux/usb/gadget.h>
112+#include <linux/clk.h>
113+
114+#include <asm/byteorder.h>
115+#include <asm/io.h>
116+#include <asm/irq.h>
117+#include <asm/system.h>
118+#include <asm/mach-jz4740/clock.h>
119+
120+#include "jz4740_udc.h"
121+
122+#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
123+#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
124+#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
125+#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
126+#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
127+#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
128+#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
129+#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
130+#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
131+#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
132+#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
133+
134+#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
135+#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
136+#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
137+#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
138+
139+#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
140+#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
141+#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
142+#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
143+
144+#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
145+
146+#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
147+#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
148+
149+#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
150+#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
151+#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
152+#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
153+#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
154+#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
155+#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
156+
157+/* Power register bit masks */
158+#define USB_POWER_SUSPENDM 0x01
159+#define USB_POWER_RESUME 0x04
160+#define USB_POWER_HSMODE 0x10
161+#define USB_POWER_HSENAB 0x20
162+#define USB_POWER_SOFTCONN 0x40
163+
164+/* Interrupt register bit masks */
165+#define USB_INTR_SUSPEND 0x01
166+#define USB_INTR_RESUME 0x02
167+#define USB_INTR_RESET 0x04
168+
169+#define USB_INTR_EP0 0x0001
170+#define USB_INTR_INEP1 0x0002
171+#define USB_INTR_INEP2 0x0004
172+#define USB_INTR_OUTEP1 0x0002
173+
174+/* CSR0 bit masks */
175+#define USB_CSR0_OUTPKTRDY 0x01
176+#define USB_CSR0_INPKTRDY 0x02
177+#define USB_CSR0_SENTSTALL 0x04
178+#define USB_CSR0_DATAEND 0x08
179+#define USB_CSR0_SETUPEND 0x10
180+#define USB_CSR0_SENDSTALL 0x20
181+#define USB_CSR0_SVDOUTPKTRDY 0x40
182+#define USB_CSR0_SVDSETUPEND 0x80
183+
184+/* Endpoint CSR register bits */
185+#define USB_INCSRH_AUTOSET 0x80
186+#define USB_INCSRH_ISO 0x40
187+#define USB_INCSRH_MODE 0x20
188+#define USB_INCSRH_DMAREQENAB 0x10
189+#define USB_INCSRH_DMAREQMODE 0x04
190+#define USB_INCSR_CDT 0x40
191+#define USB_INCSR_SENTSTALL 0x20
192+#define USB_INCSR_SENDSTALL 0x10
193+#define USB_INCSR_FF 0x08
194+#define USB_INCSR_UNDERRUN 0x04
195+#define USB_INCSR_FFNOTEMPT 0x02
196+#define USB_INCSR_INPKTRDY 0x01
197+
198+#define USB_OUTCSRH_AUTOCLR 0x80
199+#define USB_OUTCSRH_ISO 0x40
200+#define USB_OUTCSRH_DMAREQENAB 0x20
201+#define USB_OUTCSRH_DNYT 0x10
202+#define USB_OUTCSRH_DMAREQMODE 0x08
203+#define USB_OUTCSR_CDT 0x80
204+#define USB_OUTCSR_SENTSTALL 0x40
205+#define USB_OUTCSR_SENDSTALL 0x20
206+#define USB_OUTCSR_FF 0x10
207+#define USB_OUTCSR_DATAERR 0x08
208+#define USB_OUTCSR_OVERRUN 0x04
209+#define USB_OUTCSR_FFFULL 0x02
210+#define USB_OUTCSR_OUTPKTRDY 0x01
211+
212+/* DMA control bits */
213+#define USB_CNTL_ENA 0x01
214+#define USB_CNTL_DIR_IN 0x02
215+#define USB_CNTL_MODE_1 0x04
216+#define USB_CNTL_INTR_EN 0x08
217+#define USB_CNTL_EP(n) ((n) << 4)
218+#define USB_CNTL_BURST_0 (0 << 9)
219+#define USB_CNTL_BURST_4 (1 << 9)
220+#define USB_CNTL_BURST_8 (2 << 9)
221+#define USB_CNTL_BURST_16 (3 << 9)
222+
223+
224+#ifndef DEBUG
225+# define DEBUG(fmt,args...) do {} while(0)
226+#endif
227+#ifndef DEBUG_EP0
228+# define NO_STATES
229+# define DEBUG_EP0(fmt,args...) do {} while(0)
230+#endif
231+#ifndef DEBUG_SETUP
232+# define DEBUG_SETUP(fmt,args...) do {} while(0)
233+#endif
234+
235+static struct jz4740_udc jz4740_udc_controller;
236+
237+/*
238+ * Local declarations.
239+ */
240+static int jz4740_udc_start(struct usb_gadget_driver *driver,
241+ int (*bind)(struct usb_gadget *));
242+static int jz4740_udc_stop(struct usb_gadget_driver *driver);
243+static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
244+static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
245+
246+static void done(struct jz4740_ep *ep, struct jz4740_request *req,
247+ int status);
248+static void pio_irq_enable(struct jz4740_ep *ep);
249+static void pio_irq_disable(struct jz4740_ep *ep);
250+static void stop_activity(struct jz4740_udc *dev,
251+ struct usb_gadget_driver *driver);
252+static void nuke(struct jz4740_ep *ep, int status);
253+static void flush(struct jz4740_ep *ep);
254+static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
255+
256+/*-------------------------------------------------------------------------*/
257+
258+/* inline functions of register read/write/set/clear */
259+
260+static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
261+{
262+ return readb(udc->base + reg);
263+}
264+
265+static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
266+{
267+ return readw(udc->base + reg);
268+}
269+
270+static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
271+{
272+ return readl(udc->base + reg);
273+}
274+
275+static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
276+{
277+ writeb(val, udc->base + reg);
278+}
279+
280+static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
281+{
282+ writew(val, udc->base + reg);
283+}
284+
285+static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
286+{
287+ writel(val, udc->base + reg);
288+}
289+
290+static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
291+{
292+ usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
293+}
294+
295+static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
296+{
297+ usb_writew(udc, reg, usb_readw(udc, reg) | mask);
298+}
299+
300+static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
301+{
302+ usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
303+}
304+
305+static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
306+{
307+ usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
308+}
309+
310+/*-------------------------------------------------------------------------*/
311+
312+static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
313+{
314+ usb_writeb(udc, JZ_REG_UDC_INDEX, index);
315+}
316+
317+static inline void jz_udc_select_ep(struct jz4740_ep *ep)
318+{
319+ jz_udc_set_index(ep->dev, ep_index(ep));
320+}
321+
322+static inline int write_packet(struct jz4740_ep *ep,
323+ struct jz4740_request *req, unsigned int count)
324+{
325+ uint8_t *buf;
326+ unsigned int length;
327+ void __iomem *fifo = ep->dev->base + ep->fifo;
328+
329+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
330+
331+ buf = req->req.buf + req->req.actual;
332+
333+ length = req->req.length - req->req.actual;
334+ if (length > count)
335+ length = count;
336+ req->req.actual += length;
337+
338+ DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
339+
340+ writesl(fifo, buf, length >> 2);
341+ writesb(fifo, &buf[length - (length & 3)], length & 3);
342+
343+ return length;
344+}
345+
346+static int read_packet(struct jz4740_ep *ep,
347+ struct jz4740_request *req, unsigned int count)
348+{
349+ uint8_t *buf;
350+ unsigned int length;
351+ void __iomem *fifo = ep->dev->base + ep->fifo;
352+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
353+
354+ buf = req->req.buf + req->req.actual;
355+
356+ length = req->req.length - req->req.actual;
357+ if (length > count)
358+ length = count;
359+ req->req.actual += length;
360+
361+ DEBUG("Read %d, fifo %x\n", length, ep->fifo);
362+
363+ readsl(fifo, buf, length >> 2);
364+ readsb(fifo, &buf[length - (length & 3)], length & 3);
365+
366+ return length;
367+}
368+
369+/*-------------------------------------------------------------------------*/
370+
371+/*
372+ * udc_disable - disable USB device controller
373+ */
374+static void udc_disable(struct jz4740_udc *dev)
375+{
376+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
377+
378+ udc_set_address(dev, 0);
379+
380+ /* Disable interrupts */
381+ usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
382+ usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
383+ usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
384+
385+ /* Disable DMA */
386+ usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
387+ usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
388+
389+ /* Disconnect from usb */
390+ usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
391+
392+ /* Disable the USB PHY */
393+ clk_disable(dev->clk);
394+
395+ dev->ep0state = WAIT_FOR_SETUP;
396+ dev->gadget.speed = USB_SPEED_UNKNOWN;
397+
398+ return;
399+}
400+
401+/*
402+ * udc_reinit - initialize software state
403+ */
404+static void udc_reinit(struct jz4740_udc *dev)
405+{
406+ int i;
407+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
408+
409+ /* device/ep0 records init */
410+ INIT_LIST_HEAD(&dev->gadget.ep_list);
411+ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
412+ dev->ep0state = WAIT_FOR_SETUP;
413+
414+ for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
415+ struct jz4740_ep *ep = &dev->ep[i];
416+
417+ if (i != 0)
418+ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
419+
420+ INIT_LIST_HEAD(&ep->queue);
421+ ep->desc = 0;
422+ ep->stopped = 0;
423+ }
424+}
425+
426+/* until it's enabled, this UDC should be completely invisible
427+ * to any USB host.
428+ */
429+static void udc_enable(struct jz4740_udc *dev)
430+{
431+ int i;
432+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
433+
434+ /* UDC state is incorrect - Added by River */
435+ if (dev->state != UDC_STATE_ENABLE) {
436+ return;
437+ }
438+
439+ dev->gadget.speed = USB_SPEED_UNKNOWN;
440+
441+ /* Flush FIFO for each */
442+ for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
443+ struct jz4740_ep *ep = &dev->ep[i];
444+
445+ jz_udc_select_ep(ep);
446+ flush(ep);
447+ }
448+
449+ /* Set this bit to allow the UDC entering low-power mode when
450+ * there are no actions on the USB bus.
451+ * UDC still works during this bit was set.
452+ */
453+ jz4740_clock_udc_enable_auto_suspend();
454+
455+ /* Enable the USB PHY */
456+ clk_enable(dev->clk);
457+
458+ /* Disable interrupts */
459+/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
460+ usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
461+ usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
462+
463+ /* Enable interrupts */
464+ usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
465+ usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
466+ /* Don't enable rest of the interrupts */
467+ /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
468+ usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
469+
470+ /* Enable SUSPEND */
471+ /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
472+
473+ /* Enable HS Mode */
474+ usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
475+
476+ /* Let host detect UDC:
477+ * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
478+ * transistor on and pull the USBDP pin HIGH.
479+ */
480+ usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
481+
482+ return;
483+}
484+
485+/*-------------------------------------------------------------------------*/
486+
487+/* keeping it simple:
488+ * - one bus driver, initted first;
489+ * - one function driver, initted second
490+ */
491+
492+/*
493+ * Register entry point for the peripheral controller driver.
494+ */
495+
496+static int jz4740_udc_start(struct usb_gadget_driver *driver,
497+ int (*bind)(struct usb_gadget *))
498+{
499+ struct jz4740_udc *dev = &jz4740_udc_controller;
500+ int retval;
501+
502+ if (!driver || !bind)
503+ return -EINVAL;
504+
505+ if (!dev)
506+ return -ENODEV;
507+
508+ if (dev->driver)
509+ return -EBUSY;
510+
511+ /* hook up the driver */
512+ dev->driver = driver;
513+ dev->gadget.dev.driver = &driver->driver;
514+
515+ retval = bind(&dev->gadget);
516+ if (retval) {
517+ DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
518+ driver->driver.name, retval);
519+ dev->driver = 0;
520+ return retval;
521+ }
522+
523+ /* then enable host detection and ep0; and we're ready
524+ * for set_configuration as well as eventual disconnect.
525+ */
526+ udc_enable(dev);
527+
528+ DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
529+ driver->driver.name);
530+
531+ return 0;
532+}
533+
534+static void stop_activity(struct jz4740_udc *dev,
535+ struct usb_gadget_driver *driver)
536+{
537+ int i;
538+
539+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
540+
541+ /* don't disconnect drivers more than once */
542+ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
543+ driver = 0;
544+ dev->gadget.speed = USB_SPEED_UNKNOWN;
545+
546+ /* prevent new request submissions, kill any outstanding requests */
547+ for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
548+ struct jz4740_ep *ep = &dev->ep[i];
549+
550+ ep->stopped = 1;
551+
552+ jz_udc_select_ep(ep);
553+ nuke(ep, -ESHUTDOWN);
554+ }
555+
556+ /* report disconnect; the driver is already quiesced */
557+ if (driver) {
558+ spin_unlock(&dev->lock);
559+ driver->disconnect(&dev->gadget);
560+ spin_lock(&dev->lock);
561+ }
562+
563+ /* re-init driver-visible data structures */
564+ udc_reinit(dev);
565+}
566+
567+
568+/*
569+ * Unregister entry point for the peripheral controller driver.
570+ */
571+static int jz4740_udc_stop(struct usb_gadget_driver *driver)
572+{
573+ struct jz4740_udc *dev = &jz4740_udc_controller;
574+ unsigned long flags;
575+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
576+
577+ if (!dev)
578+ return -ENODEV;
579+ if (!driver || driver != dev->driver)
580+ return -EINVAL;
581+ if (!driver->unbind)
582+ return -EBUSY;
583+
584+ spin_lock_irqsave(&dev->lock, flags);
585+ dev->driver = 0;
586+ stop_activity(dev, driver);
587+ spin_unlock_irqrestore(&dev->lock, flags);
588+
589+ driver->unbind(&dev->gadget);
590+
591+ udc_disable(dev);
592+
593+ DEBUG("unregistered driver '%s'\n", driver->driver.name);
594+
595+ return 0;
596+}
597+
598+/*-------------------------------------------------------------------------*/
599+
600+/** Write request to FIFO (max write == maxp size)
601+ * Return: 0 = still running, 1 = completed, negative = errno
602+ * NOTE: INDEX register must be set for EP
603+ */
604+static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
605+{
606+ struct jz4740_udc *dev = ep->dev;
607+ uint32_t max, csr;
608+
609+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
610+ max = le16_to_cpu(ep->desc->wMaxPacketSize);
611+
612+ csr = usb_readb(dev, ep->csr);
613+
614+ if (!(csr & USB_INCSR_FFNOTEMPT)) {
615+ unsigned count;
616+ int is_last, is_short;
617+
618+ count = write_packet(ep, req, max);
619+ usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
620+
621+ /* last packet is usually short (or a zlp) */
622+ if (unlikely(count != max))
623+ is_last = is_short = 1;
624+ else {
625+ if (likely(req->req.length != req->req.actual)
626+ || req->req.zero)
627+ is_last = 0;
628+ else
629+ is_last = 1;
630+ /* interrupt/iso maxpacket may not fill the fifo */
631+ is_short = unlikely(max < ep_maxpacket(ep));
632+ }
633+
634+ DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
635+ ep->ep.name, count,
636+ is_last ? "/L" : "", is_short ? "/S" : "",
637+ req->req.length - req->req.actual, req);
638+
639+ /* requests complete when all IN data is in the FIFO */
640+ if (is_last) {
641+ done(ep, req, 0);
642+ if (list_empty(&ep->queue)) {
643+ pio_irq_disable(ep);
644+ }
645+ return 1;
646+ }
647+ } else {
648+ DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
649+ }
650+
651+ return 0;
652+}
653+
654+/** Read to request from FIFO (max read == bytes in fifo)
655+ * Return: 0 = still running, 1 = completed, negative = errno
656+ * NOTE: INDEX register must be set for EP
657+ */
658+static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
659+{
660+ struct jz4740_udc *dev = ep->dev;
661+ uint32_t csr;
662+ unsigned count, is_short;
663+
664+ /* make sure there's a packet in the FIFO. */
665+ csr = usb_readb(dev, ep->csr);
666+ if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
667+ DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
668+ return -EINVAL;
669+ }
670+
671+ /* read all bytes from this packet */
672+ count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
673+
674+ is_short = (count < ep->ep.maxpacket);
675+
676+ count = read_packet(ep, req, count);
677+
678+ DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
679+ ep->ep.name, csr, count,
680+ is_short ? "/S" : "", req, req->req.actual, req->req.length);
681+
682+ /* Clear OutPktRdy */
683+ usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
684+
685+ /* completion */
686+ if (is_short || req->req.actual == req->req.length) {
687+ done(ep, req, 0);
688+
689+ if (list_empty(&ep->queue))
690+ pio_irq_disable(ep);
691+ return 1;
692+ }
693+
694+ /* finished that packet. the next one may be waiting... */
695+ return 0;
696+}
697+
698+/*
699+ * done - retire a request; caller blocked irqs
700+ * INDEX register is preserved to keep same
701+ */
702+static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
703+{
704+ unsigned int stopped = ep->stopped;
705+ uint32_t index;
706+
707+ DEBUG("%s, %p\n", __FUNCTION__, ep);
708+ list_del_init(&req->queue);
709+
710+ if (likely(req->req.status == -EINPROGRESS))
711+ req->req.status = status;
712+ else
713+ status = req->req.status;
714+
715+ if (status && status != -ESHUTDOWN)
716+ DEBUG("complete %s req %p stat %d len %u/%u\n",
717+ ep->ep.name, &req->req, status,
718+ req->req.actual, req->req.length);
719+
720+ /* don't modify queue heads during completion callback */
721+ ep->stopped = 1;
722+ /* Read current index (completion may modify it) */
723+ index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
724+ spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
725+
726+ req->req.complete(&ep->ep, &req->req);
727+
728+ spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
729+ /* Restore index */
730+ jz_udc_set_index(ep->dev, index);
731+ ep->stopped = stopped;
732+}
733+
734+static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep)
735+{
736+ if (ep_is_in(ep))
737+ return JZ_REG_UDC_INTRINE;
738+ else
739+ return JZ_REG_UDC_INTROUTE;
740+}
741+
742+/** Enable EP interrupt */
743+static void pio_irq_enable(struct jz4740_ep *ep)
744+{
745+ DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
746+
747+ usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
748+}
749+
750+/** Disable EP interrupt */
751+static void pio_irq_disable(struct jz4740_ep *ep)
752+{
753+ DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
754+
755+ usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
756+}
757+
758+/*
759+ * nuke - dequeue ALL requests
760+ */
761+static void nuke(struct jz4740_ep *ep, int status)
762+{
763+ struct jz4740_request *req;
764+
765+ DEBUG("%s, %p\n", __FUNCTION__, ep);
766+
767+ /* Flush FIFO */
768+ flush(ep);
769+
770+ /* called with irqs blocked */
771+ while (!list_empty(&ep->queue)) {
772+ req = list_entry(ep->queue.next, struct jz4740_request, queue);
773+ done(ep, req, status);
774+ }
775+
776+ /* Disable IRQ if EP is enabled (has descriptor) */
777+ if (ep->desc)
778+ pio_irq_disable(ep);
779+}
780+
781+/** Flush EP FIFO
782+ * NOTE: INDEX register must be set before this call
783+ */
784+static void flush(struct jz4740_ep *ep)
785+{
786+ DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
787+
788+ switch (ep->type) {
789+ case ep_bulk_in:
790+ case ep_interrupt:
791+ usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
792+ break;
793+ case ep_bulk_out:
794+ usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
795+ break;
796+ case ep_control:
797+ break;
798+ }
799+}
800+
801+/**
802+ * jz4740_in_epn - handle IN interrupt
803+ */
804+static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
805+{
806+ uint32_t csr;
807+ struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
808+ struct jz4740_request *req;
809+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
810+
811+ jz_udc_select_ep(ep);
812+
813+ csr = usb_readb(dev, ep->csr);
814+ DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
815+
816+ if (csr & USB_INCSR_SENTSTALL) {
817+ DEBUG("USB_INCSR_SENTSTALL\n");
818+ usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
819+ return;
820+ }
821+
822+ if (!ep->desc) {
823+ DEBUG("%s: NO EP DESC\n", __FUNCTION__);
824+ return;
825+ }
826+
827+ if (!list_empty(&ep->queue)) {
828+ req = list_first_entry(&ep->queue, struct jz4740_request, queue);
829+ write_fifo(ep, req);
830+ }
831+}
832+
833+/*
834+ * Bulk OUT (recv)
835+ */
836+static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
837+{
838+ struct jz4740_ep *ep = &dev->ep[ep_idx];
839+ struct jz4740_request *req;
840+
841+ DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
842+
843+ jz_udc_select_ep(ep);
844+ if (ep->desc) {
845+ uint32_t csr;
846+
847+ while ((csr = usb_readb(dev, ep->csr)) &
848+ (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
849+ DEBUG("%s: %x\n", __FUNCTION__, csr);
850+
851+ if (csr & USB_OUTCSR_SENTSTALL) {
852+ DEBUG("%s: stall sent, flush fifo\n",
853+ __FUNCTION__);
854+ /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
855+ flush(ep);
856+ } else if (csr & USB_OUTCSR_OUTPKTRDY) {
857+ if (list_empty(&ep->queue))
858+ req = 0;
859+ else
860+ req =
861+ list_entry(ep->queue.next,
862+ struct jz4740_request,
863+ queue);
864+
865+ if (!req) {
866+ DEBUG("%s: NULL REQ %d\n",
867+ __FUNCTION__, ep_idx);
868+ break;
869+ } else {
870+ read_fifo(ep, req);
871+ }
872+ }
873+ }
874+ } else {
875+ /* Throw packet away.. */
876+ DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
877+ flush(ep);
878+ }
879+}
880+
881+/** Halt specific EP
882+ * Return 0 if success
883+ * NOTE: Sets INDEX register to EP !
884+ */
885+static int jz4740_set_halt(struct usb_ep *_ep, int value)
886+{
887+ struct jz4740_udc *dev;
888+ struct jz4740_ep *ep;
889+ unsigned long flags;
890+
891+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
892+
893+ ep = container_of(_ep, struct jz4740_ep, ep);
894+ if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
895+ DEBUG("%s, bad ep\n", __FUNCTION__);
896+ return -EINVAL;
897+ }
898+
899+ dev = ep->dev;
900+
901+ spin_lock_irqsave(&dev->lock, flags);
902+
903+ jz_udc_select_ep(ep);
904+
905+ DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
906+
907+ if (ep_index(ep) == 0) {
908+ /* EP0 */
909+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
910+ } else if (ep_is_in(ep)) {
911+ uint32_t csr = usb_readb(dev, ep->csr);
912+ if (value && ((csr & USB_INCSR_FFNOTEMPT)
913+ || !list_empty(&ep->queue))) {
914+ /*
915+ * Attempts to halt IN endpoints will fail (returning -EAGAIN)
916+ * if any transfer requests are still queued, or if the controller
917+ * FIFO still holds bytes that the host hasnÂ’t collected.
918+ */
919+ spin_unlock_irqrestore(&dev->lock, flags);
920+ DEBUG
921+ ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
922+ (csr & USB_INCSR_FFNOTEMPT),
923+ !list_empty(&ep->queue));
924+ return -EAGAIN;
925+ }
926+ flush(ep);
927+ if (value) {
928+ usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
929+ } else {
930+ usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
931+ usb_setb(dev, ep->csr, USB_INCSR_CDT);
932+ }
933+ } else {
934+
935+ flush(ep);
936+ if (value) {
937+ usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
938+ } else {
939+ usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
940+ usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
941+ }
942+ }
943+
944+ ep->stopped = value;
945+
946+ spin_unlock_irqrestore(&dev->lock, flags);
947+
948+ DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
949+
950+ return 0;
951+}
952+
953+
954+static int jz4740_ep_enable(struct usb_ep *_ep,
955+ const struct usb_endpoint_descriptor *desc)
956+{
957+ struct jz4740_ep *ep;
958+ struct jz4740_udc *dev;
959+ unsigned long flags;
960+ uint32_t max, csrh = 0;
961+
962+ DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
963+
964+ if (!_ep || !desc)
965+ return -EINVAL;
966+
967+ ep = container_of(_ep, struct jz4740_ep, ep);
968+ if (ep->desc || ep->type == ep_control
969+ || desc->bDescriptorType != USB_DT_ENDPOINT
970+ || ep->bEndpointAddress != desc->bEndpointAddress) {
971+ DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
972+ return -EINVAL;
973+ }
974+
975+ /* xfer types must match, except that interrupt ~= bulk */
976+ if (ep->bmAttributes != desc->bmAttributes
977+ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
978+ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
979+ DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
980+ return -EINVAL;
981+ }
982+
983+ dev = ep->dev;
984+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
985+ DEBUG("%s, bogus device state\n", __FUNCTION__);
986+ return -ESHUTDOWN;
987+ }
988+
989+ max = le16_to_cpu(desc->wMaxPacketSize);
990+
991+ spin_lock_irqsave(&ep->dev->lock, flags);
992+
993+ /* Configure the endpoint */
994+ jz_udc_select_ep(ep);
995+ if (ep_is_in(ep)) {
996+ usb_writew(dev, JZ_REG_UDC_INMAXP, max);
997+ switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
998+ case USB_ENDPOINT_XFER_BULK:
999+ case USB_ENDPOINT_XFER_INT:
1000+ csrh &= ~USB_INCSRH_ISO;
1001+ break;
1002+ case USB_ENDPOINT_XFER_ISOC:
1003+ csrh |= USB_INCSRH_ISO;
1004+ break;
1005+ }
1006+ usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1007+ }
1008+ else {
1009+ usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1010+ switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1011+ case USB_ENDPOINT_XFER_BULK:
1012+ csrh &= ~USB_OUTCSRH_ISO;
1013+ break;
1014+ case USB_ENDPOINT_XFER_INT:
1015+ csrh &= ~USB_OUTCSRH_ISO;
1016+ csrh |= USB_OUTCSRH_DNYT;
1017+ break;
1018+ case USB_ENDPOINT_XFER_ISOC:
1019+ csrh |= USB_OUTCSRH_ISO;
1020+ break;
1021+ }
1022+ usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1023+ }
1024+
1025+
1026+ ep->stopped = 0;
1027+ ep->desc = desc;
1028+ ep->ep.maxpacket = max;
1029+
1030+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1031+
1032+ /* Reset halt state (does flush) */
1033+ jz4740_set_halt(_ep, 0);
1034+
1035+ DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1036+
1037+ return 0;
1038+}
1039+
1040+/** Disable EP
1041+ * NOTE: Sets INDEX register
1042+ */
1043+static int jz4740_ep_disable(struct usb_ep *_ep)
1044+{
1045+ struct jz4740_ep *ep;
1046+ unsigned long flags;
1047+
1048+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
1049+
1050+ ep = container_of(_ep, struct jz4740_ep, ep);
1051+ if (!_ep || !ep->desc) {
1052+ DEBUG("%s, %s not enabled\n", __FUNCTION__,
1053+ _ep ? ep->ep.name : NULL);
1054+ return -EINVAL;
1055+ }
1056+
1057+ spin_lock_irqsave(&ep->dev->lock, flags);
1058+
1059+ jz_udc_select_ep(ep);
1060+
1061+ /* Nuke all pending requests (does flush) */
1062+ nuke(ep, -ESHUTDOWN);
1063+
1064+ /* Disable ep IRQ */
1065+ pio_irq_disable(ep);
1066+
1067+ ep->desc = 0;
1068+ ep->stopped = 1;
1069+
1070+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1071+
1072+ DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1073+ return 0;
1074+}
1075+
1076+static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1077+{
1078+ struct jz4740_request *req;
1079+
1080+ req = kzalloc(sizeof(*req), gfp_flags);
1081+ if (!req)
1082+ return NULL;
1083+
1084+ INIT_LIST_HEAD(&req->queue);
1085+
1086+ return &req->req;
1087+}
1088+
1089+static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1090+{
1091+ struct jz4740_request *req;
1092+
1093+ req = container_of(_req, struct jz4740_request, req);
1094+ WARN_ON(!list_empty(&req->queue));
1095+
1096+ kfree(req);
1097+}
1098+
1099+/*--------------------------------------------------------------------*/
1100+
1101+/** Queue one request
1102+ * Kickstart transfer if needed
1103+ * NOTE: Sets INDEX register
1104+ */
1105+static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1106+ gfp_t gfp_flags)
1107+{
1108+ struct jz4740_request *req;
1109+ struct jz4740_ep *ep;
1110+ struct jz4740_udc *dev;
1111+
1112+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
1113+
1114+ req = container_of(_req, struct jz4740_request, req);
1115+ if (unlikely
1116+ (!_req || !_req->complete || !_req->buf
1117+ || !list_empty(&req->queue))) {
1118+ DEBUG("%s, bad params\n", __FUNCTION__);
1119+ return -EINVAL;
1120+ }
1121+
1122+ ep = container_of(_ep, struct jz4740_ep, ep);
1123+ if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1124+ DEBUG("%s, bad ep\n", __FUNCTION__);
1125+ return -EINVAL;
1126+ }
1127+
1128+ dev = ep->dev;
1129+ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1130+ DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1131+ return -ESHUTDOWN;
1132+ }
1133+
1134+ DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1135+ _req->buf);
1136+
1137+ spin_lock_irqsave(&dev->lock, dev->lock_flags);
1138+
1139+ _req->status = -EINPROGRESS;
1140+ _req->actual = 0;
1141+
1142+ /* kickstart this i/o queue? */
1143+ DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1144+ ep->stopped);
1145+ if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1146+ uint32_t csr;
1147+
1148+ if (unlikely(ep_index(ep) == 0)) {
1149+ /* EP0 */
1150+ list_add_tail(&req->queue, &ep->queue);
1151+ jz4740_ep0_kick(dev, ep);
1152+ req = 0;
1153+ }
1154+ else if (ep_is_in(ep)) {
1155+ /* EP1 & EP2 */
1156+ jz_udc_select_ep(ep);
1157+ csr = usb_readb(dev, ep->csr);
1158+ pio_irq_enable(ep);
1159+ if (!(csr & USB_INCSR_FFNOTEMPT)) {
1160+ if (write_fifo(ep, req) == 1)
1161+ req = 0;
1162+ }
1163+ } else {
1164+ /* EP1 */
1165+ jz_udc_select_ep(ep);
1166+ csr = usb_readb(dev, ep->csr);
1167+ pio_irq_enable(ep);
1168+ if (csr & USB_OUTCSR_OUTPKTRDY) {
1169+ if (read_fifo(ep, req) == 1)
1170+ req = 0;
1171+ }
1172+ }
1173+ }
1174+
1175+ /* pio or dma irq handler advances the queue. */
1176+ if (likely(req != 0))
1177+ list_add_tail(&req->queue, &ep->queue);
1178+
1179+ spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1180+
1181+ return 0;
1182+}
1183+
1184+/* dequeue JUST ONE request */
1185+static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1186+{
1187+ struct jz4740_ep *ep;
1188+ struct jz4740_request *req;
1189+ unsigned long flags;
1190+
1191+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
1192+
1193+ ep = container_of(_ep, struct jz4740_ep, ep);
1194+ if (!_ep || ep->type == ep_control)
1195+ return -EINVAL;
1196+
1197+ spin_lock_irqsave(&ep->dev->lock, flags);
1198+
1199+ /* make sure it's actually queued on this endpoint */
1200+ list_for_each_entry(req, &ep->queue, queue) {
1201+ if (&req->req == _req)
1202+ break;
1203+ }
1204+ if (&req->req != _req) {
1205+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1206+ return -EINVAL;
1207+ }
1208+ done(ep, req, -ECONNRESET);
1209+
1210+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1211+ return 0;
1212+}
1213+
1214+/** Return bytes in EP FIFO
1215+ * NOTE: Sets INDEX register to EP
1216+ */
1217+static int jz4740_fifo_status(struct usb_ep *_ep)
1218+{
1219+ uint32_t csr;
1220+ int count = 0;
1221+ struct jz4740_ep *ep;
1222+ unsigned long flags;
1223+
1224+ ep = container_of(_ep, struct jz4740_ep, ep);
1225+ if (!_ep) {
1226+ DEBUG("%s, bad ep\n", __FUNCTION__);
1227+ return -ENODEV;
1228+ }
1229+
1230+ DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1231+
1232+ /* LPD can't report unclaimed bytes from IN fifos */
1233+ if (ep_is_in(ep))
1234+ return -EOPNOTSUPP;
1235+
1236+ spin_lock_irqsave(&ep->dev->lock, flags);
1237+ jz_udc_select_ep(ep);
1238+
1239+ csr = usb_readb(ep->dev, ep->csr);
1240+ if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1241+ csr & 0x1) {
1242+ count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1243+ }
1244+
1245+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1246+
1247+ return count;
1248+}
1249+
1250+/** Flush EP FIFO
1251+ * NOTE: Sets INDEX register to EP
1252+ */
1253+static void jz4740_fifo_flush(struct usb_ep *_ep)
1254+{
1255+ struct jz4740_ep *ep;
1256+ unsigned long flags;
1257+
1258+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1259+
1260+ ep = container_of(_ep, struct jz4740_ep, ep);
1261+ if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1262+ DEBUG("%s, bad ep\n", __FUNCTION__);
1263+ return;
1264+ }
1265+
1266+ spin_lock_irqsave(&ep->dev->lock, flags);
1267+
1268+ jz_udc_select_ep(ep);
1269+ flush(ep);
1270+
1271+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1272+}
1273+
1274+/****************************************************************/
1275+/* End Point 0 related functions */
1276+/****************************************************************/
1277+
1278+/* return: 0 = still running, 1 = completed, negative = errno */
1279+static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1280+{
1281+ uint32_t max;
1282+ unsigned count;
1283+ int is_last;
1284+
1285+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1286+ max = ep_maxpacket(ep);
1287+
1288+ count = write_packet(ep, req, max);
1289+
1290+ /* last packet is usually short (or a zlp) */
1291+ if (unlikely(count != max))
1292+ is_last = 1;
1293+ else {
1294+ if (likely(req->req.length != req->req.actual) || req->req.zero)
1295+ is_last = 0;
1296+ else
1297+ is_last = 1;
1298+ }
1299+
1300+ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1301+ ep->ep.name, count,
1302+ is_last ? "/L" : "", req->req.length - req->req.actual, req);
1303+
1304+ /* requests complete when all IN data is in the FIFO */
1305+ if (is_last) {
1306+ done(ep, req, 0);
1307+ return 1;
1308+ }
1309+
1310+ return 0;
1311+}
1312+
1313+static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1314+ unsigned char *cp, int max)
1315+{
1316+ int bytes;
1317+ int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1318+
1319+ if (count > max)
1320+ count = max;
1321+ bytes = count;
1322+ while (count--)
1323+ *cp++ = usb_readb(ep->dev, ep->fifo);
1324+
1325+ return bytes;
1326+}
1327+
1328+static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1329+ unsigned char *cp, int count)
1330+{
1331+ DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1332+ while (count--)
1333+ usb_writeb(ep->dev, ep->fifo, *cp++);
1334+}
1335+
1336+static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1337+{
1338+ struct jz4740_udc *dev = ep->dev;
1339+ uint32_t csr;
1340+ uint8_t *buf;
1341+ unsigned bufferspace, count, is_short;
1342+
1343+ DEBUG_EP0("%s\n", __FUNCTION__);
1344+
1345+ csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1346+ if (!(csr & USB_CSR0_OUTPKTRDY))
1347+ return 0;
1348+
1349+ buf = req->req.buf + req->req.actual;
1350+ prefetchw(buf);
1351+ bufferspace = req->req.length - req->req.actual;
1352+
1353+ /* read all bytes from this packet */
1354+ if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1355+ count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1356+ req->req.actual += min(count, bufferspace);
1357+ } else /* zlp */
1358+ count = 0;
1359+
1360+ is_short = (count < ep->ep.maxpacket);
1361+ DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1362+ ep->ep.name, csr, count,
1363+ is_short ? "/S" : "", req, req->req.actual, req->req.length);
1364+
1365+ while (likely(count-- != 0)) {
1366+ uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1367+
1368+ if (unlikely(bufferspace == 0)) {
1369+ /* this happens when the driver's buffer
1370+ * is smaller than what the host sent.
1371+ * discard the extra data.
1372+ */
1373+ if (req->req.status != -EOVERFLOW)
1374+ DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1375+ count);
1376+ req->req.status = -EOVERFLOW;
1377+ } else {
1378+ *buf++ = byte;
1379+ bufferspace--;
1380+ }
1381+ }
1382+
1383+ /* completion */
1384+ if (is_short || req->req.actual == req->req.length) {
1385+ done(ep, req, 0);
1386+ return 1;
1387+ }
1388+
1389+ /* finished that packet. the next one may be waiting... */
1390+ return 0;
1391+}
1392+
1393+/**
1394+ * udc_set_address - set the USB address for this device
1395+ * @address:
1396+ *
1397+ * Called from control endpoint function after it decodes a set address setup packet.
1398+ */
1399+static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1400+{
1401+ DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1402+
1403+ usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1404+}
1405+
1406+/*
1407+ * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1408+ * - if error
1409+ * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1410+ * - else
1411+ * set USB_CSR0_SVDOUTPKTRDY bit
1412+ if last set USB_CSR0_DATAEND bit
1413+ */
1414+static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1415+{
1416+ struct jz4740_request *req;
1417+ struct jz4740_ep *ep = &dev->ep[0];
1418+ int ret;
1419+
1420+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1421+
1422+ if (list_empty(&ep->queue))
1423+ req = 0;
1424+ else
1425+ req = list_entry(ep->queue.next, struct jz4740_request, queue);
1426+
1427+ if (req) {
1428+ if (req->req.length == 0) {
1429+ DEBUG_EP0("ZERO LENGTH OUT!\n");
1430+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1431+ dev->ep0state = WAIT_FOR_SETUP;
1432+ return;
1433+ } else if (kickstart) {
1434+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1435+ return;
1436+ }
1437+ ret = read_fifo_ep0(ep, req);
1438+ if (ret) {
1439+ /* Done! */
1440+ DEBUG_EP0("%s: finished, waiting for status\n",
1441+ __FUNCTION__);
1442+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1443+ dev->ep0state = WAIT_FOR_SETUP;
1444+ } else {
1445+ /* Not done yet.. */
1446+ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1447+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1448+ }
1449+ } else {
1450+ DEBUG_EP0("NO REQ??!\n");
1451+ }
1452+}
1453+
1454+/*
1455+ * DATA_STATE_XMIT
1456+ */
1457+static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1458+{
1459+ struct jz4740_request *req;
1460+ struct jz4740_ep *ep = &dev->ep[0];
1461+ int ret, need_zlp = 0;
1462+
1463+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1464+
1465+ if (list_empty(&ep->queue))
1466+ req = 0;
1467+ else
1468+ req = list_entry(ep->queue.next, struct jz4740_request, queue);
1469+
1470+ if (!req) {
1471+ DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1472+ return 0;
1473+ }
1474+
1475+ if (req->req.length == 0) {
1476+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1477+ dev->ep0state = WAIT_FOR_SETUP;
1478+ return 1;
1479+ }
1480+
1481+ if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1482+ /* Next write will end with the packet size, */
1483+ /* so we need zero-length-packet */
1484+ need_zlp = 1;
1485+ }
1486+
1487+ ret = write_fifo_ep0(ep, req);
1488+
1489+ if (ret == 1 && !need_zlp) {
1490+ /* Last packet */
1491+ DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1492+
1493+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1494+ dev->ep0state = WAIT_FOR_SETUP;
1495+ } else {
1496+ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1497+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1498+ }
1499+
1500+ if (need_zlp) {
1501+ DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1502+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1503+ dev->ep0state = DATA_STATE_NEED_ZLP;
1504+ }
1505+
1506+ return 1;
1507+}
1508+
1509+static int jz4740_handle_get_status(struct jz4740_udc *dev,
1510+ struct usb_ctrlrequest *ctrl)
1511+{
1512+ struct jz4740_ep *ep0 = &dev->ep[0];
1513+ struct jz4740_ep *qep;
1514+ int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1515+ uint16_t val = 0;
1516+
1517+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1518+
1519+ if (reqtype == USB_RECIP_INTERFACE) {
1520+ /* This is not supported.
1521+ * And according to the USB spec, this one does nothing..
1522+ * Just return 0
1523+ */
1524+ DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1525+ } else if (reqtype == USB_RECIP_DEVICE) {
1526+ DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1527+ val |= (1 << 0); /* Self powered */
1528+ /*val |= (1<<1); *//* Remote wakeup */
1529+ } else if (reqtype == USB_RECIP_ENDPOINT) {
1530+ int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1531+
1532+ DEBUG_SETUP
1533+ ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1534+ ep_num, ctrl->wLength);
1535+
1536+ if (ctrl->wLength > 2 || ep_num > 3)
1537+ return -EOPNOTSUPP;
1538+
1539+ qep = &dev->ep[ep_num];
1540+ if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1541+ && ep_index(qep) != 0) {
1542+ return -EOPNOTSUPP;
1543+ }
1544+
1545+ jz_udc_select_ep(qep);
1546+
1547+ /* Return status on next IN token */
1548+ switch (qep->type) {
1549+ case ep_control:
1550+ val =
1551+ (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1552+ USB_CSR0_SENDSTALL;
1553+ break;
1554+ case ep_bulk_in:
1555+ case ep_interrupt:
1556+ val =
1557+ (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1558+ USB_INCSR_SENDSTALL;
1559+ break;
1560+ case ep_bulk_out:
1561+ val =
1562+ (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1563+ USB_OUTCSR_SENDSTALL;
1564+ break;
1565+ }
1566+
1567+ /* Back to EP0 index */
1568+ jz_udc_set_index(dev, 0);
1569+
1570+ DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1571+ ctrl->wIndex, val);
1572+ } else {
1573+ DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1574+ return -EOPNOTSUPP;
1575+ }
1576+
1577+ /* Clear "out packet ready" */
1578+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1579+ /* Put status to FIFO */
1580+ jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1581+ /* Issue "In packet ready" */
1582+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1583+
1584+ return 0;
1585+}
1586+
1587+/*
1588+ * WAIT_FOR_SETUP (OUTPKTRDY)
1589+ * - read data packet from EP0 FIFO
1590+ * - decode command
1591+ * - if error
1592+ * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1593+ * - else
1594+ * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1595+ */
1596+static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1597+{
1598+ struct jz4740_ep *ep = &dev->ep[0];
1599+ struct usb_ctrlrequest ctrl;
1600+ int i;
1601+
1602+ DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1603+
1604+ /* Nuke all previous transfers */
1605+ nuke(ep, -EPROTO);
1606+
1607+ /* read control req from fifo (8 bytes) */
1608+ jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1609+
1610+ DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1611+ ctrl.bRequestType, ctrl.bRequest,
1612+ ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1613+
1614+ /* Set direction of EP0 */
1615+ if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1616+ ep->bEndpointAddress |= USB_DIR_IN;
1617+ } else {
1618+ ep->bEndpointAddress &= ~USB_DIR_IN;
1619+ }
1620+
1621+ /* Handle some SETUP packets ourselves */
1622+ switch (ctrl.bRequest) {
1623+ case USB_REQ_SET_ADDRESS:
1624+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1625+ break;
1626+
1627+ DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1628+ udc_set_address(dev, ctrl.wValue);
1629+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1630+ return;
1631+
1632+ case USB_REQ_SET_CONFIGURATION:
1633+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1634+ break;
1635+
1636+ DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1637+/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1638+
1639+ /* Enable RESUME and SUSPEND interrupts */
1640+ usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1641+ break;
1642+
1643+ case USB_REQ_SET_INTERFACE:
1644+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1645+ break;
1646+
1647+ DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1648+/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1649+ break;
1650+
1651+ case USB_REQ_GET_STATUS:
1652+ if (jz4740_handle_get_status(dev, &ctrl) == 0)
1653+ return;
1654+
1655+ case USB_REQ_CLEAR_FEATURE:
1656+ case USB_REQ_SET_FEATURE:
1657+ if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1658+ struct jz4740_ep *qep;
1659+ int ep_num = (ctrl.wIndex & 0x0f);
1660+
1661+ /* Support only HALT feature */
1662+ if (ctrl.wValue != 0 || ctrl.wLength != 0
1663+ || ep_num > 3 || ep_num < 1)
1664+ break;
1665+
1666+ qep = &dev->ep[ep_num];
1667+ spin_unlock(&dev->lock);
1668+ if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1669+ DEBUG_SETUP("SET_FEATURE (%d)\n",
1670+ ep_num);
1671+ jz4740_set_halt(&qep->ep, 1);
1672+ } else {
1673+ DEBUG_SETUP("CLR_FEATURE (%d)\n",
1674+ ep_num);
1675+ jz4740_set_halt(&qep->ep, 0);
1676+ }
1677+ spin_lock(&dev->lock);
1678+
1679+ jz_udc_set_index(dev, 0);
1680+
1681+ /* Reply with a ZLP on next IN token */
1682+ usb_setb(dev, JZ_REG_UDC_CSR0,
1683+ (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1684+ return;
1685+ }
1686+ break;
1687+
1688+ default:
1689+ break;
1690+ }
1691+
1692+ /* gadget drivers see class/vendor specific requests,
1693+ * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1694+ * and more.
1695+ */
1696+ if (dev->driver) {
1697+ /* device-2-host (IN) or no data setup command, process immediately */
1698+ spin_unlock(&dev->lock);
1699+
1700+ i = dev->driver->setup(&dev->gadget, &ctrl);
1701+ spin_lock(&dev->lock);
1702+
1703+ if (unlikely(i < 0)) {
1704+ /* setup processing failed, force stall */
1705+ DEBUG_SETUP
1706+ (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1707+ i);
1708+ jz_udc_set_index(dev, 0);
1709+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1710+
1711+ /* ep->stopped = 1; */
1712+ dev->ep0state = WAIT_FOR_SETUP;
1713+ }
1714+ else {
1715+ DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1716+/* if (!ctrl.wLength) {
1717+ usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1718+ }*/
1719+ }
1720+ }
1721+}
1722+
1723+/*
1724+ * DATA_STATE_NEED_ZLP
1725+ */
1726+static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1727+{
1728+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1729+
1730+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1731+ dev->ep0state = WAIT_FOR_SETUP;
1732+}
1733+
1734+/*
1735+ * handle ep0 interrupt
1736+ */
1737+static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1738+{
1739+ struct jz4740_ep *ep = &dev->ep[0];
1740+ uint32_t csr;
1741+
1742+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1743+ /* Set index 0 */
1744+ jz_udc_set_index(dev, 0);
1745+ csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1746+
1747+ DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1748+
1749+ /*
1750+ * if SENT_STALL is set
1751+ * - clear the SENT_STALL bit
1752+ */
1753+ if (csr & USB_CSR0_SENTSTALL) {
1754+ DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1755+ usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1756+ nuke(ep, -ECONNABORTED);
1757+ dev->ep0state = WAIT_FOR_SETUP;
1758+ return;
1759+ }
1760+
1761+ /*
1762+ * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1763+ * - fill EP0 FIFO
1764+ * - if last packet
1765+ * - set IN_PKT_RDY | DATA_END
1766+ * - else
1767+ * set IN_PKT_RDY
1768+ */
1769+ if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1770+ DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1771+ __FUNCTION__);
1772+
1773+ switch (dev->ep0state) {
1774+ case DATA_STATE_XMIT:
1775+ DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1776+ jz4740_ep0_in(dev, csr);
1777+ return;
1778+ case DATA_STATE_NEED_ZLP:
1779+ DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1780+ jz4740_ep0_in_zlp(dev, csr);
1781+ return;
1782+ default:
1783+ /* Stall? */
1784+// DEBUG_EP0("Odd state!! state = %s\n",
1785+// state_names[dev->ep0state]);
1786+ dev->ep0state = WAIT_FOR_SETUP;
1787+ /* nuke(ep, 0); */
1788+ /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1789+// break;
1790+ return;
1791+ }
1792+ }
1793+
1794+ /*
1795+ * if SETUPEND is set
1796+ * - abort the last transfer
1797+ * - set SERVICED_SETUP_END_BIT
1798+ */
1799+ if (csr & USB_CSR0_SETUPEND) {
1800+ DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1801+
1802+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1803+ nuke(ep, 0);
1804+ dev->ep0state = WAIT_FOR_SETUP;
1805+ }
1806+
1807+ /*
1808+ * if USB_CSR0_OUTPKTRDY is set
1809+ * - read data packet from EP0 FIFO
1810+ * - decode command
1811+ * - if error
1812+ * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1813+ * - else
1814+ * set SVDOUTPKTRDY | DATAEND bits
1815+ */
1816+ if (csr & USB_CSR0_OUTPKTRDY) {
1817+
1818+ DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1819+ csr);
1820+
1821+ switch (dev->ep0state) {
1822+ case WAIT_FOR_SETUP:
1823+ DEBUG_EP0("WAIT_FOR_SETUP\n");
1824+ jz4740_ep0_setup(dev, csr);
1825+ break;
1826+
1827+ case DATA_STATE_RECV:
1828+ DEBUG_EP0("DATA_STATE_RECV\n");
1829+ jz4740_ep0_out(dev, csr, 0);
1830+ break;
1831+
1832+ default:
1833+ /* send stall? */
1834+ DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1835+ dev->ep0state);
1836+ break;
1837+ }
1838+ }
1839+}
1840+
1841+static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1842+{
1843+ uint32_t csr;
1844+
1845+ jz_udc_set_index(dev, 0);
1846+
1847+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1848+
1849+ /* Clear "out packet ready" */
1850+
1851+ if (ep_is_in(ep)) {
1852+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1853+ csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1854+ dev->ep0state = DATA_STATE_XMIT;
1855+ jz4740_ep0_in(dev, csr);
1856+ } else {
1857+ csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1858+ dev->ep0state = DATA_STATE_RECV;
1859+ jz4740_ep0_out(dev, csr, 1);
1860+ }
1861+}
1862+
1863+/** Handle USB RESET interrupt
1864+ */
1865+static void jz4740_reset_irq(struct jz4740_udc *dev)
1866+{
1867+ dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1868+ USB_SPEED_HIGH : USB_SPEED_FULL;
1869+
1870+ DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
1871+ (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1872+}
1873+
1874+/*
1875+ * jz4740 usb device interrupt handler.
1876+ */
1877+static irqreturn_t jz4740_udc_irq(int irq, void *devid)
1878+{
1879+ struct jz4740_udc *jz4740_udc = devid;
1880+ uint8_t index;
1881+
1882+ uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1883+ uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
1884+ uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
1885+ uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
1886+
1887+ if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1888+ return IRQ_HANDLED;
1889+
1890+
1891+ DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1892+ intr_out, intr_in, intr_usb);
1893+
1894+ spin_lock(&jz4740_udc->lock);
1895+ index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
1896+
1897+ /* Check for resume from suspend mode */
1898+ if ((intr_usb & USB_INTR_RESUME) &&
1899+ (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1900+ DEBUG("USB resume\n");
1901+ jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
1902+ }
1903+
1904+ /* Check for system interrupts */
1905+ if (intr_usb & USB_INTR_RESET) {
1906+ DEBUG("USB reset\n");
1907+ jz4740_reset_irq(jz4740_udc);
1908+ }
1909+
1910+ /* Check for endpoint 0 interrupt */
1911+ if (intr_in & USB_INTR_EP0) {
1912+ DEBUG("USB_INTR_EP0 (control)\n");
1913+ jz4740_handle_ep0(jz4740_udc, intr_in);
1914+ }
1915+
1916+ /* Check for Bulk-IN DMA interrupt */
1917+ if (intr_dma & 0x1) {
1918+ int ep_num;
1919+ struct jz4740_ep *ep;
1920+ ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
1921+ ep = &jz4740_udc->ep[ep_num + 1];
1922+ jz_udc_select_ep(ep);
1923+ usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
1924+/* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
1925+ }
1926+
1927+ /* Check for Bulk-OUT DMA interrupt */
1928+ if (intr_dma & 0x2) {
1929+ int ep_num;
1930+ ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
1931+ jz4740_out_epn(jz4740_udc, ep_num, intr_out);
1932+ }
1933+
1934+ /* Check for each configured endpoint interrupt */
1935+ if (intr_in & USB_INTR_INEP1) {
1936+ DEBUG("USB_INTR_INEP1\n");
1937+ jz4740_in_epn(jz4740_udc, 1, intr_in);
1938+ }
1939+
1940+ if (intr_in & USB_INTR_INEP2) {
1941+ DEBUG("USB_INTR_INEP2\n");
1942+ jz4740_in_epn(jz4740_udc, 2, intr_in);
1943+ }
1944+
1945+ if (intr_out & USB_INTR_OUTEP1) {
1946+ DEBUG("USB_INTR_OUTEP1\n");
1947+ jz4740_out_epn(jz4740_udc, 1, intr_out);
1948+ }
1949+
1950+ /* Check for suspend mode */
1951+ if ((intr_usb & USB_INTR_SUSPEND) &&
1952+ (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
1953+ DEBUG("USB suspend\n");
1954+ jz4740_udc->driver->suspend(&jz4740_udc->gadget);
1955+ /* Host unloaded from us, can do something, such as flushing
1956+ the NAND block cache etc. */
1957+ }
1958+
1959+ jz_udc_set_index(jz4740_udc, index);
1960+
1961+ spin_unlock(&jz4740_udc->lock);
1962+
1963+ return IRQ_HANDLED;
1964+}
1965+
1966+
1967+
1968+/*-------------------------------------------------------------------------*/
1969+
1970+
1971+static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
1972+{
1973+ return container_of(gadget, struct jz4740_udc, gadget);
1974+}
1975+
1976+static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
1977+{
1978+ DEBUG("%s, %p\n", __FUNCTION__, _gadget);
1979+ return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
1980+}
1981+
1982+static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
1983+{
1984+ /* host may not have enabled remote wakeup */
1985+ /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
1986+ return -EHOSTUNREACH;
1987+ udc_set_mask_UDCCR(UDCCR_RSM); */
1988+ return -ENOTSUPP;
1989+}
1990+
1991+static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
1992+{
1993+ struct jz4740_udc *udc = gadget_to_udc(_gadget);
1994+ unsigned long flags;
1995+
1996+ local_irq_save(flags);
1997+
1998+ if (on) {
1999+ udc->state = UDC_STATE_ENABLE;
2000+ udc_enable(udc);
2001+ } else {
2002+ udc->state = UDC_STATE_DISABLE;
2003+ udc_disable(udc);
2004+ }
2005+
2006+ local_irq_restore(flags);
2007+
2008+ return 0;
2009+}
2010+
2011+
2012+static const struct usb_gadget_ops jz4740_udc_ops = {
2013+ .get_frame = jz4740_udc_get_frame,
2014+ .wakeup = jz4740_udc_wakeup,
2015+ .pullup = jz4740_udc_pullup,
2016+ .start = jz4740_udc_start,
2017+ .stop = jz4740_udc_stop,
2018+};
2019+
2020+static struct usb_ep_ops jz4740_ep_ops = {
2021+ .enable = jz4740_ep_enable,
2022+ .disable = jz4740_ep_disable,
2023+
2024+ .alloc_request = jz4740_alloc_request,
2025+ .free_request = jz4740_free_request,
2026+
2027+ .queue = jz4740_queue,
2028+ .dequeue = jz4740_dequeue,
2029+
2030+ .set_halt = jz4740_set_halt,
2031+ .fifo_status = jz4740_fifo_status,
2032+ .fifo_flush = jz4740_fifo_flush,
2033+};
2034+
2035+
2036+/*-------------------------------------------------------------------------*/
2037+
2038+static struct jz4740_udc jz4740_udc_controller = {
2039+ .gadget = {
2040+ .ops = &jz4740_udc_ops,
2041+ .ep0 = &jz4740_udc_controller.ep[0].ep,
2042+ .name = "jz4740-udc",
2043+ .dev = {
2044+ .init_name = "gadget",
2045+ },
2046+ },
2047+
2048+ /* control endpoint */
2049+ .ep[0] = {
2050+ .ep = {
2051+ .name = "ep0",
2052+ .ops = &jz4740_ep_ops,
2053+ .maxpacket = EP0_MAXPACKETSIZE,
2054+ },
2055+ .dev = &jz4740_udc_controller,
2056+
2057+ .bEndpointAddress = 0,
2058+ .bmAttributes = 0,
2059+
2060+ .type = ep_control,
2061+ .fifo = JZ_REG_UDC_EP_FIFO(0),
2062+ .csr = JZ_REG_UDC_CSR0,
2063+ },
2064+
2065+ /* bulk out endpoint */
2066+ .ep[1] = {
2067+ .ep = {
2068+ .name = "ep1out-bulk",
2069+ .ops = &jz4740_ep_ops,
2070+ .maxpacket = EPBULK_MAXPACKETSIZE,
2071+ },
2072+ .dev = &jz4740_udc_controller,
2073+
2074+ .bEndpointAddress = 1,
2075+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
2076+
2077+ .type = ep_bulk_out,
2078+ .fifo = JZ_REG_UDC_EP_FIFO(1),
2079+ .csr = JZ_REG_UDC_OUTCSR,
2080+ },
2081+
2082+ /* bulk in endpoint */
2083+ .ep[2] = {
2084+ .ep = {
2085+ .name = "ep1in-bulk",
2086+ .ops = &jz4740_ep_ops,
2087+ .maxpacket = EPBULK_MAXPACKETSIZE,
2088+ },
2089+ .dev = &jz4740_udc_controller,
2090+
2091+ .bEndpointAddress = 1 | USB_DIR_IN,
2092+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
2093+
2094+ .type = ep_bulk_in,
2095+ .fifo = JZ_REG_UDC_EP_FIFO(1),
2096+ .csr = JZ_REG_UDC_INCSR,
2097+ },
2098+
2099+ /* interrupt in endpoint */
2100+ .ep[3] = {
2101+ .ep = {
2102+ .name = "ep2in-int",
2103+ .ops = &jz4740_ep_ops,
2104+ .maxpacket = EPINTR_MAXPACKETSIZE,
2105+ },
2106+ .dev = &jz4740_udc_controller,
2107+
2108+ .bEndpointAddress = 2 | USB_DIR_IN,
2109+ .bmAttributes = USB_ENDPOINT_XFER_INT,
2110+
2111+ .type = ep_interrupt,
2112+ .fifo = JZ_REG_UDC_EP_FIFO(2),
2113+ .csr = JZ_REG_UDC_INCSR,
2114+ },
2115+};
2116+
2117+static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2118+{
2119+ struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2120+ int ret;
2121+
2122+ spin_lock_init(&jz4740_udc->lock);
2123+
2124+ jz4740_udc->dev = &pdev->dev;
2125+ jz4740_udc->gadget.dev.parent = &pdev->dev;
2126+ jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
2127+
2128+ ret = device_register(&jz4740_udc->gadget.dev);
2129+ if (ret)
2130+ return ret;
2131+
2132+ jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2133+ if (IS_ERR(jz4740_udc->clk)) {
2134+ ret = PTR_ERR(jz4740_udc->clk);
2135+ dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2136+ goto err_device_unregister;
2137+ }
2138+
2139+ platform_set_drvdata(pdev, jz4740_udc);
2140+
2141+ jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2142+
2143+ if (!jz4740_udc->mem) {
2144+ ret = -ENOENT;
2145+ dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2146+ goto err_clk_put;
2147+ }
2148+
2149+ jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2150+ resource_size(jz4740_udc->mem), pdev->name);
2151+
2152+ if (!jz4740_udc->mem) {
2153+ ret = -EBUSY;
2154+ dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2155+ goto err_device_unregister;
2156+ }
2157+
2158+ jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2159+
2160+ if (!jz4740_udc->base) {
2161+ ret = -EBUSY;
2162+ dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2163+ goto err_release_mem_region;
2164+ }
2165+
2166+ jz4740_udc->irq = platform_get_irq(pdev, 0);
2167+ ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2168+ jz4740_udc);
2169+ if (ret) {
2170+ dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2171+ goto err_iounmap;
2172+ }
2173+
2174+ ret = usb_add_gadget_udc(&pdev->dev, &jz4740_udc->gadget);
2175+ if (ret) {
2176+ dev_err(&pdev->dev, "Failed to add gadget: %d\n", ret);
2177+ goto err_free_irq;
2178+ }
2179+
2180+ udc_disable(jz4740_udc);
2181+ udc_reinit(jz4740_udc);
2182+
2183+ return 0;
2184+
2185+err_free_irq:
2186+ free_irq(jz4740_udc->irq, pdev);
2187+err_iounmap:
2188+ iounmap(jz4740_udc->base);
2189+err_release_mem_region:
2190+ release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2191+err_clk_put:
2192+ clk_put(jz4740_udc->clk);
2193+err_device_unregister:
2194+ device_unregister(&jz4740_udc->gadget.dev);
2195+ platform_set_drvdata(pdev, NULL);
2196+
2197+ return ret;
2198+}
2199+
2200+static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2201+{
2202+ struct jz4740_udc *dev = platform_get_drvdata(pdev);
2203+
2204+ usb_del_gadget_udc(&dev->gadget);
2205+ if (dev->driver)
2206+ return -EBUSY;
2207+
2208+ udc_disable(dev);
2209+
2210+ free_irq(dev->irq, dev);
2211+ iounmap(dev->base);
2212+ release_mem_region(dev->mem->start, resource_size(dev->mem));
2213+ clk_put(dev->clk);
2214+
2215+ platform_set_drvdata(pdev, NULL);
2216+ device_unregister(&dev->gadget.dev);
2217+
2218+ return 0;
2219+}
2220+
2221+#ifdef CONFIG_PM
2222+
2223+static int jz4740_udc_suspend(struct device *dev)
2224+{
2225+ struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2226+
2227+ if (jz4740_udc->state == UDC_STATE_ENABLE)
2228+ udc_disable(jz4740_udc);
2229+
2230+ return 0;
2231+}
2232+
2233+static int jz4740_udc_resume(struct device *dev)
2234+{
2235+ struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2236+
2237+ if (jz4740_udc->state == UDC_STATE_ENABLE)
2238+ udc_enable(jz4740_udc);
2239+
2240+ return 0;
2241+}
2242+
2243+static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume);
2244+#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2245+
2246+#else
2247+#define JZ4740_UDC_PM_OPS NULL
2248+#endif
2249+
2250+static struct platform_driver udc_driver = {
2251+ .probe = jz4740_udc_probe,
2252+ .remove = __devexit_p(jz4740_udc_remove),
2253+ .driver = {
2254+ .name = "jz-udc",
2255+ .owner = THIS_MODULE,
2256+ .pm = JZ4740_UDC_PM_OPS,
2257+ },
2258+};
2259+
2260+/*-------------------------------------------------------------------------*/
2261+
2262+static int __init udc_init (void)
2263+{
2264+ return platform_driver_register(&udc_driver);
2265+}
2266+module_init(udc_init);
2267+
2268+static void __exit udc_exit (void)
2269+{
2270+ platform_driver_unregister(&udc_driver);
2271+}
2272+module_exit(udc_exit);
2273+
2274+MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2275+MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2276+MODULE_LICENSE("GPL");
2277diff --git a/drivers/usb/gadget/jz4740_udc.h b/drivers/usb/gadget/jz4740_udc.h
2278new file mode 100644
2279index 0000000..53fd1da
2280--- /dev/null
2281+++ b/drivers/usb/gadget/jz4740_udc.h
2282@@ -0,0 +1,101 @@
2283+/*
2284+ * linux/drivers/usb/gadget/jz4740_udc.h
2285+ *
2286+ * Ingenic JZ4740 on-chip high speed USB device controller
2287+ *
2288+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
2289+ * Author: <jlwei@ingenic.cn>
2290+ *
2291+ * This program is free software; you can redistribute it and/or modify
2292+ * it under the terms of the GNU General Public License as published by
2293+ * the Free Software Foundation; either version 2 of the License, or
2294+ * (at your option) any later version.
2295+ */
2296+
2297+#ifndef __USB_GADGET_JZ4740_H__
2298+#define __USB_GADGET_JZ4740_H__
2299+
2300+/*-------------------------------------------------------------------------*/
2301+
2302+// Max packet size
2303+#define EP0_MAXPACKETSIZE 64
2304+#define EPBULK_MAXPACKETSIZE 512
2305+#define EPINTR_MAXPACKETSIZE 64
2306+
2307+#define UDC_MAX_ENDPOINTS 4
2308+
2309+/*-------------------------------------------------------------------------*/
2310+
2311+enum ep_type {
2312+ ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2313+};
2314+
2315+struct jz4740_ep {
2316+ struct usb_ep ep;
2317+ struct jz4740_udc *dev;
2318+
2319+ const struct usb_endpoint_descriptor *desc;
2320+
2321+ uint8_t stopped;
2322+ uint8_t bEndpointAddress;
2323+ uint8_t bmAttributes;
2324+
2325+ enum ep_type type;
2326+ size_t fifo;
2327+ uint32_t csr;
2328+
2329+ uint32_t reg_addr;
2330+ struct list_head queue;
2331+};
2332+
2333+struct jz4740_request {
2334+ struct usb_request req;
2335+ struct list_head queue;
2336+};
2337+
2338+enum ep0state {
2339+ WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2340+ DATA_STATE_XMIT, /* data tx stage */
2341+ DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2342+ WAIT_FOR_OUT_STATUS, /* status stages */
2343+ DATA_STATE_RECV, /* data rx stage */
2344+};
2345+
2346+/* For function binding with UDC Disable - Added by River */
2347+typedef enum {
2348+ UDC_STATE_ENABLE = 0,
2349+ UDC_STATE_DISABLE,
2350+}udc_state_t;
2351+
2352+struct jz4740_udc {
2353+ struct usb_gadget gadget;
2354+ struct usb_gadget_driver *driver;
2355+ struct device *dev;
2356+ spinlock_t lock;
2357+ unsigned long lock_flags;
2358+
2359+ enum ep0state ep0state;
2360+ struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2361+
2362+ udc_state_t state;
2363+
2364+ struct resource *mem;
2365+ void __iomem *base;
2366+ int irq;
2367+
2368+ struct clk *clk;
2369+};
2370+
2371+#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2372+
2373+static inline bool ep_is_in(const struct jz4740_ep *ep)
2374+{
2375+ return (ep->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN;
2376+}
2377+
2378+static inline uint8_t ep_index(const struct jz4740_ep *ep)
2379+{
2380+ return ep->bEndpointAddress & 0xf;
2381+}
2382+
2383+#endif /* __USB_GADGET_JZ4740_H__ */
2384--
23851.7.5.4
2386
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release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



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