Root/package/ltq-dsl/src/ifxmips_atm_amazon_se.c

1/******************************************************************************
2**
3** FILE NAME : ifxmips_atm_amazon_se.c
4** PROJECT : UEIP
5** MODULES : ATM
6**
7** DATE : 7 Jul 2009
8** AUTHOR : Xu Liang
9** DESCRIPTION : ATM driver common source file (core functions)
10** COPYRIGHT : Copyright (c) 2006
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 07 JUL 2009 Xu Liang Init Version
22*******************************************************************************/
23
24
25
26/*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31
32/*
33 * Common Head File
34 */
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/version.h>
38#include <linux/types.h>
39#include <linux/errno.h>
40#include <linux/proc_fs.h>
41#include <linux/init.h>
42#include <linux/ioctl.h>
43#include <linux/clk.h>
44#include <asm/delay.h>
45
46/*
47 * Chip Specific Head File
48 */
49#include <lantiq_soc.h>
50#include "ifxmips_compat.h"
51#include "ifxmips_atm_core.h"
52#include "ifxmips_atm_fw_amazon_se.h"
53
54
55
56/*
57 * ####################################
58 * Definition
59 * ####################################
60 */
61
62/*
63 * EMA Settings
64 */
65#define EMA_CMD_BUF_LEN 0x0040
66#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
67#define EMA_DATA_BUF_LEN 0x0100
68#define EMA_DATA_BASE_ADDR (0x00000B00 << 2)
69#define EMA_WRITE_BURST 0x2
70#define EMA_READ_BURST 0x2
71
72
73
74/*
75 * ####################################
76 * Declaration
77 * ####################################
78 */
79
80/*
81 * Hardware Init/Uninit Functions
82 */
83static inline void init_pmu(void);
84static inline void uninit_pmu(void);
85static inline void reset_ppe(void);
86static inline void init_ema(void);
87static inline void init_mailbox(void);
88static inline void init_atm_tc(void);
89static inline void clear_share_buffer(void);
90
91
92
93/*
94 * ####################################
95 * Local Variable
96 * ####################################
97 */
98
99
100
101/*
102 * ####################################
103 * Local Function
104 * ####################################
105 */
106
107static inline void init_pmu(void)
108{
109    //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
110    //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
111/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
112    PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
113    PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
114    //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
115    PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
116    DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
117    struct clk *clk = clk_get_sys("ltq_dsl", NULL);
118    clk_enable(clk);
119}
120
121static inline void uninit_pmu(void)
122{
123/* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
124    PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
125    PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
126    //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
127    PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
128    DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
129    //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);*/
130    struct clk *clk = clk_get_sys("ltq_dsl", NULL);
131    clk_disable(clk);
132}
133
134static inline void reset_ppe(void)
135{
136#ifdef MODULE
137/* unsigned int etop_cfg;
138    unsigned int etop_mdio_cfg;
139    unsigned int etop_ig_plen_ctrl;
140    unsigned int enet_mac_cfg;
141
142    etop_cfg = *IFX_PP32_ETOP_CFG;
143    etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
144    etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
145    enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
146
147    *IFX_PP32_ETOP_CFG = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001;
148
149    // reset PPE
150    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
151
152    *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
153    *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
154    *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
155    *IFX_PP32_ETOP_CFG = etop_cfg;*/
156#endif
157}
158
159static inline void init_ema(void)
160{
161    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
162    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
163    IFX_REG_W32(0x000000FF, EMA_IER);
164    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
165}
166
167static inline void init_mailbox(void)
168{
169    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
170    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
171    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
172    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
173}
174
175static inline void init_atm_tc(void)
176{
177    IFX_REG_W32(0x0000, DREG_AT_CTRL);
178    IFX_REG_W32(0x0000, DREG_AR_CTRL);
179    IFX_REG_W32(0x0, DREG_AT_IDLE0);
180    IFX_REG_W32(0x0, DREG_AT_IDLE1);
181    IFX_REG_W32(0x0, DREG_AR_IDLE0);
182    IFX_REG_W32(0x0, DREG_AR_IDLE1);
183    IFX_REG_W32(0x40, RFBI_CFG);
184    IFX_REG_W32(0x0700, SFSM_DBA0);
185    IFX_REG_W32(0x0818, SFSM_DBA1);
186    IFX_REG_W32(0x0930, SFSM_CBA0);
187    IFX_REG_W32(0x0944, SFSM_CBA1);
188    IFX_REG_W32(0x14014, SFSM_CFG0);
189    IFX_REG_W32(0x14014, SFSM_CFG1);
190    IFX_REG_W32(0x0958, FFSM_DBA0);
191    IFX_REG_W32(0x09AC, FFSM_DBA1);
192    IFX_REG_W32(0x10006, FFSM_CFG0);
193    IFX_REG_W32(0x10006, FFSM_CFG1);
194    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
195    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
196}
197
198static inline void clear_share_buffer(void)
199{
200    volatile u32 *p = SB_RAM0_ADDR(0);
201    unsigned int i;
202
203    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ )
204        IFX_REG_W32(0, p++);
205}
206
207/*
208 * Description:
209 * Download PPE firmware binary code.
210 * Input:
211 * src --- u32 *, binary code buffer
212 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
213 * Output:
214 * int --- IFX_SUCCESS: Success
215 * else: Error Code
216 */
217static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
218{
219    volatile u32 *dest;
220
221    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
222        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
223        return IFX_ERROR;
224
225    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
226        IFX_REG_W32(0x00, CDM_CFG);
227    else
228        IFX_REG_W32(0x04, CDM_CFG);
229
230    /* copy code */
231    dest = CDM_CODE_MEMORY(0, 0);
232    while ( code_dword_len-- > 0 )
233        IFX_REG_W32(*code_src++, dest++);
234
235    /* copy data */
236    dest = CDM_DATA_MEMORY(0, 0);
237    while ( data_dword_len-- > 0 )
238        IFX_REG_W32(*data_src++, dest++);
239
240    return IFX_SUCCESS;
241}
242
243
244
245/*
246 * ####################################
247 * Global Function
248 * ####################################
249 */
250
251extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
252{
253    ASSERT(major != NULL, "pointer is NULL");
254    ASSERT(minor != NULL, "pointer is NULL");
255
256#ifdef VER_IN_FIRMWARE
257    *major = FW_VER_ID->major;
258    *minor = FW_VER_ID->minor;
259#else
260    *major = ATM_FW_VER_MAJOR;
261    *minor = ATM_FW_VER_MINOR;
262#endif
263}
264
265void ifx_atm_init_chip(void)
266{
267    init_pmu();
268
269    reset_ppe();
270
271    init_ema();
272
273    init_mailbox();
274
275    init_atm_tc();
276
277    clear_share_buffer();
278}
279
280void ifx_atm_uninit_chip(void)
281{
282    uninit_pmu();
283}
284
285/*
286 * Description:
287 * Initialize and start up PP32.
288 * Input:
289 * none
290 * Output:
291 * int --- IFX_SUCCESS: Success
292 * else: Error Code
293 */
294int ifx_pp32_start(int pp32)
295{
296    int ret;
297
298    /* download firmware */
299    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
300    if ( ret != IFX_SUCCESS )
301        return ret;
302
303    /* run PP32 */
304    IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL);
305
306    /* idle for a while to let PP32 init itself */
307    udelay(10);
308
309    return IFX_SUCCESS;
310}
311
312/*
313 * Description:
314 * Halt PP32.
315 * Input:
316 * none
317 * Output:
318 * none
319 */
320void ifx_pp32_stop(int pp32)
321{
322    /* halt PP32 */
323    IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL);
324}
325

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