Root/package/ltq-dsl/src/ifxmips_atm_ar9.c

1/******************************************************************************
2**
3** FILE NAME : ifxmips_atm_ar9.c
4** PROJECT : UEIP
5** MODULES : ATM
6**
7** DATE : 7 Jul 2009
8** AUTHOR : Xu Liang
9** DESCRIPTION : ATM driver common source file (core functions)
10** COPYRIGHT : Copyright (c) 2006
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 07 JUL 2009 Xu Liang Init Version
22*******************************************************************************/
23
24
25
26/*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31
32/*
33 * Common Head File
34 */
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/version.h>
38#include <linux/types.h>
39#include <linux/errno.h>
40#include <linux/proc_fs.h>
41#include <linux/init.h>
42#include <linux/ioctl.h>
43#include <linux/clk.h>
44#include <asm/delay.h>
45
46/*
47 * Chip Specific Head File
48 */
49#include <lantiq_soc.h>
50#include "ifxmips_compat.h"
51#define IFX_MEI_BSP 1
52#include "ifxmips_mei_interface.h"
53#include "ifxmips_atm_core.h"
54#include "ifxmips_atm_ppe_common.h"
55 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
56  #include "ifxmips_atm_fw_ar9_retx.h"
57#else
58  #include "ifxmips_atm_fw_ar9.h"
59#endif
60
61
62
63/*
64 * ####################################
65 * Definition
66 * ####################################
67 */
68
69/*
70 * EMA Settings
71 */
72#define EMA_CMD_BUF_LEN 0x0040
73#define EMA_CMD_BASE_ADDR (0x00003B80 << 2)
74#define EMA_DATA_BUF_LEN 0x0100
75#define EMA_DATA_BASE_ADDR (0x00003C00 << 2)
76#define EMA_WRITE_BURST 0x2
77#define EMA_READ_BURST 0x2
78
79
80
81/*
82 * ####################################
83 * Declaration
84 * ####################################
85 */
86
87/*
88 * Hardware Init/Uninit Functions
89 */
90static inline void init_pmu(void);
91static inline void uninit_pmu(void);
92static inline void reset_ppe(void);
93static inline void init_ema(void);
94static inline void init_mailbox(void);
95static inline void init_atm_tc(void);
96static inline void clear_share_buffer(void);
97
98
99
100/*
101 * ####################################
102 * Local Variable
103 * ####################################
104 */
105
106
107
108/*
109 * ####################################
110 * Local Function
111 * ####################################
112 */
113
114static inline void init_pmu(void)
115{
116    //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
117    //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
118/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
119    PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
120    PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
121    PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
122    PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
123    DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
124    struct clk *clk = clk_get_sys("ltq_dsl", NULL);
125    clk_enable(clk);
126}
127
128static inline void uninit_pmu(void)
129{
130  /* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
131    PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
132    PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
133    PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
134    PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
135    DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);*/
136    //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
137    struct clk *clk = clk_get_sys("ltq_dsl", NULL);
138    clk_disable(clk);
139}
140
141static inline void reset_ppe(void)
142{
143#ifdef MODULE
144    // reset PPE
145    //ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
146#endif
147}
148
149static inline void init_ema(void)
150{
151    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
152    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
153    IFX_REG_W32(0x000000FF, EMA_IER);
154    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
155}
156
157static inline void init_mailbox(void)
158{
159    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
160    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
161    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
162    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
163}
164
165static inline void init_atm_tc(void)
166{
167}
168
169static inline void clear_share_buffer(void)
170{
171    volatile u32 *p = SB_RAM0_ADDR(0);
172    unsigned int i;
173
174    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ )
175        IFX_REG_W32(0, p++);
176}
177
178/*
179 * Description:
180 * Download PPE firmware binary code.
181 * Input:
182 * src --- u32 *, binary code buffer
183 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
184 * Output:
185 * int --- IFX_SUCCESS: Success
186 * else: Error Code
187 */
188static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
189{
190    volatile u32 *dest;
191
192    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
193        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
194        return IFX_ERROR;
195
196    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
197        IFX_REG_W32(0x00, CDM_CFG);
198    else
199        IFX_REG_W32(0x04, CDM_CFG);
200
201    /* copy code */
202    dest = CDM_CODE_MEMORY(0, 0);
203    while ( code_dword_len-- > 0 )
204        IFX_REG_W32(*code_src++, dest++);
205
206    /* copy data */
207    dest = CDM_DATA_MEMORY(0, 0);
208    while ( data_dword_len-- > 0 )
209        IFX_REG_W32(*data_src++, dest++);
210
211    return IFX_SUCCESS;
212}
213
214
215
216/*
217 * ####################################
218 * Global Function
219 * ####################################
220 */
221
222extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
223{
224    ASSERT(major != NULL, "pointer is NULL");
225    ASSERT(minor != NULL, "pointer is NULL");
226
227#if (defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX) || defined(VER_IN_FIRMWARE)
228    *major = FW_VER_ID->major;
229    *minor = FW_VER_ID->minor;
230#else
231    *major = ATM_FW_VER_MAJOR;
232    *minor = ATM_FW_VER_MINOR;
233#endif
234}
235
236void ifx_atm_init_chip(void)
237{
238    init_pmu();
239
240    reset_ppe();
241
242    init_ema();
243
244    init_mailbox();
245
246    init_atm_tc();
247
248    clear_share_buffer();
249}
250
251void ifx_atm_uninit_chip(void)
252{
253    uninit_pmu();
254}
255
256/*
257 * Description:
258 * Initialize and start up PP32.
259 * Input:
260 * none
261 * Output:
262 * int --- IFX_SUCCESS: Success
263 * else: Error Code
264 */
265int ifx_pp32_start(int pp32)
266{
267    int ret;
268
269    /* download firmware */
270    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
271    if ( ret != IFX_SUCCESS )
272        return ret;
273
274    /* run PP32 */
275    IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
276
277    /* idle for a while to let PP32 init itself */
278    udelay(10);
279
280    return IFX_SUCCESS;
281}
282
283/*
284 * Description:
285 * Halt PP32.
286 * Input:
287 * none
288 * Output:
289 * none
290 */
291void ifx_pp32_stop(int pp32)
292{
293    /* halt PP32 */
294    IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
295}
296

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