Root/package/ltq-dsl/src/ifxmips_atm_danube.c

1/******************************************************************************
2**
3** FILE NAME : ifxmips_atm_danube.c
4** PROJECT : UEIP
5** MODULES : ATM
6**
7** DATE : 7 Jul 2009
8** AUTHOR : Xu Liang
9** DESCRIPTION : ATM driver common source file (core functions)
10** COPYRIGHT : Copyright (c) 2006
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 07 JUL 2009 Xu Liang Init Version
22*******************************************************************************/
23
24
25
26/*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31
32/*
33 * Common Head File
34 */
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/version.h>
38#include <linux/types.h>
39#include <linux/errno.h>
40#include <linux/proc_fs.h>
41#include <linux/init.h>
42#include <linux/ioctl.h>
43#include <linux/clk.h>
44#include <asm/delay.h>
45
46/*
47 * Chip Specific Head File
48 */
49#include <lantiq_soc.h>
50#include "ifxmips_compat.h"
51#include "ifxmips_atm_core.h"
52#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
53  #include "ifxmips_atm_fw_danube_retx.h"
54#else
55  #include "ifxmips_atm_fw_danube.h"
56#endif
57
58/*
59 * ####################################
60 * Definition
61 * ####################################
62 */
63
64/*
65 * EMA Settings
66 */
67#define EMA_CMD_BUF_LEN 0x0040
68#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
69#define EMA_DATA_BUF_LEN 0x0100
70#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
71#define EMA_WRITE_BURST 0x2
72#define EMA_READ_BURST 0x2
73
74
75
76/*
77 * ####################################
78 * Declaration
79 * ####################################
80 */
81
82/*
83 * Hardware Init/Uninit Functions
84 */
85static inline void init_pmu(void);
86static inline void uninit_pmu(void);
87static inline void reset_ppe(void);
88static inline void init_ema(void);
89static inline void init_mailbox(void);
90static inline void init_atm_tc(void);
91static inline void clear_share_buffer(void);
92
93
94
95/*
96 * ####################################
97 * Local Variable
98 * ####################################
99 */
100
101
102
103/*
104 * ####################################
105 * Local Function
106 * ####################################
107 */
108
109static inline void init_pmu(void)
110{
111    //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
112    //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
113/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
114    PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
115    PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
116    PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
117    PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
118    DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
119    struct clk *clk = clk_get_sys("ltq_dsl", NULL);
120    clk_enable(clk);
121}
122
123static inline void uninit_pmu(void)
124{
125/* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
126    PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
127    PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
128    PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
129    PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
130    DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);*/
131    //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
132    struct clk *clk = clk_get_sys("ltq_dsl", NULL);
133    clk_disable(clk);
134}
135
136static inline void reset_ppe(void)
137{
138#if 0 //def MODULE
139    unsigned int etop_cfg;
140    unsigned int etop_mdio_cfg;
141    unsigned int etop_ig_plen_ctrl;
142    unsigned int enet_mac_cfg;
143
144    etop_cfg = *IFX_PP32_ETOP_CFG;
145    etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
146    etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
147    enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
148
149    *IFX_PP32_ETOP_CFG &= ~0x03C0;
150
151    // reset PPE
152    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
153
154    *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
155    *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
156    *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
157    *IFX_PP32_ETOP_CFG = etop_cfg;
158#endif
159}
160
161static inline void init_ema(void)
162{
163    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
164    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
165    IFX_REG_W32(0x000000FF, EMA_IER);
166    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
167}
168
169static inline void init_mailbox(void)
170{
171    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
172    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
173    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
174    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
175}
176
177static inline void init_atm_tc(void)
178{
179    IFX_REG_W32(0x0000, DREG_AT_CTRL);
180    IFX_REG_W32(0x0000, DREG_AR_CTRL);
181    IFX_REG_W32(0x0, DREG_AT_IDLE0);
182    IFX_REG_W32(0x0, DREG_AT_IDLE1);
183    IFX_REG_W32(0x0, DREG_AR_IDLE0);
184    IFX_REG_W32(0x0, DREG_AR_IDLE1);
185    IFX_REG_W32(0x40, RFBI_CFG);
186    IFX_REG_W32(0x1600, SFSM_DBA0);
187    IFX_REG_W32(0x1718, SFSM_DBA1);
188    IFX_REG_W32(0x1830, SFSM_CBA0);
189    IFX_REG_W32(0x1844, SFSM_CBA1);
190    IFX_REG_W32(0x14014, SFSM_CFG0);
191    IFX_REG_W32(0x14014, SFSM_CFG1);
192    IFX_REG_W32(0x1858, FFSM_DBA0);
193    IFX_REG_W32(0x18AC, FFSM_DBA1);
194    IFX_REG_W32(0x10006, FFSM_CFG0);
195    IFX_REG_W32(0x10006, FFSM_CFG1);
196    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
197    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
198}
199
200static inline void clear_share_buffer(void)
201{
202    volatile u32 *p = SB_RAM0_ADDR(0);
203    unsigned int i;
204
205    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
206        IFX_REG_W32(0, p++);
207}
208
209/*
210 * Description:
211 * Download PPE firmware binary code.
212 * Input:
213 * src --- u32 *, binary code buffer
214 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
215 * Output:
216 * int --- IFX_SUCCESS: Success
217 * else: Error Code
218 */
219static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
220{
221    volatile u32 *dest;
222
223    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
224        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
225        return IFX_ERROR;
226
227    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
228        IFX_REG_W32(0x00, CDM_CFG);
229    else
230        IFX_REG_W32(0x04, CDM_CFG);
231
232    /* copy code */
233    dest = CDM_CODE_MEMORY(0, 0);
234    while ( code_dword_len-- > 0 )
235        IFX_REG_W32(*code_src++, dest++);
236
237    /* copy data */
238    dest = CDM_DATA_MEMORY(0, 0);
239    while ( data_dword_len-- > 0 )
240        IFX_REG_W32(*data_src++, dest++);
241
242    return IFX_SUCCESS;
243}
244
245
246
247/*
248 * ####################################
249 * Global Function
250 * ####################################
251 */
252
253extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
254{
255    ASSERT(major != NULL, "pointer is NULL");
256    ASSERT(minor != NULL, "pointer is NULL");
257
258#if (defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX) || defined(VER_IN_FIRMWARE)
259    *major = FW_VER_ID->major;
260    *minor = FW_VER_ID->minor;
261#else
262    *major = ATM_FW_VER_MAJOR;
263    *minor = ATM_FW_VER_MINOR;
264#endif
265}
266
267void ifx_atm_init_chip(void)
268{
269    init_pmu();
270
271    reset_ppe();
272
273    init_ema();
274
275    init_mailbox();
276
277    init_atm_tc();
278
279    clear_share_buffer();
280}
281
282void ifx_atm_uninit_chip(void)
283{
284    uninit_pmu();
285}
286
287/*
288 * Description:
289 * Initialize and start up PP32.
290 * Input:
291 * none
292 * Output:
293 * int --- IFX_SUCCESS: Success
294 * else: Error Code
295 */
296int ifx_pp32_start(int pp32)
297{
298    int ret;
299
300    /* download firmware */
301    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
302    if ( ret != IFX_SUCCESS )
303        return ret;
304
305    /* run PP32 */
306    IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
307
308    /* idle for a while to let PP32 init itself */
309    udelay(10);
310
311    return IFX_SUCCESS;
312}
313
314/*
315 * Description:
316 * Halt PP32.
317 * Input:
318 * none
319 * Output:
320 * none
321 */
322void ifx_pp32_stop(int pp32)
323{
324    /* halt PP32 */
325    IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
326}
327

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