Root/package/mac80211/patches/620-rt2x00-support-rt3352.patch

1From 03839951515b0ea2b21d649b1fe7b63f9817d0c8 Mon Sep 17 00:00:00 2001
2From: Daniel Golle <dgolle@allnet.de>
3Date: Sun, 9 Sep 2012 14:24:39 +0300
4Subject: [PATCH] rt2x00: add MediaTek/RaLink Rt3352 WiSoC
5
6Support for the RT3352 WiSoC was developed for and tested with the ALL5002
7devboard running OpenWrt. For now, this supports only devices with internal
8TXALC. Corrections were made according to the remarks of Stanislaw Gruszka and
9Gertjan van Wingerde, thank you guys for reviewing!
10
11Signed-off-by: Daniel Golle <dgolle@allnet.de>
12Signed-off-by: John W. Linville <linville@tuxdriver.com>
13---
14 drivers/net/wireless/rt2x00/rt2800.h | 5 +
15 drivers/net/wireless/rt2x00/rt2800lib.c | 211 +++++++++++++++++++++++++++++++-
16 drivers/net/wireless/rt2x00/rt2x00.h | 1 +
17 3 files changed, 212 insertions(+), 5 deletions(-)
18
19--- a/drivers/net/wireless/rt2x00/rt2800.h
20+++ b/drivers/net/wireless/rt2x00/rt2800.h
21@@ -1943,6 +1943,11 @@ struct mac_iveiv_entry {
22 #define BBP47_TSSI_ADC6 FIELD8(0x80)
23 
24 /*
25+ * BBP 49
26+ */
27+#define BBP49_UPDATE_FLAG FIELD8(0x01)
28+
29+/*
30  * BBP 109
31  */
32 #define BBP109_TX0_POWER FIELD8(0x0f)
33--- a/drivers/net/wireless/rt2x00/rt2800lib.c
34+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
35@@ -1615,6 +1615,7 @@ void rt2800_config_ant(struct rt2x00_dev
36     case 1:
37         if (rt2x00_rt(rt2x00dev, RT3070) ||
38             rt2x00_rt(rt2x00dev, RT3090) ||
39+ rt2x00_rt(rt2x00dev, RT3352) ||
40             rt2x00_rt(rt2x00dev, RT3390)) {
41             rt2x00_eeprom_read(rt2x00dev,
42                        EEPROM_NIC_CONF1, &eeprom);
43@@ -2053,6 +2054,60 @@ static void rt2800_config_channel_rf3290
44     }
45 }
46 
47+static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
48+ struct ieee80211_conf *conf,
49+ struct rf_channel *rf,
50+ struct channel_info *info)
51+{
52+ u8 rfcsr;
53+
54+ rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
55+ rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
56+
57+ rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
58+ rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
59+ rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
60+
61+ if (info->default_power1 > POWER_BOUND)
62+ rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
63+ else
64+ rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
65+
66+ if (info->default_power2 > POWER_BOUND)
67+ rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
68+ else
69+ rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
70+
71+ rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
72+ if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
73+ rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
74+ else
75+ rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
76+
77+ rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
78+
79+ rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
80+ rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
81+ rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
82+
83+ if ( rt2x00dev->default_ant.tx_chain_num == 2 )
84+ rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
85+ else
86+ rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
87+
88+ if ( rt2x00dev->default_ant.rx_chain_num == 2 )
89+ rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
90+ else
91+ rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
92+
93+ rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
94+ rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
95+
96+ rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
97+
98+ rt2800_rfcsr_write(rt2x00dev, 31, 80);
99+}
100+
101 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
102                      struct ieee80211_conf *conf,
103                      struct rf_channel *rf,
104@@ -2182,6 +2237,9 @@ static void rt2800_config_channel(struct
105     case RF3290:
106         rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
107         break;
108+ case RF3322:
109+ rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
110+ break;
111     case RF5360:
112     case RF5370:
113     case RF5372:
114@@ -2194,6 +2252,7 @@ static void rt2800_config_channel(struct
115     }
116 
117     if (rt2x00_rf(rt2x00dev, RF3290) ||
118+ rt2x00_rf(rt2x00dev, RF3322) ||
119         rt2x00_rf(rt2x00dev, RF5360) ||
120         rt2x00_rf(rt2x00dev, RF5370) ||
121         rt2x00_rf(rt2x00dev, RF5372) ||
122@@ -2212,10 +2271,17 @@ static void rt2800_config_channel(struct
123     /*
124      * Change BBP settings
125      */
126- rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
127- rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
128- rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
129- rt2800_bbp_write(rt2x00dev, 86, 0);
130+ if (rt2x00_rt(rt2x00dev, RT3352)) {
131+ rt2800_bbp_write(rt2x00dev, 27, 0x0);
132+ rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
133+ rt2800_bbp_write(rt2x00dev, 27, 0x20);
134+ rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
135+ } else {
136+ rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
137+ rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
138+ rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
139+ rt2800_bbp_write(rt2x00dev, 86, 0);
140+ }
141 
142     if (rf->channel <= 14) {
143         if (!rt2x00_rt(rt2x00dev, RT5390) &&
144@@ -2310,6 +2376,15 @@ static void rt2800_config_channel(struct
145     rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
146     rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
147     rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
148+
149+ /*
150+ * Clear update flag
151+ */
152+ if (rt2x00_rt(rt2x00dev, RT3352)) {
153+ rt2800_bbp_read(rt2x00dev, 49, &bbp);
154+ rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
155+ rt2800_bbp_write(rt2x00dev, 49, bbp);
156+ }
157 }
158 
159 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
160@@ -2998,6 +3073,10 @@ static int rt2800_init_registers(struct
161         rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
162         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
163         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
164+ } else if (rt2x00_rt(rt2x00dev, RT3352)) {
165+ rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
166+ rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
167+ rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
168     } else if (rt2x00_rt(rt2x00dev, RT3572)) {
169         rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
170         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
171@@ -3378,6 +3457,11 @@ static int rt2800_init_bbp(struct rt2x00
172              rt2800_wait_bbp_ready(rt2x00dev)))
173         return -EACCES;
174 
175+ if (rt2x00_rt(rt2x00dev, RT3352)) {
176+ rt2800_bbp_write(rt2x00dev, 3, 0x00);
177+ rt2800_bbp_write(rt2x00dev, 4, 0x50);
178+ }
179+
180     if (rt2x00_rt(rt2x00dev, RT3290) ||
181         rt2x00_rt(rt2x00dev, RT5390) ||
182         rt2x00_rt(rt2x00dev, RT5392)) {
183@@ -3388,15 +3472,20 @@ static int rt2800_init_bbp(struct rt2x00
184 
185     if (rt2800_is_305x_soc(rt2x00dev) ||
186         rt2x00_rt(rt2x00dev, RT3290) ||
187+ rt2x00_rt(rt2x00dev, RT3352) ||
188         rt2x00_rt(rt2x00dev, RT3572) ||
189         rt2x00_rt(rt2x00dev, RT5390) ||
190         rt2x00_rt(rt2x00dev, RT5392))
191         rt2800_bbp_write(rt2x00dev, 31, 0x08);
192 
193+ if (rt2x00_rt(rt2x00dev, RT3352))
194+ rt2800_bbp_write(rt2x00dev, 47, 0x48);
195+
196     rt2800_bbp_write(rt2x00dev, 65, 0x2c);
197     rt2800_bbp_write(rt2x00dev, 66, 0x38);
198 
199     if (rt2x00_rt(rt2x00dev, RT3290) ||
200+ rt2x00_rt(rt2x00dev, RT3352) ||
201         rt2x00_rt(rt2x00dev, RT5390) ||
202         rt2x00_rt(rt2x00dev, RT5392))
203         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
204@@ -3405,6 +3494,7 @@ static int rt2800_init_bbp(struct rt2x00
205         rt2800_bbp_write(rt2x00dev, 69, 0x16);
206         rt2800_bbp_write(rt2x00dev, 73, 0x12);
207     } else if (rt2x00_rt(rt2x00dev, RT3290) ||
208+ rt2x00_rt(rt2x00dev, RT3352) ||
209            rt2x00_rt(rt2x00dev, RT5390) ||
210            rt2x00_rt(rt2x00dev, RT5392)) {
211         rt2800_bbp_write(rt2x00dev, 69, 0x12);
212@@ -3436,6 +3526,10 @@ static int rt2800_init_bbp(struct rt2x00
213     } else if (rt2800_is_305x_soc(rt2x00dev)) {
214         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
215         rt2800_bbp_write(rt2x00dev, 80, 0x08);
216+ } else if (rt2x00_rt(rt2x00dev, RT3352)) {
217+ rt2800_bbp_write(rt2x00dev, 78, 0x0e);
218+ rt2800_bbp_write(rt2x00dev, 80, 0x08);
219+ rt2800_bbp_write(rt2x00dev, 81, 0x37);
220     } else {
221         rt2800_bbp_write(rt2x00dev, 81, 0x37);
222     }
223@@ -3465,18 +3559,21 @@ static int rt2800_init_bbp(struct rt2x00
224         rt2800_bbp_write(rt2x00dev, 84, 0x99);
225 
226     if (rt2x00_rt(rt2x00dev, RT3290) ||
227+ rt2x00_rt(rt2x00dev, RT3352) ||
228         rt2x00_rt(rt2x00dev, RT5390) ||
229         rt2x00_rt(rt2x00dev, RT5392))
230         rt2800_bbp_write(rt2x00dev, 86, 0x38);
231     else
232         rt2800_bbp_write(rt2x00dev, 86, 0x00);
233 
234- if (rt2x00_rt(rt2x00dev, RT5392))
235+ if (rt2x00_rt(rt2x00dev, RT3352) ||
236+ rt2x00_rt(rt2x00dev, RT5392))
237         rt2800_bbp_write(rt2x00dev, 88, 0x90);
238 
239     rt2800_bbp_write(rt2x00dev, 91, 0x04);
240 
241     if (rt2x00_rt(rt2x00dev, RT3290) ||
242+ rt2x00_rt(rt2x00dev, RT3352) ||
243         rt2x00_rt(rt2x00dev, RT5390) ||
244         rt2x00_rt(rt2x00dev, RT5392))
245         rt2800_bbp_write(rt2x00dev, 92, 0x02);
246@@ -3493,6 +3590,7 @@ static int rt2800_init_bbp(struct rt2x00
247         rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
248         rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
249         rt2x00_rt(rt2x00dev, RT3290) ||
250+ rt2x00_rt(rt2x00dev, RT3352) ||
251         rt2x00_rt(rt2x00dev, RT3572) ||
252         rt2x00_rt(rt2x00dev, RT5390) ||
253         rt2x00_rt(rt2x00dev, RT5392) ||
254@@ -3502,6 +3600,7 @@ static int rt2800_init_bbp(struct rt2x00
255         rt2800_bbp_write(rt2x00dev, 103, 0x00);
256 
257     if (rt2x00_rt(rt2x00dev, RT3290) ||
258+ rt2x00_rt(rt2x00dev, RT3352) ||
259         rt2x00_rt(rt2x00dev, RT5390) ||
260         rt2x00_rt(rt2x00dev, RT5392))
261         rt2800_bbp_write(rt2x00dev, 104, 0x92);
262@@ -3510,6 +3609,8 @@ static int rt2800_init_bbp(struct rt2x00
263         rt2800_bbp_write(rt2x00dev, 105, 0x01);
264     else if (rt2x00_rt(rt2x00dev, RT3290))
265         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
266+ else if (rt2x00_rt(rt2x00dev, RT3352))
267+ rt2800_bbp_write(rt2x00dev, 105, 0x34);
268     else if (rt2x00_rt(rt2x00dev, RT5390) ||
269              rt2x00_rt(rt2x00dev, RT5392))
270         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
271@@ -3519,11 +3620,16 @@ static int rt2800_init_bbp(struct rt2x00
272     if (rt2x00_rt(rt2x00dev, RT3290) ||
273         rt2x00_rt(rt2x00dev, RT5390))
274         rt2800_bbp_write(rt2x00dev, 106, 0x03);
275+ else if (rt2x00_rt(rt2x00dev, RT3352))
276+ rt2800_bbp_write(rt2x00dev, 106, 0x05);
277     else if (rt2x00_rt(rt2x00dev, RT5392))
278         rt2800_bbp_write(rt2x00dev, 106, 0x12);
279     else
280         rt2800_bbp_write(rt2x00dev, 106, 0x35);
281 
282+ if (rt2x00_rt(rt2x00dev, RT3352))
283+ rt2800_bbp_write(rt2x00dev, 120, 0x50);
284+
285     if (rt2x00_rt(rt2x00dev, RT3290) ||
286         rt2x00_rt(rt2x00dev, RT5390) ||
287         rt2x00_rt(rt2x00dev, RT5392))
288@@ -3534,6 +3640,9 @@ static int rt2800_init_bbp(struct rt2x00
289         rt2800_bbp_write(rt2x00dev, 135, 0xf6);
290     }
291 
292+ if (rt2x00_rt(rt2x00dev, RT3352))
293+ rt2800_bbp_write(rt2x00dev, 137, 0x0f);
294+
295     if (rt2x00_rt(rt2x00dev, RT3071) ||
296         rt2x00_rt(rt2x00dev, RT3090) ||
297         rt2x00_rt(rt2x00dev, RT3390) ||
298@@ -3574,6 +3683,28 @@ static int rt2800_init_bbp(struct rt2x00
299         rt2800_bbp_write(rt2x00dev, 3, value);
300     }
301 
302+ if (rt2x00_rt(rt2x00dev, RT3352)) {
303+ rt2800_bbp_write(rt2x00dev, 163, 0xbd);
304+ /* Set ITxBF timeout to 0x9c40=1000msec */
305+ rt2800_bbp_write(rt2x00dev, 179, 0x02);
306+ rt2800_bbp_write(rt2x00dev, 180, 0x00);
307+ rt2800_bbp_write(rt2x00dev, 182, 0x40);
308+ rt2800_bbp_write(rt2x00dev, 180, 0x01);
309+ rt2800_bbp_write(rt2x00dev, 182, 0x9c);
310+ rt2800_bbp_write(rt2x00dev, 179, 0x00);
311+ /* Reprogram the inband interface to put right values in RXWI */
312+ rt2800_bbp_write(rt2x00dev, 142, 0x04);
313+ rt2800_bbp_write(rt2x00dev, 143, 0x3b);
314+ rt2800_bbp_write(rt2x00dev, 142, 0x06);
315+ rt2800_bbp_write(rt2x00dev, 143, 0xa0);
316+ rt2800_bbp_write(rt2x00dev, 142, 0x07);
317+ rt2800_bbp_write(rt2x00dev, 143, 0xa1);
318+ rt2800_bbp_write(rt2x00dev, 142, 0x08);
319+ rt2800_bbp_write(rt2x00dev, 143, 0xa2);
320+
321+ rt2800_bbp_write(rt2x00dev, 148, 0xc8);
322+ }
323+
324     if (rt2x00_rt(rt2x00dev, RT5390) ||
325         rt2x00_rt(rt2x00dev, RT5392)) {
326         int ant, div_mode;
327@@ -3707,6 +3838,7 @@ static int rt2800_init_rfcsr(struct rt2x
328         !rt2x00_rt(rt2x00dev, RT3071) &&
329         !rt2x00_rt(rt2x00dev, RT3090) &&
330         !rt2x00_rt(rt2x00dev, RT3290) &&
331+ !rt2x00_rt(rt2x00dev, RT3352) &&
332         !rt2x00_rt(rt2x00dev, RT3390) &&
333         !rt2x00_rt(rt2x00dev, RT3572) &&
334         !rt2x00_rt(rt2x00dev, RT5390) &&
335@@ -3903,6 +4035,70 @@ static int rt2800_init_rfcsr(struct rt2x
336         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
337         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
338         return 0;
339+ } else if (rt2x00_rt(rt2x00dev, RT3352)) {
340+ rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
341+ rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
342+ rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
343+ rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
344+ rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
345+ rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
346+ rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
347+ rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
348+ rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
349+ rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
350+ rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
351+ rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
352+ rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
353+ rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
354+ rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
355+ rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
356+ rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
357+ rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
358+ rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
359+ rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
360+ rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
361+ rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
362+ rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
363+ rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
364+ rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
365+ rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
366+ rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
367+ rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
368+ rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
369+ rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
370+ rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
371+ rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
372+ rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
373+ rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
374+ rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
375+ rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
376+ rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
377+ rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
378+ rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
379+ rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
380+ rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
381+ rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
382+ rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
383+ rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
384+ rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
385+ rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
386+ rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
387+ rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
388+ rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
389+ rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
390+ rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
391+ rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
392+ rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
393+ rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
394+ rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
395+ rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
396+ rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
397+ rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
398+ rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
399+ rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
400+ rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
401+ rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
402+ rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
403     } else if (rt2x00_rt(rt2x00dev, RT5390)) {
404         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
405         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
406@@ -4104,6 +4300,7 @@ static int rt2800_init_rfcsr(struct rt2x
407             rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
408     } else if (rt2x00_rt(rt2x00dev, RT3071) ||
409            rt2x00_rt(rt2x00dev, RT3090) ||
410+ rt2x00_rt(rt2x00dev, RT3352) ||
411            rt2x00_rt(rt2x00dev, RT3390) ||
412            rt2x00_rt(rt2x00dev, RT3572)) {
413         drv_data->calibration_bw20 =
414@@ -4566,6 +4763,7 @@ static int rt2800_init_eeprom(struct rt2
415     case RT3071:
416     case RT3090:
417     case RT3290:
418+ case RT3352:
419     case RT3390:
420     case RT3572:
421     case RT5390:
422@@ -4588,6 +4786,7 @@ static int rt2800_init_eeprom(struct rt2
423     case RF3052:
424     case RF3290:
425     case RF3320:
426+ case RF3322:
427     case RF5360:
428     case RF5370:
429     case RF5372:
430@@ -4612,6 +4811,7 @@ static int rt2800_init_eeprom(struct rt2
431 
432     if (rt2x00_rt(rt2x00dev, RT3070) ||
433         rt2x00_rt(rt2x00dev, RT3090) ||
434+ rt2x00_rt(rt2x00dev, RT3352) ||
435         rt2x00_rt(rt2x00dev, RT3390)) {
436         value = rt2x00_get_field16(eeprom,
437                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
438@@ -4904,6 +5104,7 @@ static int rt2800_probe_hw_mode(struct r
439            rt2x00_rf(rt2x00dev, RF3022) ||
440            rt2x00_rf(rt2x00dev, RF3290) ||
441            rt2x00_rf(rt2x00dev, RF3320) ||
442+ rt2x00_rf(rt2x00dev, RF3322) ||
443            rt2x00_rf(rt2x00dev, RF5360) ||
444            rt2x00_rf(rt2x00dev, RF5370) ||
445            rt2x00_rf(rt2x00dev, RF5372) ||
446--- a/drivers/net/wireless/rt2x00/rt2x00.h
447+++ b/drivers/net/wireless/rt2x00/rt2x00.h
448@@ -189,6 +189,7 @@ struct rt2x00_chip {
449 #define RT3071 0x3071
450 #define RT3090 0x3090 /* 2.4GHz PCIe */
451 #define RT3290 0x3290
452+#define RT3352 0x3352 /* WSOC */
453 #define RT3390 0x3390
454 #define RT3572 0x3572
455 #define RT3593 0x3593
456

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