Root/package/uboot-kirkwood/patches/0001-ib62x0.patch

1http://lists.denx.de/pipermail/u-boot/2012-April/122597.html
2http://patchwork.ozlabs.org/patch/153293/
3---
4
5diff --git a/MAINTAINERS b/MAINTAINERS
6index 708ded7..9d2aba7 100644
7--- a/MAINTAINERS
8+++ b/MAINTAINERS
9@@ -777,6 +777,10 @@ Linus Walleij <linus.walleij@linaro.org>
10     integratorap various
11     integratorcp various
12 
13+Luka Perkov <uboot@lukaperkov.net>
14+
15+ ib62x0 ARM926EJS
16+
17 Dave Peverley <dpeverley@mpc-data.co.uk>
18 
19     omap730p2 ARM926EJS
20diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile
21new file mode 100644
22index 0000000..d450f8d
23--- /dev/null
24+++ b/board/raidsonic/ib62x0/Makefile
25@@ -0,0 +1,43 @@
26+#
27+# (C) Copyright 2009
28+# Marvell Semiconductor <www.marvell.com>
29+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
30+#
31+# See file CREDITS for list of people who contributed to this
32+# project.
33+#
34+# This program is free software; you can redistribute it and/or
35+# modify it under the terms of the GNU General Public License as
36+# published by the Free Software Foundation; either version 2 of
37+# the License, or (at your option) any later version.
38+#
39+# This program is distributed in the hope that it will be useful,
40+# but WITHOUT ANY WARRANTY; without even the implied warranty of
41+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42+# GNU General Public License for more details.
43+#
44+# You should have received a copy of the GNU General Public License
45+# along with this program. If not, see <http://www.gnu.org/licenses/>.
46+#
47+
48+include $(TOPDIR)/config.mk
49+
50+LIB = $(obj)lib$(BOARD).o
51+
52+COBJS := ib62x0.o
53+
54+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
55+OBJS := $(addprefix $(obj),$(COBJS))
56+SOBJS := $(addprefix $(obj),$(SOBJS))
57+
58+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
59+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
60+
61+#########################################################################
62+
63+# defines $(obj).depend target
64+include $(SRCTREE)/rules.mk
65+
66+sinclude $(obj).depend
67+
68+#########################################################################
69diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
70new file mode 100644
71index 0000000..65f2c2e
72--- /dev/null
73+++ b/board/raidsonic/ib62x0/ib62x0.c
74@@ -0,0 +1,79 @@
75+/*
76+ * Copyright (C) 2011-2012
77+ * Gerald Kerma <dreagle@doukki.net>
78+ * Luka Perkov <uboot@lukaperkov.net>
79+ * Simon Baatz <gmbnomis@gmail.com>
80+ *
81+ * See file CREDITS for list of people who contributed to this
82+ * project.
83+ *
84+ * This program is free software; you can redistribute it and/or
85+ * modify it under the terms of the GNU General Public License as
86+ * published by the Free Software Foundation; either version 2 of
87+ * the License, or (at your option) any later version.
88+ *
89+ * This program is distributed in the hope that it will be useful,
90+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
91+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
92+ * GNU General Public License for more details.
93+ *
94+ * You should have received a copy of the GNU General Public License
95+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
96+ */
97+
98+#include <common.h>
99+#include <miiphy.h>
100+#include <asm/arch/cpu.h>
101+#include <asm/arch/kirkwood.h>
102+#include <asm/arch/mpp.h>
103+#include "ib62x0.h"
104+
105+DECLARE_GLOBAL_DATA_PTR;
106+
107+int board_early_init_f(void)
108+{
109+ /*
110+ * default gpio configuration
111+ * There are maximum 64 gpios controlled through 2 sets of registers
112+ * the below configuration configures mainly initial LED status
113+ */
114+ kw_config_gpio(IB62x0_OE_VAL_LOW,
115+ IB62x0_OE_VAL_HIGH,
116+ IB62x0_OE_LOW, IB62x0_OE_HIGH);
117+
118+ /* Multi-Purpose Pins Functionality configuration */
119+ u32 kwmpp_config[] = {
120+ MPP0_NF_IO2,
121+ MPP1_NF_IO3,
122+ MPP2_NF_IO4,
123+ MPP3_NF_IO5,
124+ MPP4_NF_IO6,
125+ MPP5_NF_IO7,
126+ MPP6_SYSRST_OUTn,
127+ MPP8_TW_SDA,
128+ MPP9_TW_SCK,
129+ MPP10_UART0_TXD,
130+ MPP11_UART0_RXD,
131+ MPP18_NF_IO0,
132+ MPP19_NF_IO1,
133+ MPP20_SATA1_ACTn,
134+ MPP21_SATA0_ACTn,
135+ MPP22_GPIO, /* Power LED red */
136+ MPP24_GPIO, /* Power off device */
137+ MPP25_GPIO, /* Power LED green */
138+ MPP27_GPIO, /* USB transfer LED */
139+ MPP28_GPIO, /* Reset button */
140+ MPP29_GPIO, /* USB Copy button */
141+ 0
142+ };
143+ kirkwood_mpp_conf(kwmpp_config);
144+ return 0;
145+}
146+
147+int board_init(void)
148+{
149+ /* adress of boot parameters */
150+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
151+
152+ return 0;
153+}
154diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h
155new file mode 100644
156index 0000000..0c30690
157--- /dev/null
158+++ b/board/raidsonic/ib62x0/ib62x0.h
159@@ -0,0 +1,40 @@
160+/*
161+ * Copyright (C) 2011-2012
162+ * Gerald Kerma <dreagle@doukki.net>
163+ * Simon Baatz <gmbnomis@gmail.com>
164+ * Luka Perkov <uboot@lukaperkov.net>
165+ *
166+ * See file CREDITS for list of people who contributed to this
167+ * project.
168+ *
169+ * This program is free software; you can redistribute it and/or
170+ * modify it under the terms of the GNU General Public License as
171+ * published by the Free Software Foundation; either version 2 of
172+ * the License, or (at your option) any later version.
173+ *
174+ * This program is distributed in the hope that it will be useful,
175+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
176+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
177+ * GNU General Public License for more details.
178+ *
179+ * You should have received a copy of the GNU General Public License
180+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
181+ */
182+
183+#ifndef __IB62x0_H
184+#define __IB62x0_H
185+
186+#define IB62x0_OE_LOW (~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27))
187+#define IB62x0_OE_HIGH (~(0))
188+#define IB62x0_OE_VAL_LOW 0
189+#define IB62x0_OE_VAL_HIGH 0
190+
191+/* PHY related */
192+#define MV88E1116_LED_FCTRL_REG 10
193+#define MV88E1116_CPRSP_CR3_REG 21
194+#define MV88E1116_MAC_CTRL_REG 21
195+#define MV88E1116_PGADR_REG 22
196+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
197+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
198+
199+#endif /* __IB62x0_H */
200diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
201new file mode 100644
202index 0000000..bd594eb
203--- /dev/null
204+++ b/board/raidsonic/ib62x0/kwbimage.cfg
205@@ -0,0 +1,169 @@
206+#
207+# Copyright (C) 2011-2012
208+# Gerald Kerma <dreagle@doukki.net>
209+# Simon Baatz <gmbnomis@gmail.com>
210+# Luka Perkov <uboot@lukaperkov.net>
211+#
212+# See file CREDITS for list of people who contributed to this
213+# project.
214+#
215+# This program is free software; you can redistribute it and/or
216+# modify it under the terms of the GNU General Public License as
217+# published by the Free Software Foundation; either version 2 of
218+# the License, or (at your option) any later version.
219+#
220+# This program is distributed in the hope that it will be useful,
221+# but WITHOUT ANY WARRANTY; without even the implied warranty of
222+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
223+# GNU General Public License for more details.
224+#
225+# You should have received a copy of the GNU General Public License
226+# along with this program. If not, see <http://www.gnu.org/licenses/>.
227+#
228+# Refer docs/README.kwimage for more details about how-to configure
229+# and create kirkwood boot image
230+#
231+
232+# Boot Media configurations
233+BOOT_FROM nand # change from nand to uart if building UART image
234+NAND_ECC_MODE default
235+NAND_PAGE_SIZE 0x0800
236+
237+# SOC registers configuration using bootrom header extension
238+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
239+
240+# Configure RGMII-0 interface pad voltage to 1.8V
241+DATA 0xffd100e0 0x1b1b1b9b
242+
243+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
244+DATA 0xffd01400 0x43000c30 # DDR Configuration register
245+# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
246+# bit23-14: 0x0,
247+# bit24: 0x1, enable exit self refresh mode on DDR access
248+# bit25: 0x1, required
249+# bit29-26: 0x0,
250+# bit31-30: 0x1,
251+
252+DATA 0xffd01404 0x37543000 # DDR Controller Control Low
253+# bit4: 0x0, addr/cmd in smame cycle
254+# bit5: 0x0, clk is driven during self refresh, we don't care for APX
255+# bit6: 0x0, use recommended falling edge of clk for addr/cmd
256+# bit14: 0x0, input buffer always powered up
257+# bit18: 0x1, cpu lock transaction enabled
258+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
259+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
260+# bit30-28: 0x3, required
261+# bit31: 0x0, no additional STARTBURST delay
262+
263+DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
264+# bit3-0: TRAS lsbs
265+# bit7-4: TRCD
266+# bit11-8: TRP
267+# bit15-12: TWR
268+# bit19-16: TWTR
269+# bit20: TRAS msb
270+# bit23-21: 0x0
271+# bit27-24: TRRD
272+# bit31-28: TRTP
273+
274+DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
275+# bit6-0: TRFC
276+# bit8-7: TR2R
277+# bit10-9: TR2W
278+# bit12-11: TW2W
279+# bit31-13: 0x0, required
280+
281+DATA 0xffd01410 0x0000000c # DDR Address Control
282+# bit1-0: 00, Cs0width (x8)
283+# bit3-2: 11, Cs0size (1Gb)
284+# bit5-4: 00, Cs1width (x8)
285+# bit7-6: 11, Cs1size (1Gb)
286+# bit9-8: 00, Cs2width (nonexistent
287+# bit11-10: 00, Cs2size (nonexistent
288+# bit13-12: 00, Cs3width (nonexistent
289+# bit15-14: 00, Cs3size (nonexistent
290+# bit16: 0, Cs0AddrSel
291+# bit17: 0, Cs1AddrSel
292+# bit18: 0, Cs2AddrSel
293+# bit19: 0, Cs3AddrSel
294+# bit31-20: 0x0, required
295+
296+DATA 0xffd01414 0x00000000 # DDR Open Pages Control
297+# bit0: 0, OpenPage enabled
298+# bit31-1: 0x0, required
299+
300+DATA 0xffd01418 0x00000000 # DDR Operation
301+# bit3-0: 0x0, DDR cmd
302+# bit31-4: 0x0, required
303+
304+DATA 0xffd0141c 0x00000c52 # DDR Mode
305+# bit2-0: 0x2, BurstLen=2 required
306+# bit3: 0x0, BurstType=0 required
307+# bit6-4: 0x4, CL=5
308+# bit7: 0x0, TestMode=0 normal
309+# bit8: 0x0, DLL reset=0 normal
310+# bit11-9: 0x6, auto-precharge write recovery ????????????
311+# bit12: 0x0, PD must be zero
312+# bit31-13: 0x0, required
313+
314+DATA 0xffd01420 0x00000040 # DDR Extended Mode
315+# bit0: 0, DDR DLL enabled
316+# bit1: 0, DDR drive strenght normal
317+# bit2: 1, DDR ODT control lsd (disabled)
318+# bit5-3: 0x0, required
319+# bit6: 0, DDR ODT control msb, (disabled)
320+# bit9-7: 0x0, required
321+# bit10: 0, differential DQS enabled
322+# bit11: 0, required
323+# bit12: 0, DDR output buffer enabled
324+# bit31-13: 0x0, required
325+
326+DATA 0xffd01424 0x0000f17f # DDR Controller Control High
327+# bit2-0: 0x7, required
328+# bit3: 0x1, MBUS Burst Chop disabled
329+# bit6-4: 0x7, required
330+# bit7: 0x0,
331+# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
332+# bit9: 0x0, no half clock cycle addition to dataout
333+# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
334+# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
335+# bit15-12: 0xf, required
336+# bit31-16: 0, required
337+
338+DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
339+DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
340+
341+DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
342+DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
343+# bit0: 0x1, Window enabled
344+# bit1: 0x0, Write Protect disabled
345+# bit3-2: 0x0, CS0 hit selected
346+# bit23-4: 0xfffff, required
347+# bit31-24: 0x0f, Size (i.e. 256MB)
348+
349+DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
350+DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
351+
352+DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
353+DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
354+
355+DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
356+# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
357+# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
358+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
359+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
360+
361+DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
362+# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
363+# bit3-2: 0x1, ODT1 active NEVER!
364+# bit31-4: 0x0, required
365+
366+DATA 0xffd0149c 0x0000e803 # CPU ODT Control
367+DATA 0xffd01480 0x00000001 # DDR Initialization Control
368+# bit0: 0x1, enable DDR init upon this register write
369+
370+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
371+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
372+
373+# End of Header extension
374+DATA 0x0 0x0
375diff --git a/boards.cfg b/boards.cfg
376index 3cf75c3..23f84e8 100644
377--- a/boards.cfg
378+++ b/boards.cfg
379@@ -153,6 +153,7 @@ openrd_client arm arm926ejs openrd Marvell
380 openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE
381 rd6281a arm arm926ejs - Marvell kirkwood
382 sheevaplug arm arm926ejs - Marvell kirkwood
383+ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood
384 dockstar arm arm926ejs - Seagate kirkwood
385 jadecpu arm arm926ejs jadecpu syteco mb86r0x
386 mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
387diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
388new file mode 100644
389index 0000000..85856f2
390--- /dev/null
391+++ b/include/configs/ib62x0.h
392@@ -0,0 +1,150 @@
393+/*
394+ * Copyright (C) 2011-2012
395+ * Gerald Kerma <dreagle@doukki.net>
396+ * Luka Perkov <uboot@lukaperkov.net>
397+ *
398+ * See file CREDITS for list of people who contributed to this
399+ * project.
400+ *
401+ * This program is free software; you can redistribute it and/or
402+ * modify it under the terms of the GNU General Public License as
403+ * published by the Free Software Foundation; either version 2 of
404+ * the License, or (at your option) any later version.
405+ *
406+ * This program is distributed in the hope that it will be useful,
407+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
408+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
409+ * GNU General Public License for more details.
410+ *
411+ * You should have received a copy of the GNU General Public License
412+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
413+ */
414+
415+#ifndef _CONFIG_IB62x0_H
416+#define _CONFIG_IB62x0_H
417+
418+/*
419+ * Version number information
420+ */
421+#define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS62x0"
422+
423+/*
424+ * High level configuration options
425+ */
426+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
427+#define CONFIG_KIRKWOOD /* SOC Family Name */
428+#define CONFIG_KW88F6281 /* SOC Name */
429+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
430+
431+/*
432+ * Machine type
433+ */
434+#define CONFIG_MACH_TYPE MACH_TYPE_NAS6210
435+
436+/*
437+ * Compression configuration
438+ */
439+#define CONFIG_BZIP2
440+#define CONFIG_LZMA
441+#define CONFIG_LZO
442+
443+/*
444+ * Commands configuration
445+ */
446+#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
447+#define CONFIG_SYS_MVFS
448+#include <config_cmd_default.h>
449+#define CONFIG_CMD_ENV
450+#define CONFIG_CMD_IDE
451+#define CONFIG_CMD_MII
452+#define CONFIG_CMD_NAND
453+#define CONFIG_CMD_PING
454+#define CONFIG_CMD_USB
455+
456+/*
457+ * mv-common.h should be defined after CMD configs since it used them
458+ * to enable certain macros
459+ */
460+#include "mv-common.h"
461+
462+#undef CONFIG_SYS_PROMPT
463+#define CONFIG_SYS_PROMPT "ib62x0 => "
464+
465+/*
466+ * Environment variables configuration
467+ */
468+#ifdef CONFIG_CMD_NAND
469+#define CONFIG_ENV_IS_IN_NAND
470+#define CONFIG_ENV_SECT_SIZE 0x20000
471+#else
472+#define CONFIG_ENV_IS_NOWHERE
473+#endif
474+#define CONFIG_ENV_SIZE 0x20000
475+#define CONFIG_ENV_OFFSET 0x80000
476+
477+/*
478+ * Default environment variables
479+ */
480+#define CONFIG_BOOTCOMMAND \
481+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
482+ "ubi part rootfs; " \
483+ "ubifsmount rootfs; " \
484+ "ubifsload 0x800000 ${kernel}; " \
485+ "bootm 0x800000"
486+
487+#define CONFIG_MTDPARTS \
488+ "mtdparts=orion_nand:" \
489+ "0x80000@0x0(uboot)," \
490+ "0x20000@0x80000(uboot_env)," \
491+ "-@0xa0000(rootfs)\0"
492+
493+#define CONFIG_EXTRA_ENV_SETTINGS \
494+ "console=console=ttyS0,115200\0" \
495+ "mtdids=nand0=orion_nand\0" \
496+ "mtdparts="CONFIG_MTDPARTS \
497+ "kernel=/boot/uImage\0" \
498+ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
499+
500+/*
501+ * Ethernet driver configuration
502+ */
503+#ifdef CONFIG_CMD_NET
504+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
505+#define CONFIG_PHY_BASE_ADR 0
506+#undef CONFIG_RESET_PHY_R
507+#endif /* CONFIG_CMD_NET */
508+
509+/*
510+ * SATA driver configuration
511+ */
512+#ifdef CONFIG_CMD_IDE
513+#define __io
514+#define CONFIG_IDE_PREINIT
515+#define CONFIG_DOS_PARTITION
516+#define CONFIG_MVSATA_IDE_USE_PORT0
517+#define CONFIG_MVSATA_IDE_USE_PORT1
518+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
519+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
520+#endif /* CONFIG_CMD_IDE */
521+
522+/*
523+ * RTC driver configuration
524+ */
525+#ifdef CONFIG_CMD_DATE
526+#define CONFIG_RTC_MV
527+#endif /* CONFIG_CMD_DATE */
528+
529+/*
530+ * File system
531+ */
532+#define CONFIG_CMD_EXT2
533+#define CONFIG_CMD_FAT
534+#define CONFIG_CMD_JFFS2
535+#define CONFIG_CMD_UBI
536+#define CONFIG_CMD_UBIFS
537+#define CONFIG_RBTREE
538+#define CONFIG_MTD_DEVICE
539+#define CONFIG_MTD_PARTITIONS
540+#define CONFIG_CMD_MTDPARTS
541+
542+#endif /* _CONFIG_IB62x0_H */
543

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