Root/package/uboot-xburst/patches/0001-add-qi_lb60-spl-code-and-usbboot-code.patch

1From eb328666f9381a1bd2059484a4aef024285be045 Mon Sep 17 00:00:00 2001
2From: Xiangfu Liu <xiangfu@openmobilefree.net>
3Date: Fri, 6 Jan 2012 17:05:11 +0800
4Subject: [PATCH 1/5] add qi_lb60 spl code and usbboot code
5
6---
7 arch/mips/cpu/xburst/Makefile | 7 +-
8 arch/mips/cpu/xburst/cpu.c | 4 +
9 arch/mips/cpu/xburst/jz4740.c | 84 ++--
10 arch/mips/cpu/xburst/spl/Makefile | 47 ++
11 arch/mips/cpu/xburst/spl/start.S | 65 +++
12 arch/mips/lib/Makefile | 4 +
13 arch/mips/lib/string.c | 32 ++
14 board/qi/qi_lb60/Makefile | 5 +
15 board/qi/qi_lb60/qi_lb60-spl.c | 56 +++
16 board/qi/qi_lb60/qi_lb60.c | 6 +-
17 board/qi/qi_lb60/u-boot-spl.lds | 62 +++
18 board/qi/qi_lb60/usbboot.S | 880 +++++++++++++++++++++++++++++++++++++
19 drivers/mtd/nand/jz4740_nand.c | 39 +-
20 include/configs/qi_lb60.h | 173 ++++----
21 14 files changed, 1319 insertions(+), 145 deletions(-)
22 create mode 100644 arch/mips/cpu/xburst/spl/Makefile
23 create mode 100644 arch/mips/cpu/xburst/spl/start.S
24 create mode 100644 arch/mips/lib/string.c
25 create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
26 create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
27 create mode 100644 board/qi/qi_lb60/usbboot.S
28
29diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
30index b1f2ae4..ec35e55 100644
31--- a/arch/mips/cpu/xburst/Makefile
32+++ b/arch/mips/cpu/xburst/Makefile
33@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
34 
35 LIB = $(obj)lib$(CPU).o
36 
37+COBJS-y = cpu.o jz_serial.o
38+
39+ifneq ($(CONFIG_SPL_BUILD),y)
40 START = start.o
41-SOBJS-y =
42-COBJS-y = cpu.o timer.o jz_serial.o
43+COBJS-y += timer.o
44+endif
45 
46 COBJS-$(CONFIG_JZ4740) += jz4740.o
47 
48diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
49index ddcbfaa..1432838 100644
50--- a/arch/mips/cpu/xburst/cpu.c
51+++ b/arch/mips/cpu/xburst/cpu.c
52@@ -42,6 +42,8 @@
53         : \
54         : "i" (op), "R" (*(unsigned char *)(addr)))
55 
56+#ifndef CONFIG_SPL_BUILD
57+
58 void __attribute__((weak)) _machine_restart(void)
59 {
60     struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
61@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
62         cache_op(Hit_Invalidate_D, addr);
63 }
64 
65+#endif
66+
67 void flush_icache_all(void)
68 {
69     u32 addr, t = 0;
70diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
71index c0b9817..40ef411 100644
72--- a/arch/mips/cpu/xburst/jz4740.c
73+++ b/arch/mips/cpu/xburst/jz4740.c
74@@ -32,31 +32,19 @@ int disable_interrupts(void)
75     return 0;
76 }
77 
78-/*
79- * PLL output clock = EXTAL * NF / (NR * NO)
80- * NF = FD + 2, NR = RD + 2
81- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
82- */
83 void pll_init(void)
84 {
85     struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
86 
87- register unsigned int cfcr, plcr1;
88- int n2FR[33] = {
89- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
90- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
91- 9
92- };
93- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
94- int nf, pllout2;
95+ register unsigned int cfcr, plcr;
96+ unsigned int nf, pllout2;
97 
98     cfcr = CPM_CPCCR_CLKOEN |
99- CPM_CPCCR_PCS |
100- (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
101- (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
102- (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
103- (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
104- (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
105+ (0 << CPM_CPCCR_CDIV_BIT) |
106+ (2 << CPM_CPCCR_HDIV_BIT) |
107+ (2 << CPM_CPCCR_PDIV_BIT) |
108+ (2 << CPM_CPCCR_MDIV_BIT) |
109+ (2 << CPM_CPCCR_LDIV_BIT);
110 
111     pllout2 = (cfcr & CPM_CPCCR_PCS) ?
112         CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
113@@ -65,15 +53,18 @@ void pll_init(void)
114     writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
115 
116     nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
117- plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
118+ plcr = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
119         (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
120         (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
121- (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
122+ (0x32 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
123         CPM_CPPCR_PLLEN; /* enable PLL */
124 
125     /* init PLL */
126     writel(cfcr, &cpm->cpccr);
127- writel(plcr1, &cpm->cppcr);
128+ writel(plcr, &cpm->cppcr);
129+
130+ while (!(readl(&cpm->cppcr) & CPM_CPPCR_PLLS))
131+ ;
132 }
133 
134 void sdram_init(void)
135@@ -92,26 +83,14 @@ void sdram_init(void)
136         2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
137     };
138 
139- int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
140+ unsigned int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
141 
142     cpu_clk = CONFIG_SYS_CPU_SPEED;
143- mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
144+ mem_clk = 84000000;
145 
146     writel(0, &emc->bcr); /* Disable bus release */
147     writew(0, &emc->rtcsr); /* Disable clock for counting */
148 
149- /* Fault DMCR value for mode register setting*/
150-#define SDRAM_ROW0 11
151-#define SDRAM_COL0 8
152-#define SDRAM_BANK40 0
153-
154- dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
155- ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
156- (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
157- (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
158- EMC_DMCR_EPIN |
159- cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
160-
161     /* Basic DMCR value */
162     dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
163         ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
164@@ -128,36 +107,36 @@ void sdram_init(void)
165     if (tmp > 11)
166         tmp = 11;
167     dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
168- tmp = SDRAM_RCD / ns;
169 
170+ tmp = SDRAM_RCD / ns;
171     if (tmp > 3)
172         tmp = 3;
173     dmcr |= tmp << EMC_DMCR_RCD_BIT;
174- tmp = SDRAM_TPC / ns;
175 
176+ tmp = SDRAM_TPC / ns;
177     if (tmp > 7)
178         tmp = 7;
179     dmcr |= tmp << EMC_DMCR_TPC_BIT;
180- tmp = SDRAM_TRWL / ns;
181 
182+ tmp = SDRAM_TRWL / ns;
183     if (tmp > 3)
184         tmp = 3;
185     dmcr |= tmp << EMC_DMCR_TRWL_BIT;
186- tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
187 
188+ tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
189     if (tmp > 14)
190         tmp = 14;
191     dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
192 
193     /* SDRAM mode value */
194- sdmode = EMC_SDMR_BT_SEQ |
195- EMC_SDMR_OM_NORMAL |
196- EMC_SDMR_BL_4 |
197+ sdmode = EMC_SDMR_BT_SEQ |
198+ EMC_SDMR_OM_NORMAL |
199+ EMC_SDMR_BL_4 |
200          cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
201 
202     /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
203     writel(dmcr, &emc->dmcr);
204- writeb(0, JZ4740_EMC_SDMR0 | sdmode);
205+ writeb(0, JZ4740_EMC_SDMR0 + sdmode);
206 
207     /* Wait for precharge, > 200us */
208     tmp = (cpu_clk / 1000000) * 1000;
209@@ -172,8 +151,8 @@ void sdram_init(void)
210     if (tmp > 0xff)
211         tmp = 0xff;
212     writew(tmp, &emc->rtcor);
213+
214     writew(0, &emc->rtcnt);
215- /* Divisor is 64, CKO/64 */
216     writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
217 
218     /* Wait for number of auto-refresh cycles */
219@@ -182,13 +161,17 @@ void sdram_init(void)
220         ;
221 
222     /* Stage 3. Mode Register Set */
223+ dmcr0 = (11 << EMC_DMCR_RA_BIT) |
224+ (8 << EMC_DMCR_CA_BIT) |
225+ (0 << EMC_DMCR_BA_BIT) |
226+ EMC_DMCR_EPIN |
227+ (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
228+ cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
229     writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
230     writeb(0, JZ4740_EMC_SDMR0 | sdmode);
231 
232     /* Set back to basic DMCR value */
233     writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
234-
235- /* everything is ok now */
236 }
237 
238 DECLARE_GLOBAL_DATA_PTR;
239@@ -232,9 +215,10 @@ void rtc_init(void)
240 phys_size_t initdram(int board_type)
241 {
242     struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
243- u32 dmcr;
244- u32 rows, cols, dw, banks;
245- ulong size;
246+
247+ unsigned int dmcr;
248+ unsigned int rows, cols, dw, banks;
249+ unsigned long size;
250 
251     dmcr = readl(&emc->dmcr);
252     rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
253diff --git a/arch/mips/cpu/xburst/spl/Makefile b/arch/mips/cpu/xburst/spl/Makefile
254new file mode 100644
255index 0000000..f45e8c8
256--- /dev/null
257+++ b/arch/mips/cpu/xburst/spl/Makefile
258@@ -0,0 +1,47 @@
259+#
260+# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
261+#
262+# See file CREDITS for list of people who contributed to this
263+# project.
264+#
265+# This program is free software; you can redistribute it and/or
266+# modify it under the terms of the GNU General Public License as
267+# published by the Free Software Foundation; either version 2 of
268+# the License, or (at your option) any later version.
269+#
270+# This program is distributed in the hope that it will be useful,
271+# but WITHOUT ANY WARRANTY; without even the implied warranty of
272+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
273+# GNU General Public License for more details.
274+#
275+# You should have received a copy of the GNU General Public License
276+# along with this program; if not, write to the Free Software
277+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
278+# MA 02111-1307 USA
279+#
280+
281+include $(TOPDIR)/config.mk
282+
283+LIB = $(obj)lib$(CPU).o
284+
285+START = start.o
286+SOBJS-y =
287+COBJS-y =
288+
289+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
290+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
291+START := $(addprefix $(obj),$(START))
292+
293+all: $(obj).depend $(START) $(LIB)
294+
295+$(LIB): $(OBJS)
296+ $(call cmd_link_o_target, $(OBJS))
297+
298+#########################################################################
299+
300+# defines $(obj).depend target
301+include $(SRCTREE)/rules.mk
302+
303+sinclude $(obj).depend
304+
305+#########################################################################
306diff --git a/arch/mips/cpu/xburst/spl/start.S b/arch/mips/cpu/xburst/spl/start.S
307new file mode 100644
308index 0000000..44dd1e0
309--- /dev/null
310+++ b/arch/mips/cpu/xburst/spl/start.S
311@@ -0,0 +1,65 @@
312+/*
313+ * Startup Code for MIPS32 XBURST CPU-core
314+ *
315+ * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
316+ *
317+ * See file CREDITS for list of people who contributed to this
318+ * project.
319+ *
320+ * This program is free software; you can redistribute it and/or
321+ * modify it under the terms of the GNU General Public License as
322+ * published by the Free Software Foundation; either version 3 of
323+ * the License, or (at your option) any later version.
324+ *
325+ * This program is distributed in the hope that it will be useful,
326+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
327+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
328+ * GNU General Public License for more details.
329+ *
330+ * You should have received a copy of the GNU General Public License
331+ * along with this program; if not, write to the Free Software
332+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
333+ * MA 02111-1307 USA
334+ */
335+
336+#include <config.h>
337+#include <version.h>
338+#include <asm/regdef.h>
339+#include <asm/mipsregs.h>
340+#include <asm/addrspace.h>
341+#include <asm/cacheops.h>
342+
343+#include <asm/jz4740.h>
344+
345+ .set noreorder
346+
347+ .globl _start
348+ .text
349+_start:
350+ .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
351+reset:
352+ /*
353+ * STATUS register
354+ * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
355+ */
356+ li t0, 0x0040FC04
357+ mtc0 t0, CP0_STATUS
358+ /*
359+ * CAUSE register
360+ * IV=1, use the specical interrupt vector (0x200)
361+ */
362+ li t1, 0x00800000
363+ mtc0 t1, CP0_CAUSE
364+
365+ bal 1f
366+ nop
367+ .word _GLOBAL_OFFSET_TABLE_
368+1:
369+ move gp, ra
370+ lw t1, 0(ra)
371+ move gp, t1
372+
373+ la sp, 0x80004000
374+ la t9, nand_spl_boot
375+ j t9
376+ nop
377diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
378index 967e98a..c1452a2 100644
379--- a/arch/mips/lib/Makefile
380+++ b/arch/mips/lib/Makefile
381@@ -34,12 +34,16 @@ LGOBJS := $(addprefix $(obj),$(GLSOBJS))
382 
383 SOBJS-y +=
384 
385+ifeq ($(CONFIG_SPL_BUILD),y)
386+COBJS-y += string.o
387+else
388 COBJS-y += board.o
389 ifeq ($(CONFIG_QEMU_MIPS),y)
390 COBJS-y += bootm_qemu_mips.o
391 else
392 COBJS-y += bootm.o
393 endif
394+endif
395 
396 SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
397 OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
398diff --git a/arch/mips/lib/string.c b/arch/mips/lib/string.c
399new file mode 100644
400index 0000000..d59f44a
401--- /dev/null
402+++ b/arch/mips/lib/string.c
403@@ -0,0 +1,32 @@
404+/*
405+ * Copyright (c) 2012 Xiangfu Liu <xiangfu@openmobilefree.net>
406+ *
407+ * See file CREDITS for list of people who contributed to this
408+ * project.
409+ *
410+ * This program is free software; you can redistribute it and/or
411+ * modify it under the terms of the GNU General Public License as
412+ * published by the Free Software Foundation; either version 2 of
413+ * the License, or (at your option) any later version.
414+ *
415+ * This program is distributed in the hope that it will be useful,
416+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
417+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
418+ * GNU General Public License for more details.
419+ *
420+ * You should have received a copy of the GNU General Public License
421+ * along with this program; if not, write to the Free Software
422+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
423+ * MA 02111-1307 USA
424+ */
425+
426+/* copy from lib/string bcopy */
427+char * memcpy(const char * src, char * dest, int count)
428+{
429+ char *tmp = dest;
430+
431+ while (count--)
432+ *tmp++ = *src++;
433+
434+ return dest;
435+}
436diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile
437index 5dae11b..6dd8c6f 100644
438--- a/board/qi/qi_lb60/Makefile
439+++ b/board/qi/qi_lb60/Makefile
440@@ -22,7 +22,12 @@ include $(TOPDIR)/config.mk
441 
442 LIB = $(obj)lib$(BOARD).o
443 
444+ifeq ($(CONFIG_SPL_BUILD),y)
445+SOBJS := usbboot.o
446+COBJS := $(BOARD)-spl.o
447+else
448 COBJS := $(BOARD).o
449+endif
450 
451 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
452 OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
453diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
454new file mode 100644
455index 0000000..f5031aa
456--- /dev/null
457+++ b/board/qi/qi_lb60/qi_lb60-spl.c
458@@ -0,0 +1,56 @@
459+/*
460+ * Authors: Xiangfu Liu <xiangfu@sharism.cc>
461+ *
462+ * This program is free software; you can redistribute it and/or
463+ * modify it under the terms of the GNU General Public License
464+ * as published by the Free Software Foundation; either version
465+ * 3 of the License, or (at your option) any later version.
466+ */
467+
468+#include <common.h>
469+#include <nand.h>
470+#include <asm/io.h>
471+#include <asm/jz4740.h>
472+
473+#define KEY_U_OUT (32 * 2 + 16)
474+#define KEY_U_IN (32 * 3 + 19)
475+
476+static int is_usb_boot()
477+{
478+ __gpio_as_input(KEY_U_IN);
479+ __gpio_enable_pull(KEY_U_IN);
480+ __gpio_as_output(KEY_U_OUT);
481+ __gpio_clear_pin(KEY_U_OUT);
482+
483+ if (__gpio_get_pin(KEY_U_IN) == 0)
484+ return 1;
485+
486+ return 0;
487+}
488+
489+static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
490+
491+void nand_spl_boot(void)
492+{
493+ uint32_t reg;
494+
495+ __gpio_as_sdram_16bit_4720();
496+ __gpio_as_uart0();
497+ __gpio_jtag_to_uart0();
498+
499+ serial_init();
500+ serial_puts("\nQi lb60 SPL\n");
501+
502+ pll_init();
503+ sdram_init();
504+
505+ if (is_usb_boot()) {
506+ serial_puts("[U] pressed, goto USBBOOT mode\n");
507+ usb_boot();
508+ }
509+
510+ nand_init();
511+
512+ serial_puts("\nStarting U-Boot ...\n");
513+ nand_boot();
514+}
515diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c
516index d975209..553e05d 100644
517--- a/board/qi/qi_lb60/qi_lb60.c
518+++ b/board/qi/qi_lb60/qi_lb60.c
519@@ -97,8 +97,10 @@ int board_early_init_f(void)
520 /* U-Boot common routines */
521 int checkboard(void)
522 {
523- printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
524- gd->cpu_clk / 1000000);
525+ printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC)\n");
526+ printf(" CPU: %ld \n", gd->cpu_clk);
527+ printf(" MEM: %ld \n", gd->mem_clk);
528+ printf(" DEV: %ld \n", gd->dev_clk);
529 
530     return 0;
531 }
532diff --git a/board/qi/qi_lb60/u-boot-spl.lds b/board/qi/qi_lb60/u-boot-spl.lds
533new file mode 100644
534index 0000000..cf80c35
535--- /dev/null
536+++ b/board/qi/qi_lb60/u-boot-spl.lds
537@@ -0,0 +1,62 @@
538+/*
539+ * (C) Copyright 2005
540+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
541+ *
542+ * This program is free software; you can redistribute it and/or
543+ * modify it under the terms of the GNU General Public License as
544+ * published by the Free Software Foundation; either version 2 of
545+ * the License, or (at your option) any later version.
546+ *
547+ * This program is distributed in the hope that it will be useful,
548+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
549+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
550+ * GNU General Public License for more details.
551+ *
552+ * You should have received a copy of the GNU General Public License
553+ * along with this program; if not, write to the Free Software
554+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
555+ * MA 02111-1307 USA
556+ */
557+
558+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
559+
560+OUTPUT_ARCH(mips)
561+ENTRY(_start)
562+SECTIONS
563+{
564+ . = 0x80000000;
565+ . = ALIGN(4);
566+ .text :
567+ {
568+ *(.text)
569+ }
570+
571+ . = ALIGN(4);
572+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
573+
574+ . = ALIGN(4);
575+ .data : { *(.data) }
576+
577+ . = ALIGN(4);
578+ .sdata : { *(.sdata) }
579+
580+ _gp = ALIGN(16);
581+
582+ __got_start = .;
583+ .got : { *(.got) }
584+ __got_end = .;
585+
586+ . = .;
587+ __u_boot_cmd_start = .;
588+ .u_boot_cmd : { *(.u_boot_cmd) }
589+ __u_boot_cmd_end = .;
590+
591+ uboot_end_data = .;
592+ num_got_entries = (__got_end - __got_start) >> 2;
593+
594+ . = ALIGN(4);
595+ .sbss : { *(.sbss) }
596+ .bss : { *(.bss) }
597+ uboot_end = .;
598+}
599+ASSERT(uboot_end <= 0x80002000, "NAND bootstrap too big");
600diff --git a/board/qi/qi_lb60/usbboot.S b/board/qi/qi_lb60/usbboot.S
601new file mode 100644
602index 0000000..eb8faa6
603--- /dev/null
604+++ b/board/qi/qi_lb60/usbboot.S
605@@ -0,0 +1,880 @@
606+/*
607+ * for jz4740 usb boot
608+ *
609+ * Copyright (c) 2009 Author: <jlwei@ingenic.cn>
610+ *
611+ * See file CREDITS for list of people who contributed to this
612+ * project.
613+ *
614+ * This program is free software; you can redistribute it and/or
615+ * modify it under the terms of the GNU General Public License as
616+ * published by the Free Software Foundation; either version 2 of
617+ * the License, or (at your option) any later version.
618+ *
619+ * This program is distributed in the hope that it will be useful,
620+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
621+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
622+ * GNU General Public License for more details.
623+ *
624+ * You should have received a copy of the GNU General Public License
625+ * along with this program; if not, write to the Free Software
626+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
627+ * MA 02111-1307 USA
628+ */
629+ .set noreorder
630+ .globl usb_boot
631+ .text
632+
633+//----------------------------------------------------------------------
634+// Both NAND and USB boot load data to D-Cache first, then transfer
635+// data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
636+// So init caches first and then dispatch to a proper boot routine.
637+//----------------------------------------------------------------------
638+
639+.macro load_addr reg addr
640+ li \reg, 0x80000000
641+ addiu \reg, \reg, \addr
642+ la $2, usbboot_begin
643+ subu \reg, \reg, $2
644+.endm
645+
646+usb_boot:
647+ //--------------------------------------------------------------
648+ // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
649+ //--------------------------------------------------------------
650+ la $9, 0xB0000000 // CPCCR: Clock Control Register
651+ la $8, 0x42041110 // I:S:M:P=1:2:2:2
652+ sw $8, 0($9)
653+
654+ la $9, 0xB0000010 // CPPCR: PLL Control Register
655+ la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
656+ sw $8, 0($9)
657+
658+ mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
659+ nop
660+
661+ mtc0 $0, $16 // CP0_CONFIG
662+ nop
663+
664+ // Relocate code to beginning of the ram
665+
666+ la $2, usbboot_begin
667+ la $3, usbboot_end
668+ li $4, 0x80000000
669+
670+1:
671+ lw $5, 0($2)
672+ sw $5, 0($4)
673+ addiu $2, $2, 4
674+ bne $2, $3, 1b
675+ addiu $4, $4, 4
676+
677+ li $2, 0x80000000
678+ ori $3, $2, 0
679+ addiu $3, $3, usbboot_end
680+ la $4, usbboot_begin
681+ subu $3, $3, $4
682+
683+
684+2:
685+ cache 0x0, 0($2) // Index_Invalidate_I
686+ cache 0x1, 0($2) // Index_Writeback_Inv_D
687+ addiu $2, $2, 32
688+ subu $4, $3, $2
689+ bgtz $4, 2b
690+ nop
691+
692+ load_addr $3, usb_boot_return
693+
694+ jr $3
695+
696+usbboot_begin:
697+
698+init_caches:
699+ li $2, 3 // cacheable for kseg0 access
700+ mtc0 $2, $16 // CP0_CONFIG
701+ nop
702+
703+ li $2, 0x20000000 // enable idx-store-data cache insn
704+ mtc0 $2, $26 // CP0_ERRCTL
705+
706+ ori $2, $28, 0 // start address
707+ ori $3, $2, 0x3fe0 // end address, total 16KB
708+ mtc0 $0, $28, 0 // CP0_TAGLO
709+ mtc0 $0, $28, 1 // CP0_DATALO
710+cache_clear_a_line:
711+ cache 0x8, 0($2) // Index_Store_Tag_I
712+ cache 0x9, 0($2) // Index_Store_Tag_D
713+ bne $2, $3, cache_clear_a_line
714+ addiu $2, $2, 32 // increment CACHE_LINE_SIZE
715+
716+ ori $2, $28, 0 // start address
717+ ori $3, $2, 0x3fe0 // end address, total 16KB
718+ la $4, 0x1ffff000 // physical address and 4KB page mask
719+cache_alloc_a_line:
720+ and $5, $2, $4
721+ ori $5, $5, 1 // V bit of the physical tag
722+ mtc0 $5, $28, 0 // CP0_TAGLO
723+ cache 0x8, 0($2) // Index_Store_Tag_I
724+ cache 0x9, 0($2) // Index_Store_Tag_D
725+ bne $2, $3, cache_alloc_a_line
726+ addiu $2, $2, 32 // increment CACHE_LINE_SIZE
727+
728+ nop
729+ nop
730+ nop
731+ //--------------------------------------------------------------
732+ // Transfer data from dcache to icache, then jump to icache.
733+ //
734+ // Input parameters:
735+ //
736+ // $19: data length in bytes
737+ // $20: jump target address
738+ //--------------------------------------------------------------
739+xfer_d2i:
740+
741+ ori $8, $20, 0
742+ addu $9, $8, $19 // total 16KB
743+
744+1:
745+ cache 0x0, 0($8) // Index_Invalidate_I
746+ cache 0x1, 0($8) // Index_Writeback_Inv_D
747+ bne $8, $9, 1b
748+ addiu $8, $8, 32
749+
750+ // flush write-buffer
751+ sync
752+
753+ // Invalidate BTB
754+ mfc0 $8, $16, 7 // CP0_CONFIG
755+ nop
756+ ori $8, 2
757+ mtc0 $8, $16, 7
758+ nop
759+
760+ // Overwrite config to disable ram initalisation
761+ li $2, 0xff
762+ sb $2, 20($20)
763+
764+ jalr $20
765+ nop
766+
767+icache_return:
768+ //--------------------------------------------------------------
769+ // User code can return to here after executing itself in
770+ // icache, by jumping to $31.
771+ //--------------------------------------------------------------
772+ b usb_boot_return
773+ nop
774+
775+
776+usb_boot_return:
777+ //--------------------------------------------------------------
778+ // Enable the USB PHY
779+ //--------------------------------------------------------------
780+ la $9, 0xB0000024 // CPM_SCR
781+ lw $8, 0($9)
782+ ori $8, 0x40 // USBPHY_ENABLE
783+ sw $8, 0($9)
784+
785+ //--------------------------------------------------------------
786+ // Initialize USB registers
787+ //--------------------------------------------------------------
788+ la $27, 0xb3040000 // USB registers base address
789+
790+ sb $0, 0x0b($27) // INTRUSBE: disable common USB interrupts
791+ sh $0, 0x06($27) // INTRINE: disable EPIN interrutps
792+ sh $0, 0x08($27) // INTROUTE: disable EPOUT interrutps
793+
794+ li $9, 0x61
795+ sb $9, 0x01($27) // POWER: HSENAB | SUSPENDM | SOFTCONN
796+
797+ //--------------------------------------------------------------
798+ // Initialize USB states
799+ //--------------------------------------------------------------
800+ li $22, 0 // set EP0 to IDLE state
801+ li $23, 1 // no data stage
802+
803+ //--------------------------------------------------------------
804+ // Main loop of polling the usb commands
805+ //--------------------------------------------------------------
806+usb_command_loop:
807+ lbu $9, 0x0a($27) // read INTRUSB
808+ andi $9, 0x04 // check USB_INTR_RESET
809+ beqz $9, check_intr_ep0in
810+ nop
811+
812+ //--------------------------------------------------------------
813+ // 1. Handle USB reset interrupt
814+ //--------------------------------------------------------------
815+handle_reset_intr:
816+ lbu $9, 0x01($27) // read POWER
817+ andi $9, 0x10 // test HS_MODE
818+ bnez $9, _usb_set_maxpktsize
819+ li $9, 512 // max packet size of HS mode
820+ li $9, 64 // max packet size of FS mode
821+
822+_usb_set_maxpktsize:
823+ li $8, 1
824+ sb $8, 0x0e($27) // set INDEX 1
825+
826+ sh $9, 0x10($27) // INMAXP
827+ sb $0, 0x13($27) // INCSRH
828+ sh $9, 0x14($27) // OUTMAXP
829+ sb $0, 0x17($27) // OUTCSRH
830+
831+_usb_flush_fifo:
832+ li $8, 0x48 // INCSR_CDT && INCSR_FF
833+ sb $8, 0x12($27) // INCSR
834+ li $8, 0x90 // OUTCSR_CDT && OUTCSR_FF
835+ sb $8, 0x16($27) // OUTCSR
836+
837+ li $22, 0 // set EP0 to IDLE state
838+ li $23, 1 // no data stage
839+
840+ //--------------------------------------------------------------
841+ // 2. Check and handle EP0 interrupt
842+ //--------------------------------------------------------------
843+check_intr_ep0in:
844+ lhu $10, 0x02($27) // read INTRIN
845+ andi $9, $10, 0x1 // check EP0 interrupt
846+ beqz $9, check_intr_ep1in
847+ nop
848+
849+handle_ep0_intr:
850+ sb $0, 0x0e($27) // set INDEX 0
851+ lbu $11, 0x12($27) // read CSR0
852+
853+ andi $9, $11, 0x04 // check SENTSTALL
854+ beqz $9, _ep0_setupend
855+ nop
856+
857+_ep0_sentstall:
858+ andi $9, $11, 0xdb
859+ sb $9, 0x12($27) // clear SENDSTALL and SENTSTALL
860+ li $22, 0 // set EP0 to IDLE state
861+
862+_ep0_setupend:
863+ andi $9, $11, 0x10 // check SETUPEND
864+ beqz $9, ep0_idle_state
865+ nop
866+
867+ ori $9, $11, 0x80
868+ sb $9, 0x12($27) // set SVDSETUPEND
869+ li $22, 0 // set EP0 to IDLE state
870+
871+ep0_idle_state:
872+ bnez $22, ep0_tx_state
873+ nop
874+
875+ //--------------------------------------------------------------
876+ // 2.1 Handle EP0 IDLE state interrupt
877+ //--------------------------------------------------------------
878+ andi $9, $11, 0x01 // check OUTPKTRDY
879+ beqz $9, check_intr_ep1in
880+ nop
881+
882+ //--------------------------------------------------------------
883+ // Read 8-bytes setup packet from the FIFO
884+ //--------------------------------------------------------------
885+ lw $25, 0x20($27) // first word of setup packet
886+ lw $26, 0x20($27) // second word of setup packet
887+
888+ andi $9, $25, 0x60 // bRequestType & USB_TYPE_MASK
889+ beqz $9, _ep0_std_req
890+ nop
891+
892+ //--------------------------------------------------------------
893+ // 2.1.1 Vendor-specific setup request
894+ //--------------------------------------------------------------
895+_ep0_vend_req:
896+ li $22, 0 // set EP0 to IDLE state
897+ li $23, 1 // NoData = 1
898+
899+ andi $9, $25, 0xff00 // check bRequest
900+ srl $9, $9, 8
901+ beqz $9, __ep0_get_cpu_info
902+ sub $8, $9, 0x1
903+ beqz $8, __ep0_set_data_address
904+ sub $8, $9, 0x2
905+ beqz $8, __ep0_set_data_length
906+ sub $8, $9, 0x3
907+ beqz $8, __ep0_flush_caches
908+ sub $8, $9, 0x4
909+ beqz $8, __ep0_prog_start1
910+ sub $8, $9, 0x5
911+ beqz $8, __ep0_prog_start2
912+ nop
913+ b _ep0_idle_state_fini // invalid request
914+ nop
915+
916+__ep0_get_cpu_info:
917+ load_addr $20, cpu_info_data // data pointer to transfer
918+ li $21, 8 // bytes left to transfer
919+ li $22, 1 // set EP0 to TX state
920+ li $23, 0 // NoData = 0
921+
922+ b _ep0_idle_state_fini
923+ nop
924+
925+__ep0_set_data_address:
926+ li $9, 0xffff0000
927+ and $9, $25, $9
928+ andi $8, $26, 0xffff
929+ or $20, $9, $8 // data address of next transfer
930+
931+ b _ep0_idle_state_fini
932+ nop
933+
934+__ep0_set_data_length:
935+ li $9, 0xffff0000
936+ and $9, $25, $9
937+ andi $8, $26, 0xffff
938+ or $21, $9, $8 // data length of next transfer
939+
940+ li $9, 0x48 // SVDOUTPKTRDY and DATAEND
941+ sb $9, 0x12($27) // CSR0
942+
943+ // We must write packet to FIFO before EP1-IN interrupt here.
944+ b handle_epin1_intr
945+ nop
946+
947+__ep0_flush_caches:
948+ // Flush dcache and invalidate icache.
949+ li $8, 0x80000000
950+ addi $9, $8, 0x3fe0 // total 16KB
951+
952+1:
953+ cache 0x0, 0($8) // Index_Invalidate_I
954+ cache 0x1, 0($8) // Index_Writeback_Inv_D
955+ bne $8, $9, 1b
956+ addiu $8, $8, 32
957+
958+ // flush write-buffer
959+ sync
960+
961+ // Invalidate BTB
962+ mfc0 $8, $16, 7 // CP0_CONFIG
963+ nop
964+ ori $8, 2
965+ mtc0 $8, $16, 7
966+ nop
967+
968+ b _ep0_idle_state_fini
969+ nop
970+
971+__ep0_prog_start1:
972+ li $9, 0x48 // SVDOUTPKTRDY and DATAEND
973+ sb $9, 0x12($27) // CSR0
974+
975+ li $9, 0xffff0000
976+ and $9, $25, $9
977+ andi $8, $26, 0xffff
978+ or $20, $9, $8 // target address
979+
980+ b xfer_d2i
981+ li $19, 0x2000 // 16KB data length
982+
983+__ep0_prog_start2:
984+ li $9, 0x48 // SVDOUTPKTRDY and DATAEND
985+ sb $9, 0x12($27) // CSR0
986+
987+ li $9, 0xffff0000
988+ and $9, $25, $9
989+ andi $8, $26, 0xffff
990+ or $20, $9, $8 // target address
991+
992+ jalr $20 // jump, and place the return address in $31
993+ nop
994+
995+__ep0_prog_start2_return:
996+ // User code can return to here after executing itself, by jumping to $31.
997+ b usb_boot_return
998+ nop
999+
1000+ //--------------------------------------------------------------
1001+ // 2.1.2 Standard setup request
1002+ //--------------------------------------------------------------
1003+_ep0_std_req:
1004+ andi $12, $25, 0xff00 // check bRequest
1005+ srl $12, $12, 8
1006+ sub $9, $12, 0x05 // check USB_REQ_SET_ADDRESS
1007+ bnez $9, __ep0_req_set_config
1008+ nop
1009+
1010+ //--------------------------------------------------------------
1011+ // Handle USB_REQ_SET_ADDRESS
1012+ //--------------------------------------------------------------
1013+__ep0_req_set_addr:
1014+ srl $9, $25, 16 // get wValue
1015+ sb $9, 0x0($27) // set FADDR
1016+ li $23, 1 // NoData = 1
1017+ b _ep0_idle_state_fini
1018+ nop
1019+
1020+__ep0_req_set_config:
1021+ sub $9, $12, 0x09 // check USB_REQ_SET_CONFIGURATION
1022+ bnez $9, __ep0_req_get_desc
1023+ nop
1024+
1025+ //--------------------------------------------------------------
1026+ // Handle USB_REQ_SET_CONFIGURATION
1027+ //--------------------------------------------------------------
1028+ li $23, 1 // NoData = 1
1029+ b _ep0_idle_state_fini
1030+ nop
1031+
1032+__ep0_req_get_desc:
1033+ sub $9, $12, 0x06 // check USB_REQ_GET_DESCRIPTOR
1034+ bnez $9, _ep0_idle_state_fini
1035+ li $23, 1 // NoData = 1
1036+
1037+ //--------------------------------------------------------------
1038+ // Handle USB_REQ_GET_DESCRIPTOR
1039+ //--------------------------------------------------------------
1040+ li $23, 0 // NoData = 0
1041+
1042+ srl $9, $25, 24 // wValue >> 8
1043+ sub $8, $9, 0x01 // check USB_DT_DEVICE
1044+ beqz $8, ___ep0_get_dev_desc
1045+ srl $21, $26, 16 // get wLength
1046+ sub $8, $9, 0x02 // check USB_DT_CONFIG
1047+ beqz $8, ___ep0_get_conf_desc
1048+ sub $8, $9, 0x03 // check USB_DT_STRING
1049+ beqz $8, ___ep0_get_string_desc
1050+ sub $8, $9, 0x06 // check USB_DT_DEVICE_QUALIFIER
1051+ beqz $8, ___ep0_get_dev_qualifier
1052+ nop
1053+ b _ep0_idle_state_fini
1054+ nop
1055+
1056+___ep0_get_dev_desc:
1057+ load_addr $20, device_desc // data pointer
1058+ li $22, 1 // set EP0 to TX state
1059+ sub $8, $21, 18
1060+ blez $8, _ep0_idle_state_fini // wLength <= 18
1061+ nop
1062+ li $21, 18 // max length of device_desc
1063+ b _ep0_idle_state_fini
1064+ nop
1065+
1066+___ep0_get_dev_qualifier:
1067+ load_addr $20, dev_qualifier // data pointer
1068+ li $22, 1 // set EP0 to TX state
1069+ sub $8, $21, 10
1070+ blez $8, _ep0_idle_state_fini // wLength <= 10
1071+ nop
1072+ li $21, 10 // max length of dev_qualifier
1073+ b _ep0_idle_state_fini
1074+ nop
1075+
1076+___ep0_get_conf_desc:
1077+ load_addr $20, config_desc_fs // data pointer of FS mode
1078+ lbu $8, 0x01($27) // read POWER
1079+ andi $8, 0x10 // test HS_MODE
1080+ beqz $8, ___ep0_get_conf_desc2
1081+ nop
1082+ load_addr $20, config_desc_hs // data pointer of HS mode
1083+
1084+___ep0_get_conf_desc2:
1085+ li $22, 1 // set EP0 to TX state
1086+ sub $8, $21, 32
1087+ blez $8, _ep0_idle_state_fini // wLength <= 32
1088+ nop
1089+ li $21, 32 // max length of config_desc
1090+ b _ep0_idle_state_fini
1091+ nop
1092+
1093+___ep0_get_string_desc:
1094+ li $22, 1 // set EP0 to TX state
1095+
1096+ srl $9, $25, 16 // wValue & 0xff
1097+ andi $9, 0xff
1098+
1099+ sub $8, $9, 1
1100+ beqz $8, ___ep0_get_string_manufacture
1101+ sub $8, $9, 2
1102+ beqz $8, ___ep0_get_string_product
1103+ nop
1104+
1105+___ep0_get_string_lang_ids:
1106+ load_addr $20, string_lang_ids // data pointer
1107+ b _ep0_idle_state_fini
1108+ li $21, 4 // data length
1109+
1110+___ep0_get_string_manufacture:
1111+ load_addr $20, string_manufacture // data pointer
1112+ b _ep0_idle_state_fini
1113+ li $21, 16 // data length
1114+
1115+___ep0_get_string_product:
1116+ load_addr $20, string_product // data pointer
1117+ b _ep0_idle_state_fini
1118+ li $21, 46 // data length
1119+
1120+_ep0_idle_state_fini:
1121+ li $9, 0x40 // SVDOUTPKTRDY
1122+ beqz $23, _ep0_idle_state_fini2
1123+ nop
1124+ ori $9, $9, 0x08 // DATAEND
1125+_ep0_idle_state_fini2:
1126+ sb $9, 0x12($27) // CSR0
1127+ beqz $22, check_intr_ep1in
1128+ nop
1129+
1130+ //--------------------------------------------------------------
1131+ // 2.2 Handle EP0 TX state interrupt
1132+ //--------------------------------------------------------------
1133+ep0_tx_state:
1134+ sub $9, $22, 1
1135+ bnez $9, check_intr_ep1in
1136+ nop
1137+
1138+ sub $9, $21, 64 // max packetsize
1139+ blez $9, _ep0_tx_state2 // data count <= 64
1140+ ori $19, $21, 0
1141+ li $19, 64
1142+
1143+_ep0_tx_state2:
1144+ beqz $19, _ep0_tx_state3 // send ZLP
1145+ ori $18, $19, 0 // record bytes to be transferred
1146+ sub $21, $21, $19 // decrement data count
1147+
1148+_ep0_fifo_write_loop:
1149+ lbu $9, 0($20) // read data
1150+ sb $9, 0x20($27) // load FIFO
1151+ sub $19, $19, 1 // decrement counter
1152+ bnez $19, _ep0_fifo_write_loop
1153+ addi $20, $20, 1 // increment data pointer
1154+
1155+ sub $9, $18, 64 // max packetsize
1156+ beqz $9, _ep0_tx_state4
1157+ nop
1158+
1159+_ep0_tx_state3:
1160+ // transferred bytes < max packetsize
1161+ li $9, 0x0a // set INPKTRDY and DATAEND
1162+ sb $9, 0x12($27) // CSR0
1163+ li $22, 0 // set EP0 to IDLE state
1164+ b check_intr_ep1in
1165+ nop
1166+
1167+_ep0_tx_state4:
1168+ // transferred bytes == max packetsize
1169+ li $9, 0x02 // set INPKTRDY
1170+ sb $9, 0x12($27) // CSR0
1171+ b check_intr_ep1in
1172+ nop
1173+
1174+ //--------------------------------------------------------------
1175+ // 3. Check and handle EP1 BULK-IN interrupt
1176+ //--------------------------------------------------------------
1177+check_intr_ep1in:
1178+ andi $9, $10, 0x2 // check EP1 IN interrupt
1179+ beqz $9, check_intr_ep1out
1180+ nop
1181+
1182+handle_epin1_intr:
1183+ li $9, 1
1184+ sb $9, 0x0e($27) // set INDEX 1
1185+ lbu $9, 0x12($27) // read INCSR
1186+
1187+ andi $8, $9, 0x2 // check INCSR_FFNOTEMPT
1188+ bnez $8, _epin1_tx_state4
1189+ nop
1190+
1191+_epin1_write_fifo:
1192+ lhu $9, 0x10($27) // get INMAXP
1193+ sub $8, $21, $9
1194+ blez $8, _epin1_tx_state1 // bytes left <= INMAXP
1195+ ori $19, $21, 0
1196+ ori $19, $9, 0
1197+
1198+_epin1_tx_state1:
1199+ beqz $19, _epin1_tx_state4 // No data
1200+ nop
1201+
1202+ sub $21, $21, $19 // decrement data count
1203+
1204+ srl $5, $19, 2 // # of word
1205+ andi $6, $19, 0x3 // # of byte
1206+ beqz $5, _epin1_tx_state2
1207+ nop
1208+
1209+_epin1_fifo_write_word:
1210+ lw $9, 0($20) // read data from source address
1211+ sw $9, 0x24($27) // write FIFO
1212+ sub $5, $5, 1 // decrement counter
1213+ bnez $5, _epin1_fifo_write_word
1214+ addiu $20, $20, 4 // increment dest address
1215+
1216+_epin1_tx_state2:
1217+ beqz $6, _epin1_tx_state3
1218+ nop
1219+
1220+_epin1_fifo_write_byte:
1221+ lbu $9, 0($20) // read data from source address
1222+ sb $9, 0x24($27) // write FIFO
1223+ sub $6, $6, 1 // decrement counter
1224+ bnez $6, _epin1_fifo_write_byte
1225+ addiu $20, $20, 1 // increment dest address
1226+
1227+_epin1_tx_state3:
1228+ li $9, 0x1
1229+ sb $9, 0x12($27) // INCSR, set INPKTRDY
1230+
1231+_epin1_tx_state4:
1232+ // nop
1233+
1234+ //--------------------------------------------------------------
1235+ // 4. Check and handle EP1 BULK-OUT interrupt
1236+ //--------------------------------------------------------------
1237+check_intr_ep1out:
1238+ lhu $9, 0x04($27) // read INTROUT
1239+ andi $9, 0x2
1240+ beqz $9, check_status_next
1241+ nop
1242+
1243+handle_epout1_intr:
1244+ li $9, 1
1245+ sb $9, 0x0e($27) // set INDEX 1
1246+
1247+ lbu $9, 0x16($27) // read OUTCSR
1248+ andi $9, 0x1 // check OUTPKTRDY
1249+ beqz $9, check_status_next
1250+ nop
1251+
1252+_epout1_read_fifo:
1253+ lhu $19, 0x18($27) // read OUTCOUNT
1254+ srl $5, $19, 2 // # of word
1255+ andi $6, $19, 0x3 // # of byte
1256+ beqz $5, _epout1_rx_state1
1257+ nop
1258+
1259+_epout1_fifo_read_word:
1260+ lw $9, 0x24($27) // read FIFO
1261+ sw $9, 0($20) // store to dest address
1262+ sub $5, $5, 1 // decrement counter
1263+ bnez $5, _epout1_fifo_read_word
1264+ addiu $20, $20, 4 // increment dest address
1265+
1266+_epout1_rx_state1:
1267+ beqz $6, _epout1_rx_state2
1268+ nop
1269+
1270+_epout1_fifo_read_byte:
1271+ lbu $9, 0x24($27) // read FIFO
1272+ sb $9, 0($20) // store to dest address
1273+ sub $6, $6, 1 // decrement counter
1274+ bnez $6, _epout1_fifo_read_byte
1275+ addiu $20, $20, 1 // increment dest address
1276+
1277+_epout1_rx_state2:
1278+ sb $0, 0x16($27) // clear OUTPKTRDY
1279+
1280+check_status_next:
1281+ b usb_command_loop
1282+ nop
1283+
1284+//--------------------------------------------------------------
1285+// Device/Configuration/Interface/Endpoint/String Descriptors
1286+//--------------------------------------------------------------
1287+
1288+ .align 2
1289+device_desc:
1290+ .byte 0x12 // bLength
1291+ .byte 0x01 // bDescriptorType
1292+ .byte 0x00 // bcdUSB
1293+ .byte 0x02 // bcdUSB
1294+ .byte 0x00 // bDeviceClass
1295+ .byte 0x00 // bDeviceSubClass
1296+ .byte 0x00 // bDeviceProtocol
1297+ .byte 0x40 // bMaxPacketSize0
1298+ .byte 0x1a // idVendor
1299+ .byte 0x60 // idVendor
1300+ .byte 0x40 // idProduct
1301+ .byte 0x47 // idProduct
1302+ .byte 0x00 // bcdDevice
1303+ .byte 0x01 // bcdDevice
1304+ .byte 0x01 // iManufacturer
1305+ .byte 0x02 // iProduct
1306+ .byte 0x00 // iSerialNumber
1307+ .byte 0x01 // bNumConfigurations
1308+
1309+ .align 2
1310+dev_qualifier:
1311+ .byte 0x0a // bLength
1312+ .byte 0x06 // bDescriptorType
1313+ .byte 0x00 // bcdUSB
1314+ .byte 0x02 // bcdUSB
1315+ .byte 0x00 // bDeviceClass
1316+ .byte 0x00 // bDeviceSubClass
1317+ .byte 0x00 // bDeviceProtocol
1318+ .byte 0x40 // bMaxPacketSize0
1319+ .byte 0x01 // bNumConfigurations
1320+ .byte 0x00 // bRESERVED
1321+
1322+ .align 2
1323+config_desc_hs:
1324+ .byte 0x09 // bLength
1325+ .byte 0x02 // bDescriptorType
1326+ .byte 0x20 // wTotalLength
1327+ .byte 0x00 // wTotalLength
1328+ .byte 0x01 // bNumInterfaces
1329+ .byte 0x01 // bConfigurationValue
1330+ .byte 0x00 // iConfiguration
1331+ .byte 0xc0 // bmAttributes
1332+ .byte 0x01 // MaxPower
1333+intf_desc_hs:
1334+ .byte 0x09 // bLength
1335+ .byte 0x04 // bDescriptorType
1336+ .byte 0x00 // bInterfaceNumber
1337+ .byte 0x00 // bAlternateSetting
1338+ .byte 0x02 // bNumEndpoints
1339+ .byte 0xff // bInterfaceClass
1340+ .byte 0x00 // bInterfaceSubClass
1341+ .byte 0x50 // bInterfaceProtocol
1342+ .byte 0x00 // iInterface
1343+ep1_desc_hs:
1344+ .byte 0x07 // bLength
1345+ .byte 0x05 // bDescriptorType
1346+ .byte 0x01 // bEndpointAddress
1347+ .byte 0x02 // bmAttributes
1348+ .byte 0x00 // wMaxPacketSize
1349+ .byte 0x02 // wMaxPacketSize
1350+ .byte 0x00 // bInterval
1351+ep2_desc_hs:
1352+ .byte 0x07 // bLength
1353+ .byte 0x05 // bDescriptorType
1354+ .byte 0x81 // bEndpointAddress
1355+ .byte 0x02 // bmAttributes
1356+ .byte 0x00 // wMaxPacketSize
1357+ .byte 0x02 // wMaxPacketSize
1358+ .byte 0x00 // bInterval
1359+
1360+ .align 2
1361+config_desc_fs:
1362+ .byte 0x09 // bLength
1363+ .byte 0x02 // bDescriptorType
1364+ .byte 0x20 // wTotalLength
1365+ .byte 0x00 // wTotalLength
1366+ .byte 0x01 // bNumInterfaces
1367+ .byte 0x01 // bConfigurationValue
1368+ .byte 0x00 // iConfiguration
1369+ .byte 0xc0 // bmAttributes
1370+ .byte 0x01 // MaxPower
1371+intf_desc_fs:
1372+ .byte 0x09 // bLength
1373+ .byte 0x04 // bDescriptorType
1374+ .byte 0x00 // bInterfaceNumber
1375+ .byte 0x00 // bAlternateSetting
1376+ .byte 0x02 // bNumEndpoints
1377+ .byte 0xff // bInterfaceClass
1378+ .byte 0x00 // bInterfaceSubClass
1379+ .byte 0x50 // bInterfaceProtocol
1380+ .byte 0x00 // iInterface
1381+ep1_desc_fs:
1382+ .byte 0x07 // bLength
1383+ .byte 0x05 // bDescriptorType
1384+ .byte 0x01 // bEndpointAddress
1385+ .byte 0x02 // bmAttributes
1386+ .byte 0x40 // wMaxPacketSize
1387+ .byte 0x00 // wMaxPacketSize
1388+ .byte 0x00 // bInterval
1389+ep2_desc_fs:
1390+ .byte 0x07 // bLength
1391+ .byte 0x05 // bDescriptorType
1392+ .byte 0x81 // bEndpointAddress
1393+ .byte 0x02 // bmAttributes
1394+ .byte 0x40 // wMaxPacketSize
1395+ .byte 0x00 // wMaxPacketSize
1396+ .byte 0x00 // bInterval
1397+
1398+ .align 2
1399+string_lang_ids:
1400+ .byte 0x04
1401+ .byte 0x03
1402+ .byte 0x09
1403+ .byte 0x04
1404+
1405+ .align 2
1406+string_manufacture:
1407+ .byte 0x10
1408+ .byte 0x03
1409+ .byte 0x49
1410+ .byte 0x00
1411+ .byte 0x6e
1412+ .byte 0x00
1413+ .byte 0x67
1414+ .byte 0x00
1415+ .byte 0x65
1416+ .byte 0x00
1417+ .byte 0x6e
1418+ .byte 0x00
1419+ .byte 0x69
1420+ .byte 0x00
1421+ .byte 0x63
1422+ .byte 0x00
1423+
1424+ .align 2
1425+string_product:
1426+ .byte 0x2e
1427+ .byte 0x03
1428+ .byte 0x4a
1429+ .byte 0x00
1430+ .byte 0x5a
1431+ .byte 0x00
1432+ .byte 0x34
1433+ .byte 0x00
1434+ .byte 0x37
1435+ .byte 0x00
1436+ .byte 0x34
1437+ .byte 0x00
1438+ .byte 0x30
1439+ .byte 0x00
1440+ .byte 0x20
1441+ .byte 0x00
1442+ .byte 0x55
1443+ .byte 0x00
1444+ .byte 0x53
1445+ .byte 0x00
1446+ .byte 0x42
1447+ .byte 0x00
1448+ .byte 0x20
1449+ .byte 0x00
1450+ .byte 0x42
1451+ .byte 0x00
1452+ .byte 0x6f
1453+ .byte 0x00
1454+ .byte 0x6f
1455+ .byte 0x00
1456+ .byte 0x74
1457+ .byte 0x00
1458+ .byte 0x20
1459+ .byte 0x00
1460+ .byte 0x44
1461+ .byte 0x00
1462+ .byte 0x65
1463+ .byte 0x00
1464+ .byte 0x76
1465+ .byte 0x00
1466+ .byte 0x69
1467+ .byte 0x00
1468+ .byte 0x63
1469+ .byte 0x00
1470+ .byte 0x65
1471+ .byte 0x00
1472+
1473+ .align 2
1474+cpu_info_data:
1475+ .byte 0x4a
1476+ .byte 0x5a
1477+ .byte 0x34
1478+ .byte 0x37
1479+ .byte 0x34
1480+ .byte 0x30
1481+ .byte 0x56
1482+ .byte 0x31
1483+usbboot_end:
1484+
1485+ .set reorder
1486diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
1487index 3ec34f3..4ab2229 100644
1488--- a/drivers/mtd/nand/jz4740_nand.c
1489+++ b/drivers/mtd/nand/jz4740_nand.c
1490@@ -15,6 +15,9 @@
1491 #include <asm/io.h>
1492 #include <asm/jz4740.h>
1493 
1494+#ifdef CONFIG_SPL_BUILD
1495+#define printf(arg...) do {} while (0)
1496+#endif
1497 #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
1498 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
1499 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
1500@@ -176,7 +179,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
1501         for (k = 0; k < 9; k++)
1502             writeb(read_ecc[k], &emc->nfpar[k]);
1503     }
1504- /* Set PRDY */
1505+
1506     writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
1507 
1508     /* Wait for completion */
1509@@ -184,7 +187,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
1510         status = readl(&emc->nfints);
1511     } while (!(status & EMC_NFINTS_DECF));
1512 
1513- /* disable ecc */
1514+ /* Disable ECC */
1515     writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
1516 
1517     /* Check decoding */
1518@@ -192,7 +195,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
1519         return 0;
1520 
1521     if (status & EMC_NFINTS_UNCOR) {
1522- printf("uncorrectable ecc\n");
1523+ printf("JZ4740 uncorrectable ECC\n");
1524         return -1;
1525     }
1526 
1527@@ -230,6 +233,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
1528     return errcnt;
1529 }
1530 
1531+#ifdef CONFIG_SPL_BUILD
1532+static void jz_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1533+{
1534+ int i;
1535+ struct nand_chip *this = mtd->priv;
1536+
1537+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \
1538+ (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
1539+ for (i = 0; i < len; i += 2)
1540+ buf[i] = readw(this->IO_ADDR_R);
1541+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \
1542+ (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
1543+ for (i = 0; i < len; i++)
1544+ buf[i] = readb(this->IO_ADDR_R);
1545+#else
1546+ #error JZ4740_NANDBOOT_CFG not defined or wrong
1547+#endif
1548+}
1549+
1550+static uint8_t jz_nand_read_byte(struct mtd_info *mtd)
1551+{
1552+ struct nand_chip *this = mtd->priv;
1553+ return readb(this->IO_ADDR_R);
1554+}
1555+#endif
1556+
1557 /*
1558  * Main initialization routine
1559  */
1560@@ -254,6 +283,10 @@ int board_nand_init(struct nand_chip *nand)
1561     nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
1562     nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
1563     nand->ecc.layout = &qi_lb60_ecclayout_2gb;
1564+#ifdef CONFIG_SPL_BUILD
1565+ nand->read_byte = jz_nand_read_byte;
1566+ nand->read_buf = jz_nand_read_buf;
1567+#endif
1568     nand->chip_delay = 50;
1569     nand->options = NAND_USE_FLASH_BBT;
1570 
1571diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
1572index 4bb5bbc..d4449ac 100644
1573--- a/include/configs/qi_lb60.h
1574+++ b/include/configs/qi_lb60.h
1575@@ -1,5 +1,5 @@
1576 /*
1577- * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
1578+ * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
1579  *
1580  * This program is free software; you can redistribute it and/or
1581  * modify it under the terms of the GNU General Public License
1582@@ -14,7 +14,6 @@
1583 #define CONFIG_SYS_LITTLE_ENDIAN
1584 #define CONFIG_JZSOC /* Jz SoC */
1585 #define CONFIG_JZ4740 /* Jz4740 SoC */
1586-#define CONFIG_NAND_JZ4740
1587 
1588 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
1589 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
1590@@ -24,24 +23,43 @@
1591 #define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */
1592 #define CONFIG_BAUDRATE 57600
1593 
1594+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
1595+#define CONFIG_BOOTDELAY 0
1596+#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
1597+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x280000;bootm"
1598+
1599+/*
1600+ * Miscellaneous configurable options
1601+ */
1602+#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
1603+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
1604+#define CONFIG_SYS_LOAD_ADDR 0x80600000
1605+#define CONFIG_SYS_MEMTEST_START 0x80100000
1606+#define CONFIG_SYS_MEMTEST_END 0x80A00000
1607+#define CONFIG_SYS_TEXT_BASE 0x80100000
1608+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
1609+
1610+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
1611+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
1612+
1613+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1614+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1615+
1616+#define CONFIG_SYS_LONGHELP
1617+#define CONFIG_SYS_MAXARGS 16
1618+#define CONFIG_SYS_PROMPT "NanoNote# "
1619+
1620 #define CONFIG_SKIP_LOWLEVEL_INIT
1621 #define CONFIG_BOARD_EARLY_INIT_F
1622 #define CONFIG_SYS_NO_FLASH
1623 #define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
1624-#define CONFIG_ENV_OVERWRITE
1625-
1626-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
1627-#define CONFIG_BOOTDELAY 0
1628-#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
1629-#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
1630 
1631 /*
1632- * Command line configuration.
1633+ * Command line configuration
1634  */
1635 #define CONFIG_CMD_BOOTD /* bootd */
1636 #define CONFIG_CMD_CONSOLE /* coninfo */
1637 #define CONFIG_CMD_ECHO /* echo arguments */
1638-
1639 #define CONFIG_CMD_LOADB /* loadb */
1640 #define CONFIG_CMD_LOADS /* loads */
1641 #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
1642@@ -58,45 +76,16 @@
1643 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
1644 
1645 /*
1646- * Miscellaneous configurable options
1647- */
1648-#define CONFIG_SYS_MAXARGS 16
1649-#define CONFIG_SYS_LONGHELP
1650-#define CONFIG_SYS_PROMPT "NanoNote# "
1651-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1652-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1653-
1654-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
1655-#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
1656-
1657-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
1658-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
1659-#define CONFIG_SYS_LOAD_ADDR 0x80600000
1660-#define CONFIG_SYS_MEMTEST_START 0x80100000
1661-#define CONFIG_SYS_MEMTEST_END 0x80800000
1662-
1663-/*
1664- * Environment
1665+ * NAND driver configuration
1666  */
1667-#define CONFIG_ENV_IS_IN_NAND /* use NAND for environment vars */
1668-
1669-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
1670-/*
1671- * if board nand flash is 1GB, set to 1
1672- * if board nand flash is 2GB, set to 2
1673- * for change the PAGE_SIZE and BLOCK_SIZE
1674- * will delete when there is no 1GB flash
1675- */
1676-#define NANONOTE_NAND_SIZE 2
1677-
1678-#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
1679-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
1680-/* nand bad block was marked at this page in a block, start from 0 */
1681+#define CONFIG_NAND_JZ4740
1682+#define CONFIG_SYS_NAND_PAGE_SIZE 4096
1683+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 << 10)
1684+/* NAND bad block was marked at this page in a block, start from 0 */
1685 #define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
1686 #define CONFIG_SYS_NAND_PAGE_COUNT 128
1687 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
1688-/* ECC offset position in oob area, default value is 6 if it isn't defined */
1689-#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
1690+#define CONFIG_SYS_NAND_ECC_POS 12
1691 #define CONFIG_SYS_NAND_ECCSIZE 512
1692 #define CONFIG_SYS_NAND_ECCBYTES 9
1693 #define CONFIG_SYS_NAND_ECCPOS \
1694@@ -115,10 +104,9 @@
1695 #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
1696 #define CONFIG_SYS_MAX_NAND_DEVICE 1
1697 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
1698-#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
1699 
1700 /*
1701- * IPL (Initial Program Loader, integrated inside CPU)
1702+ * IPL (Initial Program Loader, integrated inside Ingenic Xburst JZ4740 CPU)
1703  * Will load first 8k from NAND (SPL) into cache and execute it from there.
1704  *
1705  * SPL (Secondary Program Loader)
1706@@ -130,77 +118,86 @@
1707  * NUB (NAND U-Boot)
1708  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
1709  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
1710- *
1711  */
1712+
1713+/*
1714+ * NAND SPL configuration
1715+ */
1716+#define CONFIG_SPL
1717+#define CONFIG_SPL_NAND_LOAD
1718+#define CONFIG_SPL_NAND_SIMPLE
1719+#define CONFIG_SPL_NAND_SUPPORT
1720+#define CONFIG_SPL_TEXT_BASE 0x80000000
1721+#define CONFIG_SPL_START_S_PATH "arch/mips/cpu/xburst/spl"
1722+
1723+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
1724+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
1725+#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
1726+
1727 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
1728 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
1729-/* Start NUB from this addr*/
1730+ /* Start NUB from this addr */
1731+#define CONFIG_SYS_NAND_U_BOOT_OFFS (32 << 10) /* Offset of NUB */
1732+#define CONFIG_SYS_NAND_U_BOOT_SIZE (256 << 10) /* Size of NUB */
1733 
1734 /*
1735- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
1736+ * Environment configuration
1737  */
1738-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
1739-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
1740-
1741+#define CONFIG_ENV_OVERWRITE
1742+#define CONFIG_ENV_IS_IN_NAND
1743 #define CONFIG_ENV_SIZE (4 << 10)
1744 #define CONFIG_ENV_OFFSET \
1745     (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
1746 #define CONFIG_ENV_OFFSET_REDUND \
1747     (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
1748 
1749-#define CONFIG_SYS_TEXT_BASE 0x80100000
1750-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
1751-
1752 /*
1753- * SDRAM Info.
1754+ * CPU cache configuration
1755  */
1756-#define CONFIG_NR_DRAM_BANKS 1
1757+#define CONFIG_SYS_DCACHE_SIZE 16384
1758+#define CONFIG_SYS_ICACHE_SIZE 16384
1759+#define CONFIG_SYS_CACHELINE_SIZE 32
1760 
1761 /*
1762- * Cache Configuration
1763+ * SDRAM configuration
1764  */
1765-#define CONFIG_SYS_DCACHE_SIZE 16384
1766-#define CONFIG_SYS_ICACHE_SIZE 16384
1767-#define CONFIG_SYS_CACHELINE_SIZE 32
1768+#define CONFIG_NR_DRAM_BANKS 1
1769+
1770+#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
1771+#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
1772+#define SDRAM_ROW 13 /* Row address: 11 to 13 */
1773+#define SDRAM_COL 9 /* Column address: 8 to 12 */
1774+#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
1775+#define SDRAM_TRAS 45 /* RAS# Active Time */
1776+#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
1777+#define SDRAM_TPC 20 /* RAS# Precharge Time */
1778+#define SDRAM_TRWL 7 /* Write Latency Time */
1779+#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
1780 
1781 /*
1782- * GPIO definition
1783+ * GPIO configuration
1784  */
1785-#define GPIO_LCD_CS (2 * 32 + 21)
1786-#define GPIO_AMP_EN (3 * 32 + 4)
1787+#define GPIO_LCD_CS (2 * 32 + 21)
1788+#define GPIO_AMP_EN (3 * 32 + 4)
1789 
1790-#define GPIO_SDPW_EN (3 * 32 + 2)
1791-#define GPIO_SD_DETECT (3 * 32 + 0)
1792+#define GPIO_SDPW_EN (3 * 32 + 2)
1793+#define GPIO_SD_DETECT (3 * 32 + 0)
1794 
1795-#define GPIO_BUZZ_PWM (3 * 32 + 27)
1796-#define GPIO_USB_DETECT (3 * 32 + 28)
1797+#define GPIO_BUZZ_PWM (3 * 32 + 27)
1798+#define GPIO_USB_DETECT (3 * 32 + 28)
1799 
1800-#define GPIO_AUDIO_POP (1 * 32 + 29)
1801-#define GPIO_COB_TEST (1 * 32 + 30)
1802+#define GPIO_AUDIO_POP (1 * 32 + 29)
1803+#define GPIO_COB_TEST (1 * 32 + 30)
1804 
1805 #define GPIO_KEYOUT_BASE (2 * 32 + 10)
1806-#define GPIO_KEYIN_BASE (3 * 32 + 18)
1807-#define GPIO_KEYIN_8 (3 * 32 + 26)
1808+#define GPIO_KEYIN_BASE (3 * 32 + 18)
1809+#define GPIO_KEYIN_8 (3 * 32 + 26)
1810 
1811-#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
1812+#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
1813 #define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
1814 
1815 #define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
1816 #define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
1817 #define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
1818 
1819-/* SDRAM paramters */
1820-#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
1821-#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
1822-#define SDRAM_ROW 13 /* Row address: 11 to 13 */
1823-#define SDRAM_COL 9 /* Column address: 8 to 12 */
1824-#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
1825-
1826-/* SDRAM Timings, unit: ns */
1827-#define SDRAM_TRAS 45 /* RAS# Active Time */
1828-#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
1829-#define SDRAM_TPC 20 /* RAS# Precharge Time */
1830-#define SDRAM_TRWL 7 /* Write Latency Time */
1831-#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
1832-
1833 #endif
1834--
18351.7.9.5
1836
1837

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