| 1 | From ae857e757e24058a78f95cd472024bb4f268899f Mon Sep 17 00:00:00 2001 |
| 2 | From: Xiangfu <xiangfu@openmobilefree.net> |
| 3 | Date: Wed, 10 Oct 2012 18:19:41 +0800 |
| 4 | Subject: [PATCH 2/5] add mmc support |
| 5 | |
| 6 | --- |
| 7 | arch/mips/include/asm/jz4740.h | 166 ++++++ |
| 8 | board/qi/qi_lb60/qi_lb60.c | 9 +- |
| 9 | drivers/mmc/Makefile | 1 + |
| 10 | drivers/mmc/jz_mmc.c | 1179 ++++++++++++++++++++++++++++++++++++++++ |
| 11 | drivers/mmc/jz_mmc.h | 176 ++++++ |
| 12 | include/configs/qi_lb60.h | 9 + |
| 13 | include/mmc.h | 40 ++ |
| 14 | 7 files changed, 1578 insertions(+), 2 deletions(-) |
| 15 | create mode 100644 drivers/mmc/jz_mmc.c |
| 16 | create mode 100644 drivers/mmc/jz_mmc.h |
| 17 | |
| 18 | diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h |
| 19 | index 7a7cfff..68287fb 100644 |
| 20 | --- a/arch/mips/include/asm/jz4740.h |
| 21 | +++ b/arch/mips/include/asm/jz4740.h |
| 22 | @@ -1146,5 +1146,171 @@ extern void sdram_init(void); |
| 23 | extern void calc_clocks(void); |
| 24 | extern void rtc_init(void); |
| 25 | |
| 26 | +/************************************************************************* |
| 27 | + * MSC |
| 28 | + *************************************************************************/ |
| 29 | +#define REG8(addr) *((volatile u8 *)(addr)) |
| 30 | +#define REG16(addr) *((volatile u16 *)(addr)) |
| 31 | +#define REG32(addr) *((volatile u32 *)(addr)) |
| 32 | + |
| 33 | +#define CPM_BASE 0xB0000000 |
| 34 | +#define CPM_CPCCR (CPM_BASE+0x00) |
| 35 | +#define CPM_MSCCDR (CPM_BASE+0x68) |
| 36 | +#define REG_CPM_MSCCDR REG32(CPM_MSCCDR) |
| 37 | +#define REG_CPM_CPCCR REG32(CPM_CPCCR) |
| 38 | + |
| 39 | +#define MSC_BASE 0xB0021000 |
| 40 | + |
| 41 | +#define MSC_STRPCL (MSC_BASE + 0x000) |
| 42 | +#define MSC_STAT (MSC_BASE + 0x004) |
| 43 | +#define MSC_CLKRT (MSC_BASE + 0x008) |
| 44 | +#define MSC_CMDAT (MSC_BASE + 0x00C) |
| 45 | +#define MSC_RESTO (MSC_BASE + 0x010) |
| 46 | +#define MSC_RDTO (MSC_BASE + 0x014) |
| 47 | +#define MSC_BLKLEN (MSC_BASE + 0x018) |
| 48 | +#define MSC_NOB (MSC_BASE + 0x01C) |
| 49 | +#define MSC_SNOB (MSC_BASE + 0x020) |
| 50 | +#define MSC_IMASK (MSC_BASE + 0x024) |
| 51 | +#define MSC_IREG (MSC_BASE + 0x028) |
| 52 | +#define MSC_CMD (MSC_BASE + 0x02C) |
| 53 | +#define MSC_ARG (MSC_BASE + 0x030) |
| 54 | +#define MSC_RES (MSC_BASE + 0x034) |
| 55 | +#define MSC_RXFIFO (MSC_BASE + 0x038) |
| 56 | +#define MSC_TXFIFO (MSC_BASE + 0x03C) |
| 57 | + |
| 58 | +#define REG_MSC_STRPCL REG16(MSC_STRPCL) |
| 59 | +#define REG_MSC_STAT REG32(MSC_STAT) |
| 60 | +#define REG_MSC_CLKRT REG16(MSC_CLKRT) |
| 61 | +#define REG_MSC_CMDAT REG32(MSC_CMDAT) |
| 62 | +#define REG_MSC_RESTO REG16(MSC_RESTO) |
| 63 | +#define REG_MSC_RDTO REG16(MSC_RDTO) |
| 64 | +#define REG_MSC_BLKLEN REG16(MSC_BLKLEN) |
| 65 | +#define REG_MSC_NOB REG16(MSC_NOB) |
| 66 | +#define REG_MSC_SNOB REG16(MSC_SNOB) |
| 67 | +#define REG_MSC_IMASK REG16(MSC_IMASK) |
| 68 | +#define REG_MSC_IREG REG16(MSC_IREG) |
| 69 | +#define REG_MSC_CMD REG8(MSC_CMD) |
| 70 | +#define REG_MSC_ARG REG32(MSC_ARG) |
| 71 | +#define REG_MSC_RES REG16(MSC_RES) |
| 72 | +#define REG_MSC_RXFIFO REG32(MSC_RXFIFO) |
| 73 | +#define REG_MSC_TXFIFO REG32(MSC_TXFIFO) |
| 74 | + |
| 75 | +/* MSC Clock and Control Register (MSC_STRPCL) */ |
| 76 | + |
| 77 | +#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) |
| 78 | +#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) |
| 79 | +#define MSC_STRPCL_START_READWAIT (1 << 5) |
| 80 | +#define MSC_STRPCL_STOP_READWAIT (1 << 4) |
| 81 | +#define MSC_STRPCL_RESET (1 << 3) |
| 82 | +#define MSC_STRPCL_START_OP (1 << 2) |
| 83 | +#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 |
| 84 | +#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) |
| 85 | + #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ |
| 86 | + #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ |
| 87 | + |
| 88 | +/* MSC Status Register (MSC_STAT) */ |
| 89 | + |
| 90 | +#define MSC_STAT_IS_RESETTING (1 << 15) |
| 91 | +#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) |
| 92 | +#define MSC_STAT_PRG_DONE (1 << 13) |
| 93 | +#define MSC_STAT_DATA_TRAN_DONE (1 << 12) |
| 94 | +#define MSC_STAT_END_CMD_RES (1 << 11) |
| 95 | +#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) |
| 96 | +#define MSC_STAT_IS_READWAIT (1 << 9) |
| 97 | +#define MSC_STAT_CLK_EN (1 << 8) |
| 98 | +#define MSC_STAT_DATA_FIFO_FULL (1 << 7) |
| 99 | +#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) |
| 100 | +#define MSC_STAT_CRC_RES_ERR (1 << 5) |
| 101 | +#define MSC_STAT_CRC_READ_ERROR (1 << 4) |
| 102 | +#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 |
| 103 | +#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) |
| 104 | + #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ |
| 105 | + #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ |
| 106 | + #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ |
| 107 | +#define MSC_STAT_TIME_OUT_RES (1 << 1) |
| 108 | +#define MSC_STAT_TIME_OUT_READ (1 << 0) |
| 109 | + |
| 110 | +/* MSC Bus Clock Control Register (MSC_CLKRT) */ |
| 111 | + |
| 112 | +#define MSC_CLKRT_CLK_RATE_BIT 0 |
| 113 | +#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) |
| 114 | + #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ |
| 115 | + #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ |
| 116 | + #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ |
| 117 | + #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ |
| 118 | + #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ |
| 119 | + #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ |
| 120 | + #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ |
| 121 | + #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ |
| 122 | + |
| 123 | +/* MSC Command Sequence Control Register (MSC_CMDAT) */ |
| 124 | + |
| 125 | +#define MSC_CMDAT_IO_ABORT (1 << 11) |
| 126 | +#define MSC_CMDAT_BUS_WIDTH_BIT 9 |
| 127 | +#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 128 | +#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 129 | +#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 130 | +#define MSC_CMDAT_DMA_EN (1 << 8) |
| 131 | +#define MSC_CMDAT_INIT (1 << 7) |
| 132 | +#define MSC_CMDAT_BUSY (1 << 6) |
| 133 | +#define MSC_CMDAT_STREAM_BLOCK (1 << 5) |
| 134 | +#define MSC_CMDAT_WRITE (1 << 4) |
| 135 | +#define MSC_CMDAT_READ (0 << 4) |
| 136 | +#define MSC_CMDAT_DATA_EN (1 << 3) |
| 137 | +#define MSC_CMDAT_RESPONSE_BIT 0 |
| 138 | +#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) |
| 139 | +#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) |
| 140 | +#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) |
| 141 | +#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) |
| 142 | +#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) |
| 143 | +#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) |
| 144 | +#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) |
| 145 | +#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) |
| 146 | + |
| 147 | +/* MSC Interrupts Mask Register (MSC_IMASK) */ |
| 148 | +#define MSC_IMASK_SDIO (1 << 7) |
| 149 | +#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) |
| 150 | +#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) |
| 151 | +#define MSC_IMASK_END_CMD_RES (1 << 2) |
| 152 | +#define MSC_IMASK_PRG_DONE (1 << 1) |
| 153 | +#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) |
| 154 | + |
| 155 | + |
| 156 | +/* MSC Interrupts Status Register (MSC_IREG) */ |
| 157 | +#define MSC_IREG_SDIO (1 << 7) |
| 158 | +#define MSC_IREG_TXFIFO_WR_REQ (1 << 6) |
| 159 | +#define MSC_IREG_RXFIFO_RD_REQ (1 << 5) |
| 160 | +#define MSC_IREG_END_CMD_RES (1 << 2) |
| 161 | +#define MSC_IREG_PRG_DONE (1 << 1) |
| 162 | +#define MSC_IREG_DATA_TRAN_DONE (1 << 0) |
| 163 | + |
| 164 | +static __inline__ unsigned int __cpm_get_pllout2(void) |
| 165 | +{ |
| 166 | + if (REG_CPM_CPCCR & CPM_CPCCR_PCS) |
| 167 | + return __cpm_get_pllout(); |
| 168 | + else |
| 169 | + return __cpm_get_pllout()/2; |
| 170 | +} |
| 171 | + |
| 172 | +static inline void __cpm_select_msc_clk(int sd) |
| 173 | +{ |
| 174 | + unsigned int pllout2 = __cpm_get_pllout2(); |
| 175 | + unsigned int div = 0; |
| 176 | + |
| 177 | + if (sd) { |
| 178 | + div = pllout2 / 24000000; |
| 179 | + } |
| 180 | + else { |
| 181 | + div = pllout2 / 16000000; |
| 182 | + } |
| 183 | + |
| 184 | + REG_CPM_MSCCDR = div - 1; |
| 185 | +} |
| 186 | +#define __msc_reset() \ |
| 187 | +do { \ |
| 188 | + REG_MSC_STRPCL = MSC_STRPCL_RESET; \ |
| 189 | + while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ |
| 190 | +} while (0) |
| 191 | + |
| 192 | #endif /* !__ASSEMBLY__ */ |
| 193 | #endif /* __JZ4740_H__ */ |
| 194 | diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c |
| 195 | index 553e05d..68da069 100644 |
| 196 | --- a/board/qi/qi_lb60/qi_lb60.c |
| 197 | +++ b/board/qi/qi_lb60/qi_lb60.c |
| 198 | @@ -40,8 +40,13 @@ static void gpio_init(void) |
| 199 | __gpio_clear_pin(GPIO_KEYOUT_BASE + i); |
| 200 | } |
| 201 | |
| 202 | - __gpio_as_input(GPIO_KEYIN_8); |
| 203 | - __gpio_enable_pull(GPIO_KEYIN_8); |
| 204 | + if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){ |
| 205 | + printf("[S] pressed, enable UART0\n"); |
| 206 | + __gpio_as_uart0(); |
| 207 | + } else { |
| 208 | + __gpio_as_input(GPIO_KEYIN_8); |
| 209 | + __gpio_enable_pull(GPIO_KEYIN_8); |
| 210 | + } |
| 211 | |
| 212 | /* enable the TP4, TP5 as UART0 */ |
| 213 | __gpio_jtag_to_uart0(); |
| 214 | diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile |
| 215 | index 565ba6a..3c717b1 100644 |
| 216 | --- a/drivers/mmc/Makefile |
| 217 | +++ b/drivers/mmc/Makefile |
| 218 | @@ -47,6 +47,7 @@ COBJS-$(CONFIG_SDHCI) += sdhci.o |
| 219 | COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o |
| 220 | COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o |
| 221 | COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o |
| 222 | +COBJS-$(CONFIG_JZ4740_MMC) += jz_mmc.o |
| 223 | |
| 224 | COBJS := $(COBJS-y) |
| 225 | SRCS := $(COBJS:.o=.c) |
| 226 | diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c |
| 227 | new file mode 100644 |
| 228 | index 0000000..642cecc |
| 229 | --- /dev/null |
| 230 | +++ b/drivers/mmc/jz_mmc.c |
| 231 | @@ -0,0 +1,1179 @@ |
| 232 | +/* |
| 233 | + * (C) Copyright 2003 |
| 234 | + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
| 235 | + * |
| 236 | + * See file CREDITS for list of people who contributed to this |
| 237 | + * project. |
| 238 | + * |
| 239 | + * This program is free software; you can redistribute it and/or |
| 240 | + * modify it under the terms of the GNU General Public License as |
| 241 | + * published by the Free Software Foundation; either version 2 of |
| 242 | + * the License, or (at your option) any later version. |
| 243 | + * |
| 244 | + * This program is distributed in the hope that it will be useful, |
| 245 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 246 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 247 | + * GNU General Public License for more details. |
| 248 | + * |
| 249 | + * You should have received a copy of the GNU General Public License |
| 250 | + * along with this program; if not, write to the Free Software |
| 251 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 252 | + * MA 02111-1307 USA |
| 253 | + */ |
| 254 | + |
| 255 | +#include <config.h> |
| 256 | +#include <common.h> |
| 257 | +#include <part.h> |
| 258 | +#include <mmc.h> |
| 259 | + |
| 260 | +#include <asm/io.h> |
| 261 | +#include <asm/jz4740.h> |
| 262 | +#include "jz_mmc.h" |
| 263 | + |
| 264 | +static int sd2_0 = 0; |
| 265 | +static int mmc_ready = 0; |
| 266 | +static int use_4bit; /* Use 4-bit data bus */ |
| 267 | +/* |
| 268 | + * MMC Events |
| 269 | + */ |
| 270 | +#define MMC_EVENT_NONE 0x00 /* No events */ |
| 271 | +#define MMC_EVENT_RX_DATA_DONE 0x01 /* Rx data done */ |
| 272 | +#define MMC_EVENT_TX_DATA_DONE 0x02 /* Tx data done */ |
| 273 | +#define MMC_EVENT_PROG_DONE 0x04 /* Programming is done */ |
| 274 | + |
| 275 | + |
| 276 | +#define MMC_IRQ_MASK() \ |
| 277 | +do { \ |
| 278 | + REG_MSC_IMASK = 0xffff; \ |
| 279 | + REG_MSC_IREG = 0xffff; \ |
| 280 | +} while (0) |
| 281 | + |
| 282 | +/* |
| 283 | + * GPIO definition |
| 284 | + */ |
| 285 | +#if defined(CONFIG_SAKC) |
| 286 | + |
| 287 | +#define __msc_init_io() \ |
| 288 | +do { \ |
| 289 | + __gpio_as_input(GPIO_SD_CD_N); \ |
| 290 | +} while (0) |
| 291 | + |
| 292 | +#else |
| 293 | +#define __msc_init_io() \ |
| 294 | +do { \ |
| 295 | + __gpio_as_output(GPIO_SD_VCC_EN_N); \ |
| 296 | + __gpio_as_input(GPIO_SD_CD_N); \ |
| 297 | +} while (0) |
| 298 | + |
| 299 | +#define __msc_enable_power() \ |
| 300 | +do { \ |
| 301 | + __gpio_clear_pin(GPIO_SD_VCC_EN_N); \ |
| 302 | +} while (0) |
| 303 | + |
| 304 | +#define __msc_disable_power() \ |
| 305 | +do { \ |
| 306 | + __gpio_set_pin(GPIO_SD_VCC_EN_N); \ |
| 307 | +} while (0) |
| 308 | + |
| 309 | +#endif /* CONFIG_SAKE */ |
| 310 | + |
| 311 | +#define __msc_card_detected() \ |
| 312 | +({ \ |
| 313 | + int detected = 1; \ |
| 314 | + __gpio_as_input(GPIO_SD_CD_N); \ |
| 315 | + __gpio_disable_pull(GPIO_SD_CD_N); \ |
| 316 | + if (!__gpio_get_pin(GPIO_SD_CD_N)) \ |
| 317 | + detected = 0; \ |
| 318 | + detected; \ |
| 319 | +}) |
| 320 | + |
| 321 | +/* |
| 322 | + * Local functions |
| 323 | + */ |
| 324 | + |
| 325 | +extern int |
| 326 | +fat_register_device(block_dev_desc_t *dev_desc, int part_no); |
| 327 | + |
| 328 | +static block_dev_desc_t mmc_dev; |
| 329 | + |
| 330 | +block_dev_desc_t * mmc_get_dev(int dev) |
| 331 | +{ |
| 332 | + return ((block_dev_desc_t *)&mmc_dev); |
| 333 | +} |
| 334 | + |
| 335 | +/* Stop the MMC clock and wait while it happens */ |
| 336 | +static inline int jz_mmc_stop_clock(void) |
| 337 | +{ |
| 338 | + int timeout = 1000; |
| 339 | + |
| 340 | + REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; |
| 341 | + |
| 342 | + while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) { |
| 343 | + timeout--; |
| 344 | + if (timeout == 0) |
| 345 | + return MMC_ERROR_TIMEOUT; |
| 346 | + udelay(1); |
| 347 | + } |
| 348 | + return MMC_NO_ERROR; |
| 349 | +} |
| 350 | + |
| 351 | +/* Start the MMC clock and operation */ |
| 352 | +static inline int jz_mmc_start_clock(void) |
| 353 | +{ |
| 354 | + REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP; |
| 355 | + return MMC_NO_ERROR; |
| 356 | +} |
| 357 | + |
| 358 | +static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate) |
| 359 | +{ |
| 360 | + u32 clkrt = 0; |
| 361 | + u32 clk_src = is_sd ? 24000000 : 16000000; |
| 362 | + |
| 363 | + while (rate < clk_src) { |
| 364 | + clkrt ++; |
| 365 | + clk_src >>= 1; |
| 366 | + } |
| 367 | + |
| 368 | + return clkrt; |
| 369 | +} |
| 370 | + |
| 371 | +/* Set the MMC clock frequency */ |
| 372 | +void jz_mmc_set_clock(int sd, u32 rate) |
| 373 | +{ |
| 374 | + jz_mmc_stop_clock(); |
| 375 | + |
| 376 | + /* Select clock source of MSC */ |
| 377 | + __cpm_select_msc_clk(sd); |
| 378 | + |
| 379 | + /* Set clock dividor of MSC */ |
| 380 | + REG_MSC_CLKRT = jz_mmc_calc_clkrt(sd, rate); |
| 381 | +} |
| 382 | + |
| 383 | +static int jz_mmc_check_status(struct mmc_request *request) |
| 384 | +{ |
| 385 | + u32 status = REG_MSC_STAT; |
| 386 | + |
| 387 | + /* Checking for response or data timeout */ |
| 388 | + if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)) { |
| 389 | + printf("MMC/SD timeout, MMC_STAT 0x%x CMD %d\n", status, request->cmd); |
| 390 | + return MMC_ERROR_TIMEOUT; |
| 391 | + } |
| 392 | + |
| 393 | + /* Checking for CRC error */ |
| 394 | + if (status & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_RES_ERR)) { |
| 395 | + printf("MMC/CD CRC error, MMC_STAT 0x%x\n", status); |
| 396 | + return MMC_ERROR_CRC; |
| 397 | + } |
| 398 | + |
| 399 | + return MMC_NO_ERROR; |
| 400 | +} |
| 401 | + |
| 402 | +/* Obtain response to the command and store it to response buffer */ |
| 403 | +static void jz_mmc_get_response(struct mmc_request *request) |
| 404 | +{ |
| 405 | + int i; |
| 406 | + u8 *buf; |
| 407 | + u32 data; |
| 408 | + |
| 409 | + debug("fetch response for request %d, cmd %d\n", |
| 410 | + request->rtype, request->cmd); |
| 411 | + |
| 412 | + buf = request->response; |
| 413 | + request->result = MMC_NO_ERROR; |
| 414 | + |
| 415 | + switch (request->rtype) { |
| 416 | + case RESPONSE_R1: case RESPONSE_R1B: case RESPONSE_R6: |
| 417 | + case RESPONSE_R3: case RESPONSE_R4: case RESPONSE_R5: |
| 418 | + { |
| 419 | + data = REG_MSC_RES; |
| 420 | + buf[0] = (data >> 8) & 0xff; |
| 421 | + buf[1] = data & 0xff; |
| 422 | + data = REG_MSC_RES; |
| 423 | + buf[2] = (data >> 8) & 0xff; |
| 424 | + buf[3] = data & 0xff; |
| 425 | + data = REG_MSC_RES; |
| 426 | + buf[4] = data & 0xff; |
| 427 | + |
| 428 | + debug("request %d, response [%02x %02x %02x %02x %02x]\n", |
| 429 | + request->rtype, buf[0], buf[1], buf[2], buf[3], buf[4]); |
| 430 | + break; |
| 431 | + } |
| 432 | + case RESPONSE_R2_CID: case RESPONSE_R2_CSD: |
| 433 | + { |
| 434 | + for (i = 0; i < 16; i += 2) { |
| 435 | + data = REG_MSC_RES; |
| 436 | + buf[i] = (data >> 8) & 0xff; |
| 437 | + buf[i+1] = data & 0xff; |
| 438 | + } |
| 439 | + debug("request %d, response [", request->rtype); |
| 440 | +#if CONFIG_MMC_DEBUG_VERBOSE > 2 |
| 441 | + if (g_mmc_debug >= 3) { |
| 442 | + int n; |
| 443 | + for (n = 0; n < 17; n++) |
| 444 | + printk("%02x ", buf[n]); |
| 445 | + printk("]\n"); |
| 446 | + } |
| 447 | +#endif |
| 448 | + break; |
| 449 | + } |
| 450 | + case RESPONSE_NONE: |
| 451 | + debug("No response\n"); |
| 452 | + break; |
| 453 | + |
| 454 | + default: |
| 455 | + debug("unhandled response type for request %d\n", request->rtype); |
| 456 | + break; |
| 457 | + } |
| 458 | +} |
| 459 | + |
| 460 | +static int jz_mmc_receive_data(struct mmc_request *req) |
| 461 | +{ |
| 462 | + u32 stat, timeout, data, cnt; |
| 463 | + u8 *buf = req->buffer; |
| 464 | + u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */ |
| 465 | + |
| 466 | + timeout = 0x3ffffff; |
| 467 | + |
| 468 | + while (timeout) { |
| 469 | + timeout--; |
| 470 | + stat = REG_MSC_STAT; |
| 471 | + |
| 472 | + if (stat & MSC_STAT_TIME_OUT_READ) |
| 473 | + return MMC_ERROR_TIMEOUT; |
| 474 | + else if (stat & MSC_STAT_CRC_READ_ERROR) |
| 475 | + return MMC_ERROR_CRC; |
| 476 | + else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY) |
| 477 | + || (stat & MSC_STAT_DATA_FIFO_AFULL)) { |
| 478 | + /* Ready to read data */ |
| 479 | + break; |
| 480 | + } |
| 481 | + udelay(1); |
| 482 | + } |
| 483 | + if (!timeout) |
| 484 | + return MMC_ERROR_TIMEOUT; |
| 485 | + |
| 486 | + /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */ |
| 487 | + cnt = wblocklen; |
| 488 | + while (cnt) { |
| 489 | + data = REG_MSC_RXFIFO; |
| 490 | + { |
| 491 | + *buf++ = (u8)(data >> 0); |
| 492 | + *buf++ = (u8)(data >> 8); |
| 493 | + *buf++ = (u8)(data >> 16); |
| 494 | + *buf++ = (u8)(data >> 24); |
| 495 | + } |
| 496 | + cnt --; |
| 497 | + while (cnt && (REG_MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY)) |
| 498 | + ; |
| 499 | + } |
| 500 | + return MMC_NO_ERROR; |
| 501 | +} |
| 502 | + |
| 503 | +static int jz_mmc_transmit_data(struct mmc_request *req) |
| 504 | +{ |
| 505 | +#if 0 |
| 506 | + u32 nob = req->nob; |
| 507 | + u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */ |
| 508 | + u8 *buf = req->buffer; |
| 509 | + u32 *wbuf = (u32 *)buf; |
| 510 | + u32 waligned = (((u32)buf & 0x3) == 0); /* word aligned ? */ |
| 511 | + u32 stat, timeout, data, cnt; |
| 512 | + |
| 513 | + for (nob; nob >= 1; nob--) { |
| 514 | + timeout = 0x3FFFFFF; |
| 515 | + |
| 516 | + while (timeout) { |
| 517 | + timeout--; |
| 518 | + stat = REG_MSC_STAT; |
| 519 | + |
| 520 | + if (stat & (MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_WRITE_ERROR_NOSTS)) |
| 521 | + return MMC_ERROR_CRC; |
| 522 | + else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) { |
| 523 | + /* Ready to write data */ |
| 524 | + break; |
| 525 | + } |
| 526 | + |
| 527 | + udelay(1); |
| 528 | + } |
| 529 | + |
| 530 | + if (!timeout) |
| 531 | + return MMC_ERROR_TIMEOUT; |
| 532 | + |
| 533 | + /* Write data to TXFIFO */ |
| 534 | + cnt = wblocklen; |
| 535 | + while (cnt) { |
| 536 | + while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL) |
| 537 | + ; |
| 538 | + |
| 539 | + if (waligned) { |
| 540 | + REG_MSC_TXFIFO = *wbuf++; |
| 541 | + } |
| 542 | + else { |
| 543 | + data = *buf++ | (*buf++ << 8) | (*buf++ << 16) | (*buf++ << 24); |
| 544 | + REG_MSC_TXFIFO = data; |
| 545 | + } |
| 546 | + |
| 547 | + cnt--; |
| 548 | + } |
| 549 | + } |
| 550 | +#endif |
| 551 | + return MMC_NO_ERROR; |
| 552 | +} |
| 553 | + |
| 554 | + |
| 555 | +/* |
| 556 | + * Name: int jz_mmc_exec_cmd() |
| 557 | + * Function: send command to the card, and get a response |
| 558 | + * Input: struct mmc_request *req : MMC/SD request |
| 559 | + * Output: 0: right >0: error code |
| 560 | + */ |
| 561 | +int jz_mmc_exec_cmd(struct mmc_request *request) |
| 562 | +{ |
| 563 | + u32 cmdat = 0, events = 0; |
| 564 | + int retval, timeout = 0x3fffff; |
| 565 | + |
| 566 | + /* Indicate we have no result yet */ |
| 567 | + request->result = MMC_NO_RESPONSE; |
| 568 | + if (request->cmd == MMC_CIM_RESET) { |
| 569 | + /* On reset, 1-bit bus width */ |
| 570 | + use_4bit = 0; |
| 571 | + |
| 572 | + /* Reset MMC/SD controller */ |
| 573 | + __msc_reset(); |
| 574 | + |
| 575 | + /* On reset, drop MMC clock down */ |
| 576 | + jz_mmc_set_clock(0, MMC_CLOCK_SLOW); |
| 577 | + |
| 578 | + /* On reset, stop MMC clock */ |
| 579 | + jz_mmc_stop_clock(); |
| 580 | + } |
| 581 | + if (request->cmd == MMC_CMD_SEND_OP_COND) { |
| 582 | + debug("Have an MMC card\n"); |
| 583 | + /* always use 1bit for MMC */ |
| 584 | + use_4bit = 0; |
| 585 | + } |
| 586 | + if (request->cmd == SET_BUS_WIDTH) { |
| 587 | + if (request->arg == 0x2) { |
| 588 | + printf("Use 4-bit bus width\n"); |
| 589 | + use_4bit = 1; |
| 590 | + } else { |
| 591 | + printf("Use 1-bit bus width\n"); |
| 592 | + use_4bit = 0; |
| 593 | + } |
| 594 | + } |
| 595 | + |
| 596 | + /* stop clock */ |
| 597 | + jz_mmc_stop_clock(); |
| 598 | + |
| 599 | + /* mask all interrupts */ |
| 600 | + REG_MSC_IMASK = 0xffff; |
| 601 | + |
| 602 | + /* clear status */ |
| 603 | + REG_MSC_IREG = 0xffff; |
| 604 | + |
| 605 | + /* use 4-bit bus width when possible */ |
| 606 | + if (use_4bit) |
| 607 | + cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT; |
| 608 | + |
| 609 | + /* Set command type and events */ |
| 610 | + switch (request->cmd) { |
| 611 | + /* MMC core extra command */ |
| 612 | + case MMC_CIM_RESET: |
| 613 | + cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */ |
| 614 | + break; |
| 615 | + |
| 616 | + /* bc - broadcast - no response */ |
| 617 | + case MMC_CMD_GO_IDLE_STATE: |
| 618 | + case MMC_CMD_SET_DSR: |
| 619 | + break; |
| 620 | + |
| 621 | + /* bcr - broadcast with response */ |
| 622 | + case MMC_CMD_SEND_OP_COND: |
| 623 | + case MMC_CMD_ALL_SEND_CID: |
| 624 | + case MMC_GO_IRQ_STATE: |
| 625 | + break; |
| 626 | + |
| 627 | + /* adtc - addressed with data transfer */ |
| 628 | + case MMC_READ_DAT_UNTIL_STOP: |
| 629 | + case MMC_CMD_READ_SINGLE_BLOCK: |
| 630 | + case MMC_CMD_READ_MULTIPLE_BLOCK: |
| 631 | + case SD_CMD_APP_SEND_SCR: |
| 632 | + cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ; |
| 633 | + events = MMC_EVENT_RX_DATA_DONE; |
| 634 | + break; |
| 635 | + |
| 636 | + case MMC_WRITE_DAT_UNTIL_STOP: |
| 637 | + case MMC_CMD_WRITE_SINGLE_BLOCK: |
| 638 | + case MMC_CMD_WRITE_MULTIPLE_BLOCK: |
| 639 | + case MMC_PROGRAM_CID: |
| 640 | + case MMC_PROGRAM_CSD: |
| 641 | + case MMC_SEND_WRITE_PROT: |
| 642 | + case MMC_GEN_CMD: |
| 643 | + case MMC_LOCK_UNLOCK: |
| 644 | + cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE; |
| 645 | + events = MMC_EVENT_TX_DATA_DONE | MMC_EVENT_PROG_DONE; |
| 646 | + |
| 647 | + break; |
| 648 | + |
| 649 | + case MMC_CMD_STOP_TRANSMISSION: |
| 650 | + events = MMC_EVENT_PROG_DONE; |
| 651 | + break; |
| 652 | + |
| 653 | + /* ac - no data transfer */ |
| 654 | + default: |
| 655 | + break; |
| 656 | + } |
| 657 | + |
| 658 | + /* Set response type */ |
| 659 | + switch (request->rtype) { |
| 660 | + case RESPONSE_NONE: |
| 661 | + break; |
| 662 | + |
| 663 | + case RESPONSE_R1B: |
| 664 | + cmdat |= MSC_CMDAT_BUSY; |
| 665 | + /*FALLTHRU*/ |
| 666 | + case RESPONSE_R1: |
| 667 | + cmdat |= MSC_CMDAT_RESPONSE_R1; |
| 668 | + break; |
| 669 | + case RESPONSE_R2_CID: |
| 670 | + case RESPONSE_R2_CSD: |
| 671 | + cmdat |= MSC_CMDAT_RESPONSE_R2; |
| 672 | + break; |
| 673 | + case RESPONSE_R3: |
| 674 | + cmdat |= MSC_CMDAT_RESPONSE_R3; |
| 675 | + break; |
| 676 | + case RESPONSE_R4: |
| 677 | + cmdat |= MSC_CMDAT_RESPONSE_R4; |
| 678 | + break; |
| 679 | + case RESPONSE_R5: |
| 680 | + cmdat |= MSC_CMDAT_RESPONSE_R5; |
| 681 | + break; |
| 682 | + case RESPONSE_R6: |
| 683 | + cmdat |= MSC_CMDAT_RESPONSE_R6; |
| 684 | + break; |
| 685 | + default: |
| 686 | + break; |
| 687 | + } |
| 688 | + |
| 689 | + /* Set command index */ |
| 690 | + if (request->cmd == MMC_CIM_RESET) { |
| 691 | + REG_MSC_CMD = MMC_CMD_GO_IDLE_STATE; |
| 692 | + } else { |
| 693 | + REG_MSC_CMD = request->cmd; |
| 694 | + } |
| 695 | + |
| 696 | + /* Set argument */ |
| 697 | + REG_MSC_ARG = request->arg; |
| 698 | + |
| 699 | + /* Set block length and nob */ |
| 700 | + if (request->cmd == SD_CMD_APP_SEND_SCR) { /* get SCR from DataFIFO */ |
| 701 | + REG_MSC_BLKLEN = 8; |
| 702 | + REG_MSC_NOB = 1; |
| 703 | + } else { |
| 704 | + REG_MSC_BLKLEN = request->block_len; |
| 705 | + REG_MSC_NOB = request->nob; |
| 706 | + } |
| 707 | + |
| 708 | + /* Set command */ |
| 709 | + REG_MSC_CMDAT = cmdat; |
| 710 | + |
| 711 | + debug("Send cmd %d cmdat: %x arg: %x resp %d\n", request->cmd, |
| 712 | + cmdat, request->arg, request->rtype); |
| 713 | + |
| 714 | + /* Start MMC/SD clock and send command to card */ |
| 715 | + jz_mmc_start_clock(); |
| 716 | + |
| 717 | + /* Wait for command completion */ |
| 718 | + while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES)) |
| 719 | + ; |
| 720 | + |
| 721 | + if (timeout == 0) |
| 722 | + return MMC_ERROR_TIMEOUT; |
| 723 | + |
| 724 | + REG_MSC_IREG = MSC_IREG_END_CMD_RES; /* clear flag */ |
| 725 | + |
| 726 | + /* Check for status */ |
| 727 | + retval = jz_mmc_check_status(request); |
| 728 | + if (retval) { |
| 729 | + return retval; |
| 730 | + } |
| 731 | + |
| 732 | + /* Complete command with no response */ |
| 733 | + if (request->rtype == RESPONSE_NONE) { |
| 734 | + return MMC_NO_ERROR; |
| 735 | + } |
| 736 | + |
| 737 | + /* Get response */ |
| 738 | + jz_mmc_get_response(request); |
| 739 | + |
| 740 | + /* Start data operation */ |
| 741 | + if (events & (MMC_EVENT_RX_DATA_DONE | MMC_EVENT_TX_DATA_DONE)) { |
| 742 | + if (events & MMC_EVENT_RX_DATA_DONE) { |
| 743 | + if (request->cmd == SD_CMD_APP_SEND_SCR) { |
| 744 | + /* SD card returns SCR register as data. |
| 745 | + MMC core expect it in the response buffer, |
| 746 | + after normal response. */ |
| 747 | + request->buffer = (u8 *)((u32)request->response + 5); |
| 748 | + } |
| 749 | + jz_mmc_receive_data(request); |
| 750 | + } |
| 751 | + |
| 752 | + if (events & MMC_EVENT_TX_DATA_DONE) { |
| 753 | + jz_mmc_transmit_data(request); |
| 754 | + } |
| 755 | + |
| 756 | + /* Wait for Data Done */ |
| 757 | + while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE)) |
| 758 | + ; |
| 759 | + REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */ |
| 760 | + } |
| 761 | + |
| 762 | + /* Wait for Prog Done event */ |
| 763 | + if (events & MMC_EVENT_PROG_DONE) { |
| 764 | + while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE)) |
| 765 | + ; |
| 766 | + REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */ |
| 767 | + } |
| 768 | + |
| 769 | + /* Command completed */ |
| 770 | + |
| 771 | + return MMC_NO_ERROR; /* return successfully */ |
| 772 | +} |
| 773 | + |
| 774 | +int mmc_block_read(u8 *dst, ulong src, ulong len) |
| 775 | +{ |
| 776 | + |
| 777 | + struct mmc_request request; |
| 778 | + struct mmc_response_r1 r1; |
| 779 | + int retval = 0; |
| 780 | + |
| 781 | + if (len == 0) |
| 782 | + goto exit; |
| 783 | + |
| 784 | + mmc_simple_cmd(&request, MMC_CMD_SEND_STATUS, mmcinfo.rca, RESPONSE_R1); |
| 785 | + retval = mmc_unpack_r1(&request, &r1, 0); |
| 786 | + if (retval && (retval != MMC_ERROR_STATE_MISMATCH)) |
| 787 | + goto exit; |
| 788 | + |
| 789 | + mmc_simple_cmd(&request, MMC_CMD_SET_BLOCKLEN, len, RESPONSE_R1); |
| 790 | + if (retval = mmc_unpack_r1(&request, &r1, 0)) |
| 791 | + goto exit; |
| 792 | + |
| 793 | + if (!sd2_0) |
| 794 | + src *= mmcinfo.block_len; |
| 795 | + |
| 796 | + mmc_send_cmd(&request, MMC_CMD_READ_SINGLE_BLOCK, src, 1, len, RESPONSE_R1, dst); |
| 797 | + if (retval = mmc_unpack_r1(&request, &r1, 0)) |
| 798 | + goto exit; |
| 799 | + |
| 800 | +exit: |
| 801 | + return retval; |
| 802 | +} |
| 803 | + |
| 804 | +ulong mmc_bread(int dev_num, ulong blkstart, ulong blkcnt, ulong *dst) |
| 805 | +{ |
| 806 | + if (!mmc_ready) { |
| 807 | + printf("Please initial the MMC first\n"); |
| 808 | + return -1; |
| 809 | + } |
| 810 | + |
| 811 | + int i = 0; |
| 812 | + ulong dst_tmp = dst; |
| 813 | + |
| 814 | + for (i = 0; i < blkcnt; i++) { |
| 815 | + if ((mmc_block_read((uchar *)(dst_tmp), blkstart, mmcinfo.block_len)) < 0) |
| 816 | + return -1; |
| 817 | + |
| 818 | + dst_tmp += mmcinfo.block_len; |
| 819 | + blkstart++; |
| 820 | + } |
| 821 | + |
| 822 | + return i; |
| 823 | +} |
| 824 | + |
| 825 | +int mmc_select_card(void) |
| 826 | +{ |
| 827 | + struct mmc_request request; |
| 828 | + struct mmc_response_r1 r1; |
| 829 | + int retval; |
| 830 | + |
| 831 | + mmc_simple_cmd(&request, MMC_CMD_SELECT_CARD, mmcinfo.rca, RESPONSE_R1B); |
| 832 | + retval = mmc_unpack_r1(&request, &r1, 0); |
| 833 | + if (retval) { |
| 834 | + return retval; |
| 835 | + } |
| 836 | + |
| 837 | + if (mmcinfo.sd) { |
| 838 | + mmc_simple_cmd(&request, MMC_CMD_APP_CMD, mmcinfo.rca, RESPONSE_R1); |
| 839 | + retval = mmc_unpack_r1(&request,&r1,0); |
| 840 | + if (retval) { |
| 841 | + return retval; |
| 842 | + } |
| 843 | +#if defined(MMC_BUS_WIDTH_1BIT) |
| 844 | + mmc_simple_cmd(&request, SET_BUS_WIDTH, 1, RESPONSE_R1); |
| 845 | +#else |
| 846 | + mmc_simple_cmd(&request, SET_BUS_WIDTH, 2, RESPONSE_R1); |
| 847 | +#endif |
| 848 | + retval = mmc_unpack_r1(&request,&r1,0); |
| 849 | + if (retval) { |
| 850 | + return retval; |
| 851 | + } |
| 852 | + } |
| 853 | + return 0; |
| 854 | +} |
| 855 | + |
| 856 | +/* |
| 857 | + * Configure card |
| 858 | + */ |
| 859 | +static void mmc_configure_card(void) |
| 860 | +{ |
| 861 | + u32 rate; |
| 862 | + |
| 863 | + /* Get card info */ |
| 864 | + if (sd2_0) |
| 865 | + mmcinfo.block_num = (mmcinfo.csd.c_size + 1) << 10; |
| 866 | + else |
| 867 | + mmcinfo.block_num = (mmcinfo.csd.c_size + 1) * (1 << (mmcinfo.csd.c_size_mult + 2)); |
| 868 | + |
| 869 | + mmcinfo.block_len = 1 << mmcinfo.csd.read_bl_len; |
| 870 | + |
| 871 | + mmc_dev.if_type = IF_TYPE_SD; |
| 872 | + mmc_dev.part_type = PART_TYPE_DOS; |
| 873 | + mmc_dev.dev = 0; |
| 874 | + mmc_dev.lun = 0; |
| 875 | + mmc_dev.type = 0; |
| 876 | + mmc_dev.blksz = mmcinfo.block_len; |
| 877 | + mmc_dev.lba = mmcinfo.block_num; |
| 878 | + mmc_dev.removable = 0; |
| 879 | + |
| 880 | + printf("%s Detected: %lu blocks of %lu bytes\n", |
| 881 | + sd2_0 == 1 ? "SDHC" : "SD", |
| 882 | + mmc_dev.lba, |
| 883 | + mmc_dev.blksz); |
| 884 | + |
| 885 | + /* Fix the clock rate */ |
| 886 | + rate = mmc_tran_speed(mmcinfo.csd.tran_speed); |
| 887 | + if (rate < MMC_CLOCK_SLOW) |
| 888 | + rate = MMC_CLOCK_SLOW; |
| 889 | + if ((mmcinfo.sd == 0) && (rate > MMC_CLOCK_FAST)) |
| 890 | + rate = MMC_CLOCK_FAST; |
| 891 | + if ((mmcinfo.sd) && (rate > SD_CLOCK_FAST)) |
| 892 | + rate = SD_CLOCK_FAST; |
| 893 | + |
| 894 | + debug("%s: block_len=%d block_num=%d rate=%d\n", |
| 895 | + __func__, mmcinfo.block_len, mmcinfo.block_num, rate); |
| 896 | + |
| 897 | + jz_mmc_set_clock(mmcinfo.sd, rate); |
| 898 | +} |
| 899 | + |
| 900 | +/* |
| 901 | + * State machine routines to initialize card(s) |
| 902 | + */ |
| 903 | + |
| 904 | +/* |
| 905 | + CIM_SINGLE_CARD_ACQ (frequency at 400 kHz) |
| 906 | + --- Must enter from GO_IDLE_STATE --- |
| 907 | + 1. SD_SEND_OP_COND (SD Card) [CMD55] + [CMD41] |
| 908 | + 2. SEND_OP_COND (Full Range) [CMD1] {optional} |
| 909 | + 3. SEND_OP_COND (Set Range ) [CMD1] |
| 910 | + If busy, delay and repeat step 2 |
| 911 | + 4. ALL_SEND_CID [CMD2] |
| 912 | + If timeout, set an error (no cards found) |
| 913 | + 5. SET_RELATIVE_ADDR [CMD3] |
| 914 | + 6. SEND_CSD [CMD9] |
| 915 | + 7. SET_DSR [CMD4] Only call this if (csd.dsr_imp). |
| 916 | + 8. Set clock frequency (check available in csd.tran_speed) |
| 917 | + */ |
| 918 | + |
| 919 | +#define MMC_INIT_DOING 0 |
| 920 | +#define MMC_INIT_PASSED 1 |
| 921 | +#define MMC_INIT_FAILED 2 |
| 922 | + |
| 923 | +static int mmc_init_card_state(struct mmc_request *request) |
| 924 | +{ |
| 925 | + struct mmc_response_r1 r1; |
| 926 | + struct mmc_response_r3 r3; |
| 927 | + int retval; |
| 928 | + int ocr = 0x40300000; |
| 929 | + int limit_41 = 0; |
| 930 | + |
| 931 | + switch (request->cmd) { |
| 932 | + case MMC_CMD_GO_IDLE_STATE: /* No response to parse */ |
| 933 | + if (mmcinfo.sd) |
| 934 | + mmc_simple_cmd(request, 8, 0x1aa, RESPONSE_R1); |
| 935 | + else |
| 936 | + mmc_simple_cmd(request, MMC_CMD_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3); |
| 937 | + break; |
| 938 | + |
| 939 | + case 8: |
| 940 | + retval = mmc_unpack_r1(request,&r1,mmcinfo.state); |
| 941 | + mmc_simple_cmd(request, MMC_CMD_APP_CMD, 0, RESPONSE_R1); |
| 942 | + break; |
| 943 | + |
| 944 | + case MMC_CMD_APP_CMD: |
| 945 | + retval = mmc_unpack_r1(request,&r1,mmcinfo.state); |
| 946 | + if (retval & (limit_41 < 100)) { |
| 947 | + debug("%s: unable to MMC_APP_CMD error=%d (%s)\n", |
| 948 | + __func__, retval, mmc_result_to_string(retval)); |
| 949 | + limit_41++; |
| 950 | + mmc_simple_cmd(request, SD_CMD_APP_SEND_OP_COND, ocr, RESPONSE_R3); |
| 951 | + } else if (limit_41 < 100) { |
| 952 | + limit_41++; |
| 953 | + mmc_simple_cmd(request, SD_CMD_APP_SEND_OP_COND, ocr, RESPONSE_R3); |
| 954 | + } else{ |
| 955 | + /* reset the card to idle*/ |
| 956 | + mmc_simple_cmd(request, MMC_CMD_GO_IDLE_STATE, 0, RESPONSE_NONE); |
| 957 | + mmcinfo.sd = 0; |
| 958 | + } |
| 959 | + break; |
| 960 | + |
| 961 | + case SD_CMD_APP_SEND_OP_COND: |
| 962 | + retval = mmc_unpack_r3(request, &r3); |
| 963 | + if (retval) { |
| 964 | + debug("%s: try MMC card\n", __func__); |
| 965 | + mmc_simple_cmd(request, SD_CMD_APP_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3); |
| 966 | + break; |
| 967 | + } |
| 968 | + |
| 969 | + debug("%s: read ocr value = 0x%08x\n", __func__, r3.ocr); |
| 970 | + |
| 971 | + if(!(r3.ocr & MMC_CARD_BUSY || ocr == 0)){ |
| 972 | + udelay(50000); |
| 973 | + mmc_simple_cmd(request, MMC_CMD_APP_CMD, 0, RESPONSE_R1); |
| 974 | + } else { |
| 975 | + mmcinfo.sd = 1; /* SD Card ready */ |
| 976 | + mmcinfo.state = CARD_STATE_READY; |
| 977 | + mmc_simple_cmd(request, MMC_CMD_ALL_SEND_CID, 0, RESPONSE_R2_CID); |
| 978 | + } |
| 979 | + break; |
| 980 | + |
| 981 | + case MMC_CMD_SEND_OP_COND: |
| 982 | + retval = mmc_unpack_r3(request, &r3); |
| 983 | + if (retval) { |
| 984 | + debug("%s: failed SEND_OP_COND error=%d (%s)\n", |
| 985 | + __func__, retval, mmc_result_to_string(retval)); |
| 986 | + return MMC_INIT_FAILED; |
| 987 | + } |
| 988 | + |
| 989 | + debug("%s: read ocr value = 0x%08x\n", __func__, r3.ocr); |
| 990 | + if (!(r3.ocr & MMC_CARD_BUSY)) { |
| 991 | + mmc_simple_cmd(request, MMC_CMD_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3); |
| 992 | + } else { |
| 993 | + mmcinfo.sd = 0; /* MMC Card ready */ |
| 994 | + mmcinfo.state = CARD_STATE_READY; |
| 995 | + mmc_simple_cmd(request, MMC_CMD_ALL_SEND_CID, 0, RESPONSE_R2_CID); |
| 996 | + } |
| 997 | + break; |
| 998 | + |
| 999 | + case MMC_CMD_ALL_SEND_CID: |
| 1000 | + retval = mmc_unpack_cid( request, &mmcinfo.cid ); |
| 1001 | + /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */ |
| 1002 | + if ( retval && (retval != MMC_ERROR_CRC)) { |
| 1003 | + debug("mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n", |
| 1004 | + retval, mmc_result_to_string(retval)); |
| 1005 | + return MMC_INIT_FAILED; |
| 1006 | + } |
| 1007 | + mmcinfo.state = CARD_STATE_IDENT; |
| 1008 | + if(mmcinfo.sd) |
| 1009 | + mmc_simple_cmd(request, MMC_CMD_SET_RELATIVE_ADDR, 0, RESPONSE_R6); |
| 1010 | + else |
| 1011 | + mmc_simple_cmd(request, MMC_CMD_SET_RELATIVE_ADDR, ID_TO_RCA(mmcinfo.id) << 16, RESPONSE_R1); |
| 1012 | + break; |
| 1013 | + |
| 1014 | + case MMC_CMD_SET_RELATIVE_ADDR: |
| 1015 | + if (mmcinfo.sd) { |
| 1016 | + retval = mmc_unpack_r6(request, &r1, mmcinfo.state, &mmcinfo.rca); |
| 1017 | + mmcinfo.rca = mmcinfo.rca << 16; |
| 1018 | + debug("%s: Get RCA from SD: 0x%04x Status: %x\n", |
| 1019 | + __func__, mmcinfo.rca, r1.status); |
| 1020 | + } else { |
| 1021 | + retval = mmc_unpack_r1(request,&r1,mmcinfo.state); |
| 1022 | + mmcinfo.rca = ID_TO_RCA(mmcinfo.id) << 16; |
| 1023 | + } |
| 1024 | + if (retval) { |
| 1025 | + debug("%s: unable to SET_RELATIVE_ADDR error=%d (%s)\n", |
| 1026 | + __func__, retval, mmc_result_to_string(retval)); |
| 1027 | + return MMC_INIT_FAILED; |
| 1028 | + } |
| 1029 | + |
| 1030 | + mmcinfo.state = CARD_STATE_STBY; |
| 1031 | + mmc_simple_cmd(request, MMC_CMD_SEND_CSD, mmcinfo.rca, RESPONSE_R2_CSD); |
| 1032 | + |
| 1033 | + break; |
| 1034 | + |
| 1035 | + case MMC_CMD_SEND_CSD: |
| 1036 | + retval = mmc_unpack_csd(request, &mmcinfo.csd); |
| 1037 | + mmc_ready = 1; |
| 1038 | + /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */ |
| 1039 | + if (retval && (retval != MMC_ERROR_CRC)) { |
| 1040 | + debug("%s: unable to SEND_CSD error=%d (%s)\n", |
| 1041 | + __func__, retval, mmc_result_to_string(retval)); |
| 1042 | + return MMC_INIT_FAILED; |
| 1043 | + } |
| 1044 | + if (mmcinfo.csd.dsr_imp) { |
| 1045 | + debug("%s: driver doesn't support setting DSR\n", __func__); |
| 1046 | + } |
| 1047 | + mmc_configure_card(); |
| 1048 | + return MMC_INIT_PASSED; |
| 1049 | + |
| 1050 | + default: |
| 1051 | + debug("%s: error! Illegal last cmd %d\n", __func__, request->cmd); |
| 1052 | + return MMC_INIT_FAILED; |
| 1053 | + } |
| 1054 | + |
| 1055 | + return MMC_INIT_DOING; |
| 1056 | +} |
| 1057 | + |
| 1058 | +int mmc_init_card(void) |
| 1059 | +{ |
| 1060 | + struct mmc_request request; |
| 1061 | + int retval; |
| 1062 | + |
| 1063 | + mmc_simple_cmd(&request, MMC_CIM_RESET, 0, RESPONSE_NONE); /* reset card */ |
| 1064 | + mmc_simple_cmd(&request, MMC_CMD_GO_IDLE_STATE, 0, RESPONSE_NONE); |
| 1065 | + mmcinfo.sd = 1; /* assuming a SD card */ |
| 1066 | + |
| 1067 | + while ((retval = mmc_init_card_state(&request)) == MMC_INIT_DOING) |
| 1068 | + ; |
| 1069 | + |
| 1070 | + if (retval == MMC_INIT_PASSED) |
| 1071 | + return MMC_NO_ERROR; |
| 1072 | + else |
| 1073 | + return MMC_NO_RESPONSE; |
| 1074 | +} |
| 1075 | + |
| 1076 | +int mmc_legacy_init(int verbose) |
| 1077 | +{ |
| 1078 | + if (!__msc_card_detected()) |
| 1079 | + return 1; |
| 1080 | + |
| 1081 | + /* Step-1: init GPIO */ |
| 1082 | + __gpio_as_msc(); |
| 1083 | + __msc_init_io(); |
| 1084 | + |
| 1085 | + /* Step-2: turn on power of card */ |
| 1086 | +#if !defined(CONFIG_SAKC) |
| 1087 | + __msc_enable_power(); |
| 1088 | +#endif |
| 1089 | + |
| 1090 | + /* Step-3: Reset MSC Controller. */ |
| 1091 | + __msc_reset(); |
| 1092 | + |
| 1093 | + /* Step-3: mask all IRQs. */ |
| 1094 | + MMC_IRQ_MASK(); |
| 1095 | + |
| 1096 | + /* Step-4: stop MMC/SD clock */ |
| 1097 | + jz_mmc_stop_clock(); |
| 1098 | + mmc_init_card(); |
| 1099 | + mmc_select_card(); |
| 1100 | + |
| 1101 | + mmc_dev.block_read = mmc_bread; |
| 1102 | + fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ |
| 1103 | + |
| 1104 | + return 0; |
| 1105 | +} |
| 1106 | + |
| 1107 | +/* |
| 1108 | + * Debugging functions |
| 1109 | + */ |
| 1110 | +static char * mmc_result_strings[] = { |
| 1111 | + "NO_RESPONSE", |
| 1112 | + "NO_ERROR", |
| 1113 | + "ERROR_OUT_OF_RANGE", |
| 1114 | + "ERROR_ADDRESS", |
| 1115 | + "ERROR_BLOCK_LEN", |
| 1116 | + "ERROR_ERASE_SEQ", |
| 1117 | + "ERROR_ERASE_PARAM", |
| 1118 | + "ERROR_WP_VIOLATION", |
| 1119 | + "ERROR_CARD_IS_LOCKED", |
| 1120 | + "ERROR_LOCK_UNLOCK_FAILED", |
| 1121 | + "ERROR_COM_CRC", |
| 1122 | + "ERROR_ILLEGAL_COMMAND", |
| 1123 | + "ERROR_CARD_ECC_FAILED", |
| 1124 | + "ERROR_CC", |
| 1125 | + "ERROR_GENERAL", |
| 1126 | + "ERROR_UNDERRUN", |
| 1127 | + "ERROR_OVERRUN", |
| 1128 | + "ERROR_CID_CSD_OVERWRITE", |
| 1129 | + "ERROR_STATE_MISMATCH", |
| 1130 | + "ERROR_HEADER_MISMATCH", |
| 1131 | + "ERROR_TIMEOUT", |
| 1132 | + "ERROR_CRC", |
| 1133 | + "ERROR_DRIVER_FAILURE", |
| 1134 | +}; |
| 1135 | + |
| 1136 | +char * mmc_result_to_string(int i) |
| 1137 | +{ |
| 1138 | + return mmc_result_strings[i+1]; |
| 1139 | +} |
| 1140 | + |
| 1141 | +static char * card_state_strings[] = { |
| 1142 | + "empty", |
| 1143 | + "idle", |
| 1144 | + "ready", |
| 1145 | + "ident", |
| 1146 | + "stby", |
| 1147 | + "tran", |
| 1148 | + "data", |
| 1149 | + "rcv", |
| 1150 | + "prg", |
| 1151 | + "dis", |
| 1152 | +}; |
| 1153 | + |
| 1154 | +static inline char * card_state_to_string(int i) |
| 1155 | +{ |
| 1156 | + return card_state_strings[i+1]; |
| 1157 | +} |
| 1158 | + |
| 1159 | +/* |
| 1160 | + * Utility functions |
| 1161 | + */ |
| 1162 | + |
| 1163 | +#define PARSE_U32(_buf,_index) \ |
| 1164 | + (((u32)_buf[_index]) << 24) | (((u32)_buf[_index+1]) << 16) | \ |
| 1165 | + (((u32)_buf[_index+2]) << 8) | ((u32)_buf[_index+3]); |
| 1166 | + |
| 1167 | +#define PARSE_U16(_buf,_index) \ |
| 1168 | + (((u16)_buf[_index]) << 8) | ((u16)_buf[_index+1]); |
| 1169 | + |
| 1170 | +int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd) |
| 1171 | +{ |
| 1172 | + u8 *buf = request->response; |
| 1173 | + int num = 0; |
| 1174 | + |
| 1175 | + if (request->result) |
| 1176 | + return request->result; |
| 1177 | + |
| 1178 | + if (buf[0] != 0x3f) |
| 1179 | + return MMC_ERROR_HEADER_MISMATCH; |
| 1180 | + |
| 1181 | + csd->csd_structure = (buf[1] & 0xc0) >> 6; |
| 1182 | + if (csd->csd_structure) |
| 1183 | + sd2_0 = 1; |
| 1184 | + else |
| 1185 | + sd2_0 = 0; |
| 1186 | + |
| 1187 | + switch (csd->csd_structure) { |
| 1188 | + case 0 :/* Version 1.01-1.10 |
| 1189 | + * Version 2.00/Standard Capacity */ |
| 1190 | + csd->taac = buf[2]; |
| 1191 | + csd->nsac = buf[3]; |
| 1192 | + csd->tran_speed = buf[4]; |
| 1193 | + csd->ccc = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4); |
| 1194 | + csd->read_bl_len = buf[6] & 0x0f; |
| 1195 | + /* for support 2GB card*/ |
| 1196 | + if (csd->read_bl_len >= 10) |
| 1197 | + { |
| 1198 | + num = csd->read_bl_len - 9; |
| 1199 | + csd->read_bl_len = 9; |
| 1200 | + } |
| 1201 | + |
| 1202 | + csd->read_bl_partial = (buf[7] & 0x80) ? 1 : 0; |
| 1203 | + csd->write_blk_misalign = (buf[7] & 0x40) ? 1 : 0; |
| 1204 | + csd->read_blk_misalign = (buf[7] & 0x20) ? 1 : 0; |
| 1205 | + csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0; |
| 1206 | + csd->c_size = ((((u16)buf[7]) & 0x03) << 10) | (((u16)buf[8]) << 2) | (((u16)buf[9]) & 0xc0) >> 6; |
| 1207 | + |
| 1208 | + if (num) |
| 1209 | + csd->c_size = csd->c_size << num; |
| 1210 | + |
| 1211 | + |
| 1212 | + csd->vdd_r_curr_min = (buf[9] & 0x38) >> 3; |
| 1213 | + csd->vdd_r_curr_max = buf[9] & 0x07; |
| 1214 | + csd->vdd_w_curr_min = (buf[10] & 0xe0) >> 5; |
| 1215 | + csd->vdd_w_curr_max = (buf[10] & 0x1c) >> 2; |
| 1216 | + csd->c_size_mult = ((buf[10] & 0x03) << 1) | ((buf[11] & 0x80) >> 7); |
| 1217 | + csd->sector_size = (buf[11] & 0x7c) >> 2; |
| 1218 | + csd->erase_grp_size = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5); |
| 1219 | + csd->wp_grp_size = buf[12] & 0x1f; |
| 1220 | + csd->wp_grp_enable = (buf[13] & 0x80) ? 1 : 0; |
| 1221 | + csd->default_ecc = (buf[13] & 0x60) >> 5; |
| 1222 | + csd->r2w_factor = (buf[13] & 0x1c) >> 2; |
| 1223 | + csd->write_bl_len = ((buf[13] & 0x03) << 2) | ((buf[14] & 0xc0) >> 6); |
| 1224 | + if (csd->write_bl_len >= 10) |
| 1225 | + csd->write_bl_len = 9; |
| 1226 | + |
| 1227 | + csd->write_bl_partial = (buf[14] & 0x20) ? 1 : 0; |
| 1228 | + csd->file_format_grp = (buf[15] & 0x80) ? 1 : 0; |
| 1229 | + csd->copy = (buf[15] & 0x40) ? 1 : 0; |
| 1230 | + csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0; |
| 1231 | + csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0; |
| 1232 | + csd->file_format = (buf[15] & 0x0c) >> 2; |
| 1233 | + csd->ecc = buf[15] & 0x03; |
| 1234 | + break; |
| 1235 | + case 1 : /* Version 2.00/High Capacity */ |
| 1236 | + csd->taac = 0; |
| 1237 | + csd->nsac = 0; |
| 1238 | + csd->tran_speed = buf[4]; |
| 1239 | + csd->ccc = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4); |
| 1240 | + |
| 1241 | + csd->read_bl_len = 9; |
| 1242 | + csd->read_bl_partial = 0; |
| 1243 | + csd->write_blk_misalign = 0; |
| 1244 | + csd->read_blk_misalign = 0; |
| 1245 | + csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0; |
| 1246 | + csd->c_size = ((((u16)buf[8]) & 0x3f) << 16) | (((u16)buf[9]) << 8) | ((u16)buf[10]) ; |
| 1247 | + csd->sector_size = 0x7f; |
| 1248 | + csd->erase_grp_size = 0; |
| 1249 | + csd->wp_grp_size = 0; |
| 1250 | + csd->wp_grp_enable = 0; |
| 1251 | + csd->default_ecc = (buf[13] & 0x60) >> 5; |
| 1252 | + csd->r2w_factor = 4;/* Unused */ |
| 1253 | + csd->write_bl_len = 9; |
| 1254 | + |
| 1255 | + csd->write_bl_partial = 0; |
| 1256 | + csd->file_format_grp = 0; |
| 1257 | + csd->copy = (buf[15] & 0x40) ? 1 : 0; |
| 1258 | + csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0; |
| 1259 | + csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0; |
| 1260 | + csd->file_format = 0; |
| 1261 | + csd->ecc = buf[15] & 0x03; |
| 1262 | + } |
| 1263 | + |
| 1264 | + return 0; |
| 1265 | +} |
| 1266 | + |
| 1267 | +int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state) |
| 1268 | +{ |
| 1269 | + u8 *buf = request->response; |
| 1270 | + |
| 1271 | + if (request->result) |
| 1272 | + return request->result; |
| 1273 | + |
| 1274 | + r1->cmd = buf[0]; |
| 1275 | + r1->status = PARSE_U32(buf,1); |
| 1276 | + |
| 1277 | + debug("mmc_unpack_r1: cmd=%d status=%08x\n", r1->cmd, r1->status); |
| 1278 | + |
| 1279 | + if (R1_STATUS(r1->status)) { |
| 1280 | + if (r1->status & R1_OUT_OF_RANGE) return MMC_ERROR_OUT_OF_RANGE; |
| 1281 | + if (r1->status & R1_ADDRESS_ERROR) return MMC_ERROR_ADDRESS; |
| 1282 | + if (r1->status & R1_BLOCK_LEN_ERROR) return MMC_ERROR_BLOCK_LEN; |
| 1283 | + if (r1->status & R1_ERASE_SEQ_ERROR) return MMC_ERROR_ERASE_SEQ; |
| 1284 | + if (r1->status & R1_ERASE_PARAM) return MMC_ERROR_ERASE_PARAM; |
| 1285 | + if (r1->status & R1_WP_VIOLATION) return MMC_ERROR_WP_VIOLATION; |
| 1286 | + /*if (r1->status & R1_CARD_IS_LOCKED) return MMC_ERROR_CARD_IS_LOCKED; */ |
| 1287 | + if (r1->status & R1_LOCK_UNLOCK_FAILED) return MMC_ERROR_LOCK_UNLOCK_FAILED; |
| 1288 | + if (r1->status & R1_COM_CRC_ERROR) return MMC_ERROR_COM_CRC; |
| 1289 | + if (r1->status & R1_ILLEGAL_COMMAND) return MMC_ERROR_ILLEGAL_COMMAND; |
| 1290 | + if (r1->status & R1_CARD_ECC_FAILED) return MMC_ERROR_CARD_ECC_FAILED; |
| 1291 | + if (r1->status & R1_CC_ERROR) return MMC_ERROR_CC; |
| 1292 | + if (r1->status & R1_ERROR) return MMC_ERROR_GENERAL; |
| 1293 | + if (r1->status & R1_UNDERRUN) return MMC_ERROR_UNDERRUN; |
| 1294 | + if (r1->status & R1_OVERRUN) return MMC_ERROR_OVERRUN; |
| 1295 | + if (r1->status & R1_CID_CSD_OVERWRITE) return MMC_ERROR_CID_CSD_OVERWRITE; |
| 1296 | + } |
| 1297 | + |
| 1298 | + if (buf[0] != request->cmd) |
| 1299 | + return MMC_ERROR_HEADER_MISMATCH; |
| 1300 | + |
| 1301 | + /* This should be last - it's the least dangerous error */ |
| 1302 | + |
| 1303 | + return 0; |
| 1304 | +} |
| 1305 | + |
| 1306 | +int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr) |
| 1307 | +{ |
| 1308 | + u8 *buf = request->response; |
| 1309 | + if (request->result) |
| 1310 | + return request->result; |
| 1311 | + |
| 1312 | + *scr = PARSE_U32(buf, 5); /* Save SCR returned by the SD Card */ |
| 1313 | + return mmc_unpack_r1(request, r1, state); |
| 1314 | + |
| 1315 | +} |
| 1316 | + |
| 1317 | +int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca) |
| 1318 | +{ |
| 1319 | + u8 *buf = request->response; |
| 1320 | + |
| 1321 | + if (request->result) |
| 1322 | + return request->result; |
| 1323 | + |
| 1324 | + *rca = PARSE_U16(buf,1); /* Save RCA returned by the SD Card */ |
| 1325 | + |
| 1326 | + *(buf+1) = 0; |
| 1327 | + *(buf+2) = 0; |
| 1328 | + |
| 1329 | + return mmc_unpack_r1(request, r1, state); |
| 1330 | +} |
| 1331 | + |
| 1332 | +int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid) |
| 1333 | +{ |
| 1334 | + int i; |
| 1335 | + u8 *buf = request->response; |
| 1336 | + |
| 1337 | + if (request->result) |
| 1338 | + return request->result; |
| 1339 | + |
| 1340 | + cid->mid = buf[1]; |
| 1341 | + cid->oid = PARSE_U16(buf,2); |
| 1342 | + for (i = 0 ; i < 5 ; i++) |
| 1343 | + cid->pnm[i] = buf[4+i]; |
| 1344 | + cid->pnm[6] = 0; |
| 1345 | + cid->prv = buf[10]; |
| 1346 | + cid->psn = PARSE_U32(buf,10); |
| 1347 | + cid->mdt = buf[15]; |
| 1348 | + |
| 1349 | + printf("Man %02x OEM 0x%04x \"%s\" %d.%d 0x%08x " |
| 1350 | + "Date %02u/%04u\n", |
| 1351 | + cid->mid, |
| 1352 | + cid->oid, |
| 1353 | + cid->pnm, |
| 1354 | + cid->prv >> 4, |
| 1355 | + cid->prv & 0xf, |
| 1356 | + cid->psn, |
| 1357 | + cid->mdt & 0xf, |
| 1358 | + (cid->mdt >> 4) + 2000); |
| 1359 | + |
| 1360 | + if (buf[0] != 0x3f) |
| 1361 | + return MMC_ERROR_HEADER_MISMATCH; |
| 1362 | + return 0; |
| 1363 | +} |
| 1364 | + |
| 1365 | +int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3) |
| 1366 | +{ |
| 1367 | + u8 *buf = request->response; |
| 1368 | + |
| 1369 | + if (request->result) |
| 1370 | + return request->result; |
| 1371 | + |
| 1372 | + r3->ocr = PARSE_U32(buf,1); |
| 1373 | + debug("mmc_unpack_r3: ocr=%08x\n", r3->ocr); |
| 1374 | + |
| 1375 | + if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH; |
| 1376 | + return 0; |
| 1377 | +} |
| 1378 | + |
| 1379 | +#define KBPS 1 |
| 1380 | +#define MBPS 1000 |
| 1381 | + |
| 1382 | +static u32 ts_exp[] = { 100*KBPS, 1*MBPS, 10*MBPS, 100*MBPS, 0, 0, 0, 0 }; |
| 1383 | +static u32 ts_mul[] = { 0, 1000, 1200, 1300, 1500, 2000, 2500, 3000, |
| 1384 | + 3500, 4000, 4500, 5000, 5500, 6000, 7000, 8000 }; |
| 1385 | + |
| 1386 | +u32 mmc_tran_speed(u8 ts) |
| 1387 | +{ |
| 1388 | + u32 rate = ts_exp[(ts & 0x7)] * ts_mul[(ts & 0x78) >> 3]; |
| 1389 | + |
| 1390 | + if (rate <= 0) { |
| 1391 | + debug("%s: error - unrecognized speed 0x%02x\n", __func__, ts); |
| 1392 | + return 1; |
| 1393 | + } |
| 1394 | + |
| 1395 | + return rate; |
| 1396 | +} |
| 1397 | + |
| 1398 | +void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg, |
| 1399 | + u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer) |
| 1400 | +{ |
| 1401 | + request->cmd = cmd; |
| 1402 | + request->arg = arg; |
| 1403 | + request->rtype = rtype; |
| 1404 | + request->nob = nob; |
| 1405 | + request->block_len = block_len; |
| 1406 | + request->buffer = buffer; |
| 1407 | + request->cnt = nob * block_len; |
| 1408 | + |
| 1409 | + jz_mmc_exec_cmd(request); |
| 1410 | +} |
| 1411 | diff --git a/drivers/mmc/jz_mmc.h b/drivers/mmc/jz_mmc.h |
| 1412 | new file mode 100644 |
| 1413 | index 0000000..936c514 |
| 1414 | --- /dev/null |
| 1415 | +++ b/drivers/mmc/jz_mmc.h |
| 1416 | @@ -0,0 +1,176 @@ |
| 1417 | +/* |
| 1418 | + * linux/drivers/mmc/jz_mmc.h |
| 1419 | + * |
| 1420 | + * Author: Vladimir Shebordaev, Igor Oblakov |
| 1421 | + * Copyright: MontaVista Software Inc. |
| 1422 | + * |
| 1423 | + * $Id: jz_mmc.h,v 1.3 2007-06-15 08:04:20 jlwei Exp $ |
| 1424 | + * |
| 1425 | + * This program is free software; you can redistribute it and/or modify |
| 1426 | + * it under the terms of the GNU General Public License version 2 as |
| 1427 | + * published by the Free Software Foundation. |
| 1428 | + */ |
| 1429 | +#ifndef __MMC_JZMMC_H__ |
| 1430 | +#define __MMC_JZMMC_H__ |
| 1431 | + |
| 1432 | +#define ID_TO_RCA(x) ((x)+1) |
| 1433 | +#define MMC_OCR_ARG 0x00ff8000 /* Argument of OCR */ |
| 1434 | + |
| 1435 | +/* Standard MMC/SD clock speeds */ |
| 1436 | +#define MMC_CLOCK_SLOW 400000 /* 400 kHz for initial setup */ |
| 1437 | +#define MMC_CLOCK_FAST 20000000 /* 20 MHz for maximum for normal operation */ |
| 1438 | +#define SD_CLOCK_FAST 24000000 /* 24 MHz for SD Cards */ |
| 1439 | + |
| 1440 | +/* Use negative numbers to disambiguate */ |
| 1441 | +#define MMC_CIM_RESET -1 |
| 1442 | +#define SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ |
| 1443 | + |
| 1444 | +#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ |
| 1445 | +#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ |
| 1446 | +#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ |
| 1447 | +#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ |
| 1448 | +#define R1_ERASE_PARAM (1 << 27) /* ex, c */ |
| 1449 | +#define R1_WP_VIOLATION (1 << 26) /* erx, c */ |
| 1450 | +#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ |
| 1451 | +#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ |
| 1452 | +#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ |
| 1453 | +#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ |
| 1454 | +#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ |
| 1455 | +#define R1_CC_ERROR (1 << 20) /* erx, c */ |
| 1456 | +#define R1_ERROR (1 << 19) /* erx, c */ |
| 1457 | +#define R1_UNDERRUN (1 << 18) /* ex, c */ |
| 1458 | +#define R1_OVERRUN (1 << 17) /* ex, c */ |
| 1459 | +#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ |
| 1460 | +#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ |
| 1461 | +#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ |
| 1462 | +#define R1_ERASE_RESET (1 << 13) /* sr, c */ |
| 1463 | +#define R1_STATUS(x) (x & 0xFFFFE000) |
| 1464 | + |
| 1465 | +#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ |
| 1466 | + |
| 1467 | +#define MMC_PROGRAM_CID 26 /* adtc R1 */ |
| 1468 | +#define MMC_PROGRAM_CSD 27 /* adtc R1 */ |
| 1469 | + |
| 1470 | +#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ |
| 1471 | +#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */ |
| 1472 | +#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ |
| 1473 | +#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ |
| 1474 | +#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ |
| 1475 | +#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ |
| 1476 | + |
| 1477 | + |
| 1478 | +enum mmc_result_t { |
| 1479 | + MMC_NO_RESPONSE = -1, |
| 1480 | + MMC_NO_ERROR = 0, |
| 1481 | + MMC_ERROR_OUT_OF_RANGE, |
| 1482 | + MMC_ERROR_ADDRESS, |
| 1483 | + MMC_ERROR_BLOCK_LEN, |
| 1484 | + MMC_ERROR_ERASE_SEQ, |
| 1485 | + MMC_ERROR_ERASE_PARAM, |
| 1486 | + MMC_ERROR_WP_VIOLATION, |
| 1487 | + MMC_ERROR_CARD_IS_LOCKED, |
| 1488 | + MMC_ERROR_LOCK_UNLOCK_FAILED, |
| 1489 | + MMC_ERROR_COM_CRC, |
| 1490 | + MMC_ERROR_ILLEGAL_COMMAND, |
| 1491 | + MMC_ERROR_CARD_ECC_FAILED, |
| 1492 | + MMC_ERROR_CC, |
| 1493 | + MMC_ERROR_GENERAL, |
| 1494 | + MMC_ERROR_UNDERRUN, |
| 1495 | + MMC_ERROR_OVERRUN, |
| 1496 | + MMC_ERROR_CID_CSD_OVERWRITE, |
| 1497 | + MMC_ERROR_STATE_MISMATCH, |
| 1498 | + MMC_ERROR_HEADER_MISMATCH, |
| 1499 | + MMC_ERROR_TIMEOUT, |
| 1500 | + MMC_ERROR_CRC, |
| 1501 | + MMC_ERROR_DRIVER_FAILURE, |
| 1502 | +}; |
| 1503 | + |
| 1504 | +enum card_state { |
| 1505 | + CARD_STATE_EMPTY = -1, |
| 1506 | + CARD_STATE_IDLE = 0, |
| 1507 | + CARD_STATE_READY = 1, |
| 1508 | + CARD_STATE_IDENT = 2, |
| 1509 | + CARD_STATE_STBY = 3, |
| 1510 | + CARD_STATE_TRAN = 4, |
| 1511 | + CARD_STATE_DATA = 5, |
| 1512 | + CARD_STATE_RCV = 6, |
| 1513 | + CARD_STATE_PRG = 7, |
| 1514 | + CARD_STATE_DIS = 8, |
| 1515 | +}; |
| 1516 | + |
| 1517 | +enum mmc_rsp_t { |
| 1518 | + RESPONSE_NONE = 0, |
| 1519 | + RESPONSE_R1 = 1, |
| 1520 | + RESPONSE_R1B = 2, |
| 1521 | + RESPONSE_R2_CID = 3, |
| 1522 | + RESPONSE_R2_CSD = 4, |
| 1523 | + RESPONSE_R3 = 5, |
| 1524 | + RESPONSE_R4 = 6, |
| 1525 | + RESPONSE_R5 = 7, |
| 1526 | + RESPONSE_R6 = 8, |
| 1527 | +}; |
| 1528 | + |
| 1529 | +struct mmc_response_r1 { |
| 1530 | + u8 cmd; |
| 1531 | + u32 status; |
| 1532 | +}; |
| 1533 | + |
| 1534 | +struct mmc_response_r3 { |
| 1535 | + u32 ocr; |
| 1536 | +}; |
| 1537 | + |
| 1538 | +/* the information structure of MMC/SD Card */ |
| 1539 | +struct mmc_info { |
| 1540 | + int id; /* Card index */ |
| 1541 | + int sd; /* MMC or SD card */ |
| 1542 | + int rca; /* RCA */ |
| 1543 | + u32 scr; /* SCR 63:32*/ |
| 1544 | + int flags; /* Ejected, inserted */ |
| 1545 | + enum card_state state; /* empty, ident, ready, whatever */ |
| 1546 | + |
| 1547 | + /* Card specific information */ |
| 1548 | + struct mmc_cid cid; |
| 1549 | + struct mmc_csd csd; |
| 1550 | + u32 block_num; |
| 1551 | + u32 block_len; |
| 1552 | + u32 erase_unit; |
| 1553 | +}; |
| 1554 | + |
| 1555 | +struct mmc_info mmcinfo; |
| 1556 | + |
| 1557 | +struct mmc_request { |
| 1558 | + int index; /* Slot index - used for CS lines */ |
| 1559 | + int cmd; /* Command to send */ |
| 1560 | + u32 arg; /* Argument to send */ |
| 1561 | + enum mmc_rsp_t rtype; /* Response type expected */ |
| 1562 | + |
| 1563 | + /* Data transfer (these may be modified at the low level) */ |
| 1564 | + u16 nob; /* Number of blocks to transfer*/ |
| 1565 | + u16 block_len; /* Block length */ |
| 1566 | + u8 *buffer; /* Data buffer */ |
| 1567 | + u32 cnt; /* Data length, for PIO */ |
| 1568 | + |
| 1569 | + /* Results */ |
| 1570 | + u8 response[18]; /* Buffer to store response - CRC is optional */ |
| 1571 | + enum mmc_result_t result; |
| 1572 | +}; |
| 1573 | + |
| 1574 | +char * mmc_result_to_string(int); |
| 1575 | +int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd); |
| 1576 | +int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state); |
| 1577 | +int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca); |
| 1578 | +int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr); |
| 1579 | +int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid); |
| 1580 | +int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3); |
| 1581 | + |
| 1582 | +void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg, |
| 1583 | + u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer); |
| 1584 | +u32 mmc_tran_speed(u8 ts); |
| 1585 | +void jz_mmc_set_clock(int sd, u32 rate); |
| 1586 | + |
| 1587 | +static inline void mmc_simple_cmd(struct mmc_request *request, int cmd, u32 arg, enum mmc_rsp_t rtype) |
| 1588 | +{ |
| 1589 | + mmc_send_cmd( request, cmd, arg, 0, 0, rtype, 0); |
| 1590 | +} |
| 1591 | + |
| 1592 | +#endif /* __MMC_JZMMC_H__ */ |
| 1593 | diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h |
| 1594 | index d4449ac..2690e17 100644 |
| 1595 | --- a/include/configs/qi_lb60.h |
| 1596 | +++ b/include/configs/qi_lb60.h |
| 1597 | @@ -31,6 +31,15 @@ |
| 1598 | /* |
| 1599 | * Miscellaneous configurable options |
| 1600 | */ |
| 1601 | +#define CONFIG_JZ4740_MMC |
| 1602 | +#define CONFIG_MMC 1 |
| 1603 | +#define CONFIG_FAT 1 |
| 1604 | +#define CONFIG_DOS_PARTITION 1 |
| 1605 | +#define CONFIG_CMD_MMC |
| 1606 | +#define CONFIG_CMD_FAT |
| 1607 | +#define CONFIG_CMD_EXT2 |
| 1608 | + |
| 1609 | + |
| 1610 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ |
| 1611 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
| 1612 | #define CONFIG_SYS_LOAD_ADDR 0x80600000 |
| 1613 | diff --git a/include/mmc.h b/include/mmc.h |
| 1614 | index a13e2bd..3c4761c 100644 |
| 1615 | --- a/include/mmc.h |
| 1616 | +++ b/include/mmc.h |
| 1617 | @@ -283,4 +283,44 @@ struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); |
| 1618 | int mmc_legacy_init(int verbose); |
| 1619 | #endif |
| 1620 | |
| 1621 | +struct mmc_csd |
| 1622 | +{ |
| 1623 | + u8 csd_structure:2, |
| 1624 | + spec_vers:4, |
| 1625 | + rsvd1:2; |
| 1626 | + u8 taac; |
| 1627 | + u8 nsac; |
| 1628 | + u8 tran_speed; |
| 1629 | + u16 ccc:12, |
| 1630 | + read_bl_len:4; |
| 1631 | + u32 c_size:22; |
| 1632 | + u64 read_bl_partial:1, |
| 1633 | + write_blk_misalign:1, |
| 1634 | + read_blk_misalign:1, |
| 1635 | + dsr_imp:1, |
| 1636 | + rsvd2:2, |
| 1637 | + vdd_r_curr_min:3, |
| 1638 | + vdd_r_curr_max:3, |
| 1639 | + vdd_w_curr_min:3, |
| 1640 | + vdd_w_curr_max:3, |
| 1641 | + c_size_mult:3, |
| 1642 | + sector_size:5, |
| 1643 | + erase_grp_size:5, |
| 1644 | + wp_grp_size:5, |
| 1645 | + wp_grp_enable:1, |
| 1646 | + default_ecc:2, |
| 1647 | + r2w_factor:3, |
| 1648 | + write_bl_len:4, |
| 1649 | + write_bl_partial:1, |
| 1650 | + rsvd3:5; |
| 1651 | + u8 file_format_grp:1, |
| 1652 | + copy:1, |
| 1653 | + perm_write_protect:1, |
| 1654 | + tmp_write_protect:1, |
| 1655 | + file_format:2, |
| 1656 | + ecc:2; |
| 1657 | + u8 crc:7; |
| 1658 | + u8 one:1; |
| 1659 | +}; |
| 1660 | + |
| 1661 | #endif /* _MMC_H_ */ |
| 1662 | -- |
| 1663 | 1.7.9.5 |
| 1664 | |
| 1665 | |
