| 1 | /* |
| 2 | * originally drivers/net/tulip/tulip.h |
| 3 | * Copyright 2000,2001 The Linux Kernel Team |
| 4 | * Written/copyright 1994-2001 by Donald Becker. |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file "COPYING" in the main directory of this archive |
| 8 | * for more details. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __NET_TULIP_H__ |
| 12 | #define __NET_TULIP_H__ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/export.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/mii.h> |
| 19 | #include <linux/crc32.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/types.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/netdevice.h> |
| 24 | #include <linux/ethtool.h> |
| 25 | #include <linux/timer.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/etherdevice.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/io.h> |
| 30 | #include <linux/interrupt.h> |
| 31 | #include <asm/unaligned.h> |
| 32 | #include <asm/uaccess.h> |
| 33 | |
| 34 | /* undefine, or define to various debugging levels (>4 == obscene levels) */ |
| 35 | #define TULIP_DEBUG 1 |
| 36 | #define VALID_INTR 0x0001a451 |
| 37 | #define ADM8668_WAN_IRQ 8 |
| 38 | #define ADM8668_LAN_IRQ 7 |
| 39 | #define ADM8668_WAN_MACADDR 0xb00205ac |
| 40 | #define ADM8668_LAN_MACADDR 0xb0020404 |
| 41 | |
| 42 | /* Offsets to the Command and Status Registers, "CSRs". All accesses |
| 43 | must be longword instructions and quadword aligned. */ |
| 44 | enum tulip_offsets { |
| 45 | CSR0 = 0, |
| 46 | CSR1 = 0x08, |
| 47 | CSR2 = 0x10, |
| 48 | CSR3 = 0x18, |
| 49 | CSR4 = 0x20, |
| 50 | CSR5 = 0x28, |
| 51 | CSR6 = 0x30, |
| 52 | CSR7 = 0x38, |
| 53 | CSR8 = 0x40, |
| 54 | CSR9 = 0x48, |
| 55 | CSR10 = 0x50, |
| 56 | CSR11 = 0x58, |
| 57 | CSR12 = 0x60, |
| 58 | CSR13 = 0x68, |
| 59 | CSR14 = 0x70, |
| 60 | CSR15 = 0x78, |
| 61 | CSR18 = 0x88, |
| 62 | CSR19 = 0x8c, |
| 63 | CSR20 = 0x90, |
| 64 | CSR27 = 0xAC, |
| 65 | CSR28 = 0xB0, |
| 66 | }; |
| 67 | |
| 68 | #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber) |
| 69 | |
| 70 | /* The bits in the CSR5 status registers, mostly interrupt sources. */ |
| 71 | enum status_bits { |
| 72 | TimerInt = 0x800, |
| 73 | SystemError = 0x2000, |
| 74 | TPLnkFail = 0x1000, |
| 75 | TPLnkPass = 0x10, |
| 76 | NormalIntr = 0x10000, |
| 77 | AbnormalIntr = 0x8000, |
| 78 | RxJabber = 0x200, |
| 79 | RxDied = 0x100, |
| 80 | RxNoBuf = 0x80, |
| 81 | RxIntr = 0x40, |
| 82 | TxFIFOUnderflow = 0x20, |
| 83 | RxErrIntr = 0x10, |
| 84 | TxJabber = 0x08, |
| 85 | TxNoBuf = 0x04, |
| 86 | TxDied = 0x02, |
| 87 | TxIntr = 0x01, |
| 88 | }; |
| 89 | |
| 90 | /* bit mask for CSR5 TX/RX process state */ |
| 91 | #define CSR5_TS 0x00700000 |
| 92 | #define CSR5_RS 0x000e0000 |
| 93 | |
| 94 | enum tulip_mode_bits { |
| 95 | TxThreshold = (1 << 22), |
| 96 | FullDuplex = (1 << 9), |
| 97 | TxOn = 0x2000, |
| 98 | AcceptBroadcast = 0x0100, |
| 99 | AcceptAllMulticast = 0x0080, |
| 100 | AcceptAllPhys = 0x0040, |
| 101 | AcceptRunt = 0x0008, |
| 102 | RxOn = 0x0002, |
| 103 | RxTx = (TxOn | RxOn), |
| 104 | }; |
| 105 | |
| 106 | /* The Tulip Rx and Tx buffer descriptors. */ |
| 107 | struct tulip_rx_desc { |
| 108 | __le32 status; |
| 109 | __le32 length; |
| 110 | __le32 buffer1; |
| 111 | __le32 buffer2; |
| 112 | }; |
| 113 | |
| 114 | struct tulip_tx_desc { |
| 115 | __le32 status; |
| 116 | __le32 length; |
| 117 | __le32 buffer1; |
| 118 | __le32 buffer2; /* We use only buffer 1. */ |
| 119 | }; |
| 120 | |
| 121 | enum desc_status_bits { |
| 122 | DescOwned = 0x80000000, |
| 123 | DescWholePkt = 0x60000000, |
| 124 | DescEndPkt = 0x40000000, |
| 125 | DescStartPkt = 0x20000000, |
| 126 | DescEndRing = 0x02000000, |
| 127 | DescUseLink = 0x01000000, |
| 128 | |
| 129 | /* |
| 130 | * Error summary flag is logical or of 'CRC Error', 'Collision Seen', |
| 131 | * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated |
| 132 | * within tulip chip. |
| 133 | */ |
| 134 | RxDescErrorSummary = 0x8000, |
| 135 | RxDescCRCError = 0x0002, |
| 136 | RxDescCollisionSeen = 0x0040, |
| 137 | |
| 138 | /* |
| 139 | * 'Frame Too Long' flag is set if packet length including CRC exceeds |
| 140 | * 1518. However, a full sized VLAN tagged frame is 1522 bytes |
| 141 | * including CRC. |
| 142 | * |
| 143 | * The tulip chip does not block oversized frames, and if this flag is |
| 144 | * set on a receive descriptor it does not indicate the frame has been |
| 145 | * truncated. The receive descriptor also includes the actual length. |
| 146 | * Therefore we can safety ignore this flag and check the length |
| 147 | * ourselves. |
| 148 | */ |
| 149 | RxDescFrameTooLong = 0x0080, |
| 150 | RxDescRunt = 0x0800, |
| 151 | RxDescDescErr = 0x4000, |
| 152 | RxWholePkt = 0x00000300, |
| 153 | /* |
| 154 | * Top three bits of 14 bit frame length (status bits 27-29) should |
| 155 | * never be set as that would make frame over 2047 bytes. The Receive |
| 156 | * Watchdog flag (bit 4) may indicate the length is over 2048 and the |
| 157 | * length field is invalid. |
| 158 | */ |
| 159 | RxLengthOver2047 = 0x38000010 |
| 160 | }; |
| 161 | |
| 162 | /* Keep the ring sizes a power of two for efficiency. |
| 163 | Making the Tx ring too large decreases the effectiveness of channel |
| 164 | bonding and packet priority. |
| 165 | There are no ill effects from too-large receive rings. */ |
| 166 | |
| 167 | #define TX_RING_SIZE 32 |
| 168 | #define RX_RING_SIZE 128 |
| 169 | |
| 170 | /* The receiver on the DC21143 rev 65 can fail to close the last |
| 171 | * receive descriptor in certain circumstances (see errata) when |
| 172 | * using MWI. This can only occur if the receive buffer ends on |
| 173 | * a cache line boundary, so the "+ 4" below ensures it doesn't. |
| 174 | */ |
| 175 | #define PKT_BUF_SZ (1536 + 4) /* Size of each temporary Rx buffer. */ |
| 176 | |
| 177 | /* Ring-wrap flag in length field, use for last ring entry. |
| 178 | 0x01000000 means chain on buffer2 address, |
| 179 | 0x02000000 means use the ring start address in CSR2/3. |
| 180 | Note: Some work-alike chips do not function correctly in chained mode. |
| 181 | The ASIX chip works only in chained mode. |
| 182 | Thus we indicates ring mode, but always write the 'next' field for |
| 183 | chained mode as well. |
| 184 | */ |
| 185 | #define DESC_RING_WRAP 0x02000000 |
| 186 | |
| 187 | struct ring_info { |
| 188 | struct sk_buff *skb; |
| 189 | dma_addr_t mapping; |
| 190 | }; |
| 191 | |
| 192 | struct tulip_private { |
| 193 | struct tulip_rx_desc *rx_ring; |
| 194 | struct tulip_tx_desc *tx_ring; |
| 195 | dma_addr_t rx_ring_dma; |
| 196 | dma_addr_t tx_ring_dma; |
| 197 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
| 198 | struct ring_info tx_buffers[TX_RING_SIZE]; |
| 199 | /* The addresses of receive-in-place skbuffs. */ |
| 200 | struct ring_info rx_buffers[RX_RING_SIZE]; |
| 201 | struct napi_struct napi; |
| 202 | struct net_device_stats stats; |
| 203 | struct timer_list oom_timer; /* Out of memory timer. */ |
| 204 | u32 mc_filter[2]; |
| 205 | spinlock_t lock; |
| 206 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ |
| 207 | unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ |
| 208 | unsigned int csr0; /* CSR0 setting. */ |
| 209 | unsigned int csr6; /* Current CSR6 control settings. */ |
| 210 | void (*link_change) (struct net_device * dev, int csr5); |
| 211 | struct platform_device *pdev; |
| 212 | unsigned long nir; |
| 213 | void __iomem *base_addr; |
| 214 | int pad0; /* Used for 8-byte alignment */ |
| 215 | struct net_device *dev; |
| 216 | }; |
| 217 | |
| 218 | |
| 219 | /* interrupt.c */ |
| 220 | irqreturn_t tulip_interrupt(int irq, void *dev_instance); |
| 221 | int tulip_refill_rx(struct net_device *dev); |
| 222 | int tulip_poll(struct napi_struct *napi, int budget); |
| 223 | |
| 224 | /* tulip_core.c */ |
| 225 | extern int tulip_debug; |
| 226 | void oom_timer(unsigned long data); |
| 227 | |
| 228 | static inline void tulip_start_rxtx(struct tulip_private *tp) |
| 229 | { |
| 230 | void __iomem *ioaddr = tp->base_addr; |
| 231 | iowrite32(tp->csr6 | RxTx, ioaddr + CSR6); |
| 232 | barrier(); |
| 233 | (void) ioread32(ioaddr + CSR6); /* mmio sync */ |
| 234 | } |
| 235 | |
| 236 | static inline void tulip_stop_rxtx(struct tulip_private *tp) |
| 237 | { |
| 238 | void __iomem *ioaddr = tp->base_addr; |
| 239 | u32 csr6 = ioread32(ioaddr + CSR6); |
| 240 | |
| 241 | if (csr6 & RxTx) { |
| 242 | unsigned i=1300/10; |
| 243 | iowrite32(csr6 & ~RxTx, ioaddr + CSR6); |
| 244 | barrier(); |
| 245 | /* wait until in-flight frame completes. |
| 246 | * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin) |
| 247 | * Typically expect this loop to end in < 50 us on 100BT. |
| 248 | */ |
| 249 | while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS))) |
| 250 | udelay(10); |
| 251 | |
| 252 | if (!i) |
| 253 | printk(KERN_DEBUG "fixme: tulip_stop_rxtx() failed" |
| 254 | " (CSR5 0x%x CSR6 0x%x)\n", |
| 255 | ioread32(ioaddr + CSR5), |
| 256 | ioread32(ioaddr + CSR6)); |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | static inline void tulip_restart_rxtx(struct tulip_private *tp) |
| 261 | { |
| 262 | tulip_stop_rxtx(tp); |
| 263 | udelay(5); |
| 264 | tulip_start_rxtx(tp); |
| 265 | } |
| 266 | |
| 267 | static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr) |
| 268 | { |
| 269 | /* Stop and restart the chip's Tx processes. */ |
| 270 | tulip_restart_rxtx(tp); |
| 271 | /* Trigger an immediate transmit demand. */ |
| 272 | iowrite32(0, ioaddr + CSR1); |
| 273 | |
| 274 | tp->stats.tx_errors++; |
| 275 | } |
| 276 | |
| 277 | #endif /* __NET_TULIP_H__ */ |
| 278 | |
