Root/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c

1/*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/etherdevice.h>
20#include <linux/platform_device.h>
21#include <linux/serial_8250.h>
22#include <linux/clk.h>
23
24#include <asm/mach-ath79/ath79.h>
25#include <asm/mach-ath79/ar71xx_regs.h>
26#include <asm/mach-ath79/irq.h>
27
28#include "common.h"
29#include "dev-eth.h"
30
31unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32
33static struct resource ath79_mdio0_resources[] = {
34    {
35        .name = "mdio_base",
36        .flags = IORESOURCE_MEM,
37        .start = AR71XX_GE0_BASE,
38        .end = AR71XX_GE0_BASE + 0x200 - 1,
39    }
40};
41
42static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43
44struct platform_device ath79_mdio0_device = {
45    .name = "ag71xx-mdio",
46    .id = 0,
47    .resource = ath79_mdio0_resources,
48    .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49    .dev = {
50        .platform_data = &ath79_mdio0_data,
51    },
52};
53
54static struct resource ath79_mdio1_resources[] = {
55    {
56        .name = "mdio_base",
57        .flags = IORESOURCE_MEM,
58        .start = AR71XX_GE1_BASE,
59        .end = AR71XX_GE1_BASE + 0x200 - 1,
60    }
61};
62
63static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64
65struct platform_device ath79_mdio1_device = {
66    .name = "ag71xx-mdio",
67    .id = 1,
68    .resource = ath79_mdio1_resources,
69    .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70    .dev = {
71        .platform_data = &ath79_mdio1_data,
72    },
73};
74
75static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
76{
77    void __iomem *base;
78    u32 t;
79
80    base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81
82    t = __raw_readl(base + cfg_reg);
83    t &= ~(3 << shift);
84    t |= (2 << shift);
85    __raw_writel(t, base + cfg_reg);
86    udelay(100);
87
88    __raw_writel(pll_val, base + pll_reg);
89
90    t |= (3 << shift);
91    __raw_writel(t, base + cfg_reg);
92    udelay(100);
93
94    t &= ~(3 << shift);
95    __raw_writel(t, base + cfg_reg);
96    udelay(100);
97
98    printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
99        (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
100
101    iounmap(base);
102}
103
104static void __init ath79_mii_ctrl_set_if(unsigned int reg,
105                      unsigned int mii_if)
106{
107    void __iomem *base;
108    u32 t;
109
110    base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111
112    t = __raw_readl(base + reg);
113    t &= ~(AR71XX_MII_CTRL_IF_MASK);
114    t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
115    __raw_writel(t, base + reg);
116
117    iounmap(base);
118}
119
120static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
121{
122    void __iomem *base;
123    unsigned int mii_speed;
124    u32 t;
125
126    switch (speed) {
127    case SPEED_10:
128        mii_speed = AR71XX_MII_CTRL_SPEED_10;
129        break;
130    case SPEED_100:
131        mii_speed = AR71XX_MII_CTRL_SPEED_100;
132        break;
133    case SPEED_1000:
134        mii_speed = AR71XX_MII_CTRL_SPEED_1000;
135        break;
136    default:
137        BUG();
138    }
139
140    base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141
142    t = __raw_readl(base + reg);
143    t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
144    t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
145    __raw_writel(t, base + reg);
146
147    iounmap(base);
148}
149
150static unsigned long ar934x_get_mdio_ref_clock(void)
151{
152    void __iomem *base;
153    unsigned long ret;
154    u32 t;
155
156    base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
157
158    ret = 0;
159    t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
160    if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
161        ret = 100 * 1000 * 1000;
162    } else {
163        struct clk *clk;
164
165        clk = clk_get(NULL, "ref");
166        if (!IS_ERR(clk))
167            ret = clk_get_rate(clk);
168    }
169
170    iounmap(base);
171
172    return ret;
173}
174
175void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
176{
177    struct platform_device *mdio_dev;
178    struct ag71xx_mdio_platform_data *mdio_data;
179    unsigned int max_id;
180
181    if (ath79_soc == ATH79_SOC_AR9341 ||
182        ath79_soc == ATH79_SOC_AR9342 ||
183        ath79_soc == ATH79_SOC_AR9344 ||
184        ath79_soc == ATH79_SOC_QCA9558)
185        max_id = 1;
186    else
187        max_id = 0;
188
189    if (id > max_id) {
190        printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
191        return;
192    }
193
194    switch (ath79_soc) {
195    case ATH79_SOC_AR7241:
196    case ATH79_SOC_AR9330:
197    case ATH79_SOC_AR9331:
198        mdio_dev = &ath79_mdio1_device;
199        mdio_data = &ath79_mdio1_data;
200        break;
201
202    case ATH79_SOC_AR9341:
203    case ATH79_SOC_AR9342:
204    case ATH79_SOC_AR9344:
205    case ATH79_SOC_QCA9558:
206        if (id == 0) {
207            mdio_dev = &ath79_mdio0_device;
208            mdio_data = &ath79_mdio0_data;
209        } else {
210            mdio_dev = &ath79_mdio1_device;
211            mdio_data = &ath79_mdio1_data;
212        }
213        break;
214
215    case ATH79_SOC_AR7242:
216        ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
217                   AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
218                   AR71XX_ETH0_PLL_SHIFT);
219        /* fall through */
220    default:
221        mdio_dev = &ath79_mdio0_device;
222        mdio_data = &ath79_mdio0_data;
223        break;
224    }
225
226    mdio_data->phy_mask = phy_mask;
227
228    switch (ath79_soc) {
229    case ATH79_SOC_AR7240:
230        mdio_data->is_ar7240 = 1;
231        /* fall through */
232    case ATH79_SOC_AR7241:
233        mdio_data->builtin_switch = 1;
234        break;
235
236    case ATH79_SOC_AR9330:
237        mdio_data->is_ar9330 = 1;
238        /* fall through */
239    case ATH79_SOC_AR9331:
240        mdio_data->builtin_switch = 1;
241        break;
242
243    case ATH79_SOC_AR9341:
244    case ATH79_SOC_AR9342:
245    case ATH79_SOC_AR9344:
246        if (id == 1) {
247            mdio_data->builtin_switch = 1;
248            mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
249            mdio_data->mdio_clock = 6250000;
250        }
251        mdio_data->is_ar934x = 1;
252        break;
253    case ATH79_SOC_QCA9558:
254        if (id == 1)
255            mdio_data->builtin_switch = 1;
256        mdio_data->is_ar934x = 1;
257        break;
258
259    default:
260        break;
261    }
262
263    platform_device_register(mdio_dev);
264}
265
266struct ath79_eth_pll_data ath79_eth0_pll_data;
267struct ath79_eth_pll_data ath79_eth1_pll_data;
268
269static u32 ath79_get_eth_pll(unsigned int mac, int speed)
270{
271    struct ath79_eth_pll_data *pll_data;
272    u32 pll_val;
273
274    switch (mac) {
275    case 0:
276        pll_data = &ath79_eth0_pll_data;
277        break;
278    case 1:
279        pll_data = &ath79_eth1_pll_data;
280        break;
281    default:
282        BUG();
283    }
284
285    switch (speed) {
286    case SPEED_10:
287        pll_val = pll_data->pll_10;
288        break;
289    case SPEED_100:
290        pll_val = pll_data->pll_100;
291        break;
292    case SPEED_1000:
293        pll_val = pll_data->pll_1000;
294        break;
295    default:
296        BUG();
297    }
298
299    return pll_val;
300}
301
302static void ath79_set_speed_ge0(int speed)
303{
304    u32 val = ath79_get_eth_pll(0, speed);
305
306    ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
307            val, AR71XX_ETH0_PLL_SHIFT);
308    ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
309}
310
311static void ath79_set_speed_ge1(int speed)
312{
313    u32 val = ath79_get_eth_pll(1, speed);
314
315    ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
316             val, AR71XX_ETH1_PLL_SHIFT);
317    ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
318}
319
320static void ar7242_set_speed_ge0(int speed)
321{
322    u32 val = ath79_get_eth_pll(0, speed);
323    void __iomem *base;
324
325    base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
326    __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
327    iounmap(base);
328}
329
330static void ar91xx_set_speed_ge0(int speed)
331{
332    u32 val = ath79_get_eth_pll(0, speed);
333
334    ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
335             val, AR913X_ETH0_PLL_SHIFT);
336    ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
337}
338
339static void ar91xx_set_speed_ge1(int speed)
340{
341    u32 val = ath79_get_eth_pll(1, speed);
342
343    ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
344             val, AR913X_ETH1_PLL_SHIFT);
345    ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
346}
347
348static void ar934x_set_speed_ge0(int speed)
349{
350    void __iomem *base;
351    u32 val = ath79_get_eth_pll(0, speed);
352
353    base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
354    __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
355    iounmap(base);
356}
357
358static void ath79_set_speed_dummy(int speed)
359{
360}
361
362static void ath79_ddr_no_flush(void)
363{
364}
365
366static void ath79_ddr_flush_ge0(void)
367{
368    ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
369}
370
371static void ath79_ddr_flush_ge1(void)
372{
373    ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
374}
375
376static void ar724x_ddr_flush_ge0(void)
377{
378    ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
379}
380
381static void ar724x_ddr_flush_ge1(void)
382{
383    ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
384}
385
386static void ar91xx_ddr_flush_ge0(void)
387{
388    ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
389}
390
391static void ar91xx_ddr_flush_ge1(void)
392{
393    ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
394}
395
396static void ar933x_ddr_flush_ge0(void)
397{
398    ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
399}
400
401static void ar933x_ddr_flush_ge1(void)
402{
403    ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
404}
405
406static struct resource ath79_eth0_resources[] = {
407    {
408        .name = "mac_base",
409        .flags = IORESOURCE_MEM,
410        .start = AR71XX_GE0_BASE,
411        .end = AR71XX_GE0_BASE + 0x200 - 1,
412    }, {
413        .name = "mac_irq",
414        .flags = IORESOURCE_IRQ,
415        .start = ATH79_CPU_IRQ_GE0,
416        .end = ATH79_CPU_IRQ_GE0,
417    },
418};
419
420struct ag71xx_platform_data ath79_eth0_data = {
421    .reset_bit = AR71XX_RESET_GE0_MAC,
422};
423
424struct platform_device ath79_eth0_device = {
425    .name = "ag71xx",
426    .id = 0,
427    .resource = ath79_eth0_resources,
428    .num_resources = ARRAY_SIZE(ath79_eth0_resources),
429    .dev = {
430        .platform_data = &ath79_eth0_data,
431    },
432};
433
434static struct resource ath79_eth1_resources[] = {
435    {
436        .name = "mac_base",
437        .flags = IORESOURCE_MEM,
438        .start = AR71XX_GE1_BASE,
439        .end = AR71XX_GE1_BASE + 0x200 - 1,
440    }, {
441        .name = "mac_irq",
442        .flags = IORESOURCE_IRQ,
443        .start = ATH79_CPU_IRQ_GE1,
444        .end = ATH79_CPU_IRQ_GE1,
445    },
446};
447
448struct ag71xx_platform_data ath79_eth1_data = {
449    .reset_bit = AR71XX_RESET_GE1_MAC,
450};
451
452struct platform_device ath79_eth1_device = {
453    .name = "ag71xx",
454    .id = 1,
455    .resource = ath79_eth1_resources,
456    .num_resources = ARRAY_SIZE(ath79_eth1_resources),
457    .dev = {
458        .platform_data = &ath79_eth1_data,
459    },
460};
461
462struct ag71xx_switch_platform_data ath79_switch_data;
463
464#define AR71XX_PLL_VAL_1000 0x00110000
465#define AR71XX_PLL_VAL_100 0x00001099
466#define AR71XX_PLL_VAL_10 0x00991099
467
468#define AR724X_PLL_VAL_1000 0x00110000
469#define AR724X_PLL_VAL_100 0x00001099
470#define AR724X_PLL_VAL_10 0x00991099
471
472#define AR7242_PLL_VAL_1000 0x16000000
473#define AR7242_PLL_VAL_100 0x00000101
474#define AR7242_PLL_VAL_10 0x00001616
475
476#define AR913X_PLL_VAL_1000 0x1a000000
477#define AR913X_PLL_VAL_100 0x13000a44
478#define AR913X_PLL_VAL_10 0x00441099
479
480#define AR933X_PLL_VAL_1000 0x00110000
481#define AR933X_PLL_VAL_100 0x00001099
482#define AR933X_PLL_VAL_10 0x00991099
483
484#define AR934X_PLL_VAL_1000 0x16000000
485#define AR934X_PLL_VAL_100 0x00000101
486#define AR934X_PLL_VAL_10 0x00001616
487
488static void __init ath79_init_eth_pll_data(unsigned int id)
489{
490    struct ath79_eth_pll_data *pll_data;
491    u32 pll_10, pll_100, pll_1000;
492
493    switch (id) {
494    case 0:
495        pll_data = &ath79_eth0_pll_data;
496        break;
497    case 1:
498        pll_data = &ath79_eth1_pll_data;
499        break;
500    default:
501        BUG();
502    }
503
504    switch (ath79_soc) {
505    case ATH79_SOC_AR7130:
506    case ATH79_SOC_AR7141:
507    case ATH79_SOC_AR7161:
508        pll_10 = AR71XX_PLL_VAL_10;
509        pll_100 = AR71XX_PLL_VAL_100;
510        pll_1000 = AR71XX_PLL_VAL_1000;
511        break;
512
513    case ATH79_SOC_AR7240:
514    case ATH79_SOC_AR7241:
515        pll_10 = AR724X_PLL_VAL_10;
516        pll_100 = AR724X_PLL_VAL_100;
517        pll_1000 = AR724X_PLL_VAL_1000;
518        break;
519
520    case ATH79_SOC_AR7242:
521        pll_10 = AR7242_PLL_VAL_10;
522        pll_100 = AR7242_PLL_VAL_100;
523        pll_1000 = AR7242_PLL_VAL_1000;
524        break;
525
526    case ATH79_SOC_AR9130:
527    case ATH79_SOC_AR9132:
528        pll_10 = AR913X_PLL_VAL_10;
529        pll_100 = AR913X_PLL_VAL_100;
530        pll_1000 = AR913X_PLL_VAL_1000;
531        break;
532
533    case ATH79_SOC_AR9330:
534    case ATH79_SOC_AR9331:
535        pll_10 = AR933X_PLL_VAL_10;
536        pll_100 = AR933X_PLL_VAL_100;
537        pll_1000 = AR933X_PLL_VAL_1000;
538        break;
539
540    case ATH79_SOC_AR9341:
541    case ATH79_SOC_AR9342:
542    case ATH79_SOC_AR9344:
543    case ATH79_SOC_QCA9558:
544        pll_10 = AR934X_PLL_VAL_10;
545        pll_100 = AR934X_PLL_VAL_100;
546        pll_1000 = AR934X_PLL_VAL_1000;
547        break;
548
549    default:
550        BUG();
551    }
552
553    if (!pll_data->pll_10)
554        pll_data->pll_10 = pll_10;
555
556    if (!pll_data->pll_100)
557        pll_data->pll_100 = pll_100;
558
559    if (!pll_data->pll_1000)
560        pll_data->pll_1000 = pll_1000;
561}
562
563static int __init ath79_setup_phy_if_mode(unsigned int id,
564                       struct ag71xx_platform_data *pdata)
565{
566    unsigned int mii_if;
567
568    switch (id) {
569    case 0:
570        switch (ath79_soc) {
571        case ATH79_SOC_AR7130:
572        case ATH79_SOC_AR7141:
573        case ATH79_SOC_AR7161:
574        case ATH79_SOC_AR9130:
575        case ATH79_SOC_AR9132:
576            switch (pdata->phy_if_mode) {
577            case PHY_INTERFACE_MODE_MII:
578                mii_if = AR71XX_MII0_CTRL_IF_MII;
579                break;
580            case PHY_INTERFACE_MODE_GMII:
581                mii_if = AR71XX_MII0_CTRL_IF_GMII;
582                break;
583            case PHY_INTERFACE_MODE_RGMII:
584                mii_if = AR71XX_MII0_CTRL_IF_RGMII;
585                break;
586            case PHY_INTERFACE_MODE_RMII:
587                mii_if = AR71XX_MII0_CTRL_IF_RMII;
588                break;
589            default:
590                return -EINVAL;
591            }
592            ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
593            break;
594
595        case ATH79_SOC_AR7240:
596        case ATH79_SOC_AR7241:
597        case ATH79_SOC_AR9330:
598        case ATH79_SOC_AR9331:
599            pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
600            break;
601
602        case ATH79_SOC_AR7242:
603            /* FIXME */
604
605        case ATH79_SOC_AR9341:
606        case ATH79_SOC_AR9342:
607        case ATH79_SOC_AR9344:
608        case ATH79_SOC_QCA9558:
609            switch (pdata->phy_if_mode) {
610            case PHY_INTERFACE_MODE_MII:
611            case PHY_INTERFACE_MODE_GMII:
612            case PHY_INTERFACE_MODE_RGMII:
613            case PHY_INTERFACE_MODE_RMII:
614                break;
615            default:
616                return -EINVAL;
617            }
618            break;
619
620        default:
621            BUG();
622        }
623        break;
624    case 1:
625        switch (ath79_soc) {
626        case ATH79_SOC_AR7130:
627        case ATH79_SOC_AR7141:
628        case ATH79_SOC_AR7161:
629        case ATH79_SOC_AR9130:
630        case ATH79_SOC_AR9132:
631            switch (pdata->phy_if_mode) {
632            case PHY_INTERFACE_MODE_RMII:
633                mii_if = AR71XX_MII1_CTRL_IF_RMII;
634                break;
635            case PHY_INTERFACE_MODE_RGMII:
636                mii_if = AR71XX_MII1_CTRL_IF_RGMII;
637                break;
638            default:
639                return -EINVAL;
640            }
641            ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
642            break;
643
644        case ATH79_SOC_AR7240:
645        case ATH79_SOC_AR7241:
646        case ATH79_SOC_AR9330:
647        case ATH79_SOC_AR9331:
648            pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
649            break;
650
651        case ATH79_SOC_AR7242:
652            /* FIXME */
653
654        case ATH79_SOC_AR9341:
655        case ATH79_SOC_AR9342:
656        case ATH79_SOC_AR9344:
657        case ATH79_SOC_QCA9558:
658            switch (pdata->phy_if_mode) {
659            case PHY_INTERFACE_MODE_MII:
660            case PHY_INTERFACE_MODE_GMII:
661                break;
662            default:
663                return -EINVAL;
664            }
665            break;
666
667        default:
668            BUG();
669        }
670        break;
671    }
672
673    return 0;
674}
675
676void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
677{
678    void __iomem *base;
679    u32 t;
680
681    base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
682
683    t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
684    t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
685    if (mac)
686        t |= AR933X_ETH_CFG_SW_PHY_SWAP;
687    if (mdio)
688        t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
689    __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
690
691    iounmap(base);
692}
693
694static int ath79_eth_instance __initdata;
695void __init ath79_register_eth(unsigned int id)
696{
697    struct platform_device *pdev;
698    struct ag71xx_platform_data *pdata;
699    int err;
700
701    if (id > 1) {
702        printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
703        return;
704    }
705
706    ath79_init_eth_pll_data(id);
707
708    if (id == 0)
709        pdev = &ath79_eth0_device;
710    else
711        pdev = &ath79_eth1_device;
712
713    pdata = pdev->dev.platform_data;
714
715    err = ath79_setup_phy_if_mode(id, pdata);
716    if (err) {
717        printk(KERN_ERR
718               "ar71xx: invalid PHY interface mode for GE%u\n", id);
719        return;
720    }
721
722    switch (ath79_soc) {
723    case ATH79_SOC_AR7130:
724        if (id == 0) {
725            pdata->ddr_flush = ath79_ddr_flush_ge0;
726            pdata->set_speed = ath79_set_speed_ge0;
727        } else {
728            pdata->ddr_flush = ath79_ddr_flush_ge1;
729            pdata->set_speed = ath79_set_speed_ge1;
730        }
731        break;
732
733    case ATH79_SOC_AR7141:
734    case ATH79_SOC_AR7161:
735        if (id == 0) {
736            pdata->ddr_flush = ath79_ddr_flush_ge0;
737            pdata->set_speed = ath79_set_speed_ge0;
738        } else {
739            pdata->ddr_flush = ath79_ddr_flush_ge1;
740            pdata->set_speed = ath79_set_speed_ge1;
741        }
742        pdata->has_gbit = 1;
743        break;
744
745    case ATH79_SOC_AR7242:
746        if (id == 0) {
747            pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
748                        AR71XX_RESET_GE0_PHY;
749            pdata->ddr_flush = ar724x_ddr_flush_ge0;
750            pdata->set_speed = ar7242_set_speed_ge0;
751        } else {
752            pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
753                        AR71XX_RESET_GE1_PHY;
754            pdata->ddr_flush = ar724x_ddr_flush_ge1;
755            pdata->set_speed = ath79_set_speed_dummy;
756        }
757        pdata->has_gbit = 1;
758        pdata->is_ar724x = 1;
759
760        if (!pdata->fifo_cfg1)
761            pdata->fifo_cfg1 = 0x0010ffff;
762        if (!pdata->fifo_cfg2)
763            pdata->fifo_cfg2 = 0x015500aa;
764        if (!pdata->fifo_cfg3)
765            pdata->fifo_cfg3 = 0x01f00140;
766        break;
767
768    case ATH79_SOC_AR7241:
769        if (id == 0)
770            pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
771        else
772            pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
773        /* fall through */
774    case ATH79_SOC_AR7240:
775        if (id == 0) {
776            pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
777            pdata->ddr_flush = ar724x_ddr_flush_ge0;
778            pdata->set_speed = ath79_set_speed_dummy;
779
780            pdata->phy_mask = BIT(4);
781        } else {
782            pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
783            pdata->ddr_flush = ar724x_ddr_flush_ge1;
784            pdata->set_speed = ath79_set_speed_dummy;
785
786            pdata->speed = SPEED_1000;
787            pdata->duplex = DUPLEX_FULL;
788            pdata->switch_data = &ath79_switch_data;
789
790            ath79_switch_data.phy_poll_mask |= BIT(4);
791        }
792        pdata->has_gbit = 1;
793        pdata->is_ar724x = 1;
794        if (ath79_soc == ATH79_SOC_AR7240)
795            pdata->is_ar7240 = 1;
796
797        if (!pdata->fifo_cfg1)
798            pdata->fifo_cfg1 = 0x0010ffff;
799        if (!pdata->fifo_cfg2)
800            pdata->fifo_cfg2 = 0x015500aa;
801        if (!pdata->fifo_cfg3)
802            pdata->fifo_cfg3 = 0x01f00140;
803        break;
804
805    case ATH79_SOC_AR9130:
806        if (id == 0) {
807            pdata->ddr_flush = ar91xx_ddr_flush_ge0;
808            pdata->set_speed = ar91xx_set_speed_ge0;
809        } else {
810            pdata->ddr_flush = ar91xx_ddr_flush_ge1;
811            pdata->set_speed = ar91xx_set_speed_ge1;
812        }
813        pdata->is_ar91xx = 1;
814        break;
815
816    case ATH79_SOC_AR9132:
817        if (id == 0) {
818            pdata->ddr_flush = ar91xx_ddr_flush_ge0;
819            pdata->set_speed = ar91xx_set_speed_ge0;
820        } else {
821            pdata->ddr_flush = ar91xx_ddr_flush_ge1;
822            pdata->set_speed = ar91xx_set_speed_ge1;
823        }
824        pdata->is_ar91xx = 1;
825        pdata->has_gbit = 1;
826        break;
827
828    case ATH79_SOC_AR9330:
829    case ATH79_SOC_AR9331:
830        if (id == 0) {
831            pdata->reset_bit = AR933X_RESET_GE0_MAC |
832                       AR933X_RESET_GE0_MDIO;
833            pdata->ddr_flush = ar933x_ddr_flush_ge0;
834            pdata->set_speed = ath79_set_speed_dummy;
835
836            pdata->phy_mask = BIT(4);
837        } else {
838            pdata->reset_bit = AR933X_RESET_GE1_MAC |
839                       AR933X_RESET_GE1_MDIO;
840            pdata->ddr_flush = ar933x_ddr_flush_ge1;
841            pdata->set_speed = ath79_set_speed_dummy;
842
843            pdata->speed = SPEED_1000;
844            pdata->duplex = DUPLEX_FULL;
845            pdata->switch_data = &ath79_switch_data;
846
847            ath79_switch_data.phy_poll_mask |= BIT(4);
848        }
849
850        pdata->has_gbit = 1;
851        pdata->is_ar724x = 1;
852
853        if (!pdata->fifo_cfg1)
854            pdata->fifo_cfg1 = 0x0010ffff;
855        if (!pdata->fifo_cfg2)
856            pdata->fifo_cfg2 = 0x015500aa;
857        if (!pdata->fifo_cfg3)
858            pdata->fifo_cfg3 = 0x01f00140;
859        break;
860
861    case ATH79_SOC_AR9341:
862    case ATH79_SOC_AR9342:
863    case ATH79_SOC_AR9344:
864    case ATH79_SOC_QCA9558:
865        if (id == 0) {
866            pdata->reset_bit = AR934X_RESET_GE0_MAC |
867                       AR934X_RESET_GE0_MDIO;
868            pdata->set_speed = ar934x_set_speed_ge0;
869        } else {
870            pdata->reset_bit = AR934X_RESET_GE1_MAC |
871                       AR934X_RESET_GE1_MDIO;
872            pdata->set_speed = ath79_set_speed_dummy;
873
874            pdata->switch_data = &ath79_switch_data;
875
876            /* reset the built-in switch */
877            ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
878            ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
879        }
880
881        pdata->ddr_flush = ath79_ddr_no_flush;
882        pdata->has_gbit = 1;
883        pdata->is_ar724x = 1;
884
885        if (!pdata->fifo_cfg1)
886            pdata->fifo_cfg1 = 0x0010ffff;
887        if (!pdata->fifo_cfg2)
888            pdata->fifo_cfg2 = 0x015500aa;
889        if (!pdata->fifo_cfg3)
890            pdata->fifo_cfg3 = 0x01f00140;
891        break;
892
893    default:
894        BUG();
895    }
896
897    switch (pdata->phy_if_mode) {
898    case PHY_INTERFACE_MODE_GMII:
899    case PHY_INTERFACE_MODE_RGMII:
900        if (!pdata->has_gbit) {
901            printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
902                    id);
903            return;
904        }
905        /* fallthrough */
906    default:
907        break;
908    }
909
910    if (!is_valid_ether_addr(pdata->mac_addr)) {
911        random_ether_addr(pdata->mac_addr);
912        printk(KERN_DEBUG
913            "ar71xx: using random MAC address for eth%d\n",
914            ath79_eth_instance);
915    }
916
917    if (pdata->mii_bus_dev == NULL) {
918        switch (ath79_soc) {
919        case ATH79_SOC_AR9341:
920        case ATH79_SOC_AR9342:
921        case ATH79_SOC_AR9344:
922        case ATH79_SOC_QCA9558:
923            if (id == 0)
924                pdata->mii_bus_dev = &ath79_mdio0_device.dev;
925            else
926                pdata->mii_bus_dev = &ath79_mdio1_device.dev;
927            break;
928
929        case ATH79_SOC_AR7241:
930        case ATH79_SOC_AR9330:
931        case ATH79_SOC_AR9331:
932            pdata->mii_bus_dev = &ath79_mdio1_device.dev;
933            break;
934
935        default:
936            pdata->mii_bus_dev = &ath79_mdio0_device.dev;
937            break;
938        }
939    }
940
941    /* Reset the device */
942    ath79_device_reset_set(pdata->reset_bit);
943    mdelay(100);
944
945    ath79_device_reset_clear(pdata->reset_bit);
946    mdelay(100);
947
948    platform_device_register(pdev);
949    ath79_eth_instance++;
950}
951
952void __init ath79_set_mac_base(unsigned char *mac)
953{
954    memcpy(ath79_mac_base, mac, ETH_ALEN);
955}
956
957void __init ath79_parse_mac_addr(char *mac_str)
958{
959    u8 tmp[ETH_ALEN];
960    int t;
961
962    t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
963            &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
964
965    if (t != ETH_ALEN)
966        t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
967            &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
968
969    if (t == ETH_ALEN)
970        ath79_set_mac_base(tmp);
971    else
972        printk(KERN_DEBUG "ar71xx: failed to parse mac address "
973                "\"%s\"\n", mac_str);
974}
975
976static int __init ath79_ethaddr_setup(char *str)
977{
978    ath79_parse_mac_addr(str);
979    return 1;
980}
981__setup("ethaddr=", ath79_ethaddr_setup);
982
983static int __init ath79_kmac_setup(char *str)
984{
985    ath79_parse_mac_addr(str);
986    return 1;
987}
988__setup("kmac=", ath79_kmac_setup);
989
990void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
991                int offset)
992{
993    int t;
994
995    if (!dst)
996        return;
997
998    if (!src || !is_valid_ether_addr(src)) {
999        memset(dst, '\0', ETH_ALEN);
1000        return;
1001    }
1002
1003    t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1004    t += offset;
1005
1006    dst[0] = src[0];
1007    dst[1] = src[1];
1008    dst[2] = src[2];
1009    dst[3] = (t >> 16) & 0xff;
1010    dst[4] = (t >> 8) & 0xff;
1011    dst[5] = t & 0xff;
1012}
1013
1014void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1015{
1016    int i;
1017
1018    if (!dst)
1019        return;
1020
1021    if (!src || !is_valid_ether_addr(src)) {
1022        memset(dst, '\0', ETH_ALEN);
1023        return;
1024    }
1025
1026    for (i = 0; i < ETH_ALEN; i++)
1027        dst[i] = src[i];
1028    dst[0] |= 0x02;
1029}
1030

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