Root/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c

1/*
2 * MikroTik RouterBOARD 4xx series support
3 *
4 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/platform_device.h>
13#include <linux/irq.h>
14#include <linux/mdio-gpio.h>
15#include <linux/mmc/host.h>
16#include <linux/spi/spi.h>
17#include <linux/spi/flash.h>
18#include <linux/spi/mmc_spi.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/partitions.h>
21
22#include <asm/mach-ath79/ar71xx_regs.h>
23#include <asm/mach-ath79/ath79.h>
24#include <asm/mach-ath79/rb4xx_cpld.h>
25
26#include "common.h"
27#include "dev-eth.h"
28#include "dev-gpio-buttons.h"
29#include "dev-leds-gpio.h"
30#include "dev-usb.h"
31#include "machtypes.h"
32#include "pci.h"
33
34#define RB4XX_GPIO_USER_LED 4
35#define RB4XX_GPIO_RESET_SWITCH 7
36
37#define RB4XX_GPIO_CPLD_BASE 32
38#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
39#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
40#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
41#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
42#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
43
44#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */
45#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL)
46
47static struct gpio_led rb4xx_leds_gpio[] __initdata = {
48    {
49        .name = "rb4xx:yellow:user",
50        .gpio = RB4XX_GPIO_USER_LED,
51        .active_low = 0,
52    }, {
53        .name = "rb4xx:green:led1",
54        .gpio = RB4XX_GPIO_CPLD_LED1,
55        .active_low = 1,
56    }, {
57        .name = "rb4xx:green:led2",
58        .gpio = RB4XX_GPIO_CPLD_LED2,
59        .active_low = 1,
60    }, {
61        .name = "rb4xx:green:led3",
62        .gpio = RB4XX_GPIO_CPLD_LED3,
63        .active_low = 1,
64    }, {
65        .name = "rb4xx:green:led4",
66        .gpio = RB4XX_GPIO_CPLD_LED4,
67        .active_low = 1,
68    }, {
69        .name = "rb4xx:green:led5",
70        .gpio = RB4XX_GPIO_CPLD_LED5,
71        .active_low = 0,
72    },
73};
74
75static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
76    {
77        .desc = "reset_switch",
78        .type = EV_KEY,
79        .code = KEY_RESTART,
80        .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
81        .gpio = RB4XX_GPIO_RESET_SWITCH,
82        .active_low = 1,
83    }
84};
85
86static struct platform_device rb4xx_nand_device = {
87    .name = "rb4xx-nand",
88    .id = -1,
89};
90
91static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
92    {
93        .slot = 17,
94        .pin = 1,
95        .irq = ATH79_PCI_IRQ(2),
96    }, {
97        .slot = 18,
98        .pin = 1,
99        .irq = ATH79_PCI_IRQ(0),
100    }, {
101        .slot = 18,
102        .pin = 2,
103        .irq = ATH79_PCI_IRQ(1),
104    }, {
105        .slot = 19,
106        .pin = 1,
107        .irq = ATH79_PCI_IRQ(1),
108    }, {
109        .slot = 19,
110        .pin = 1,
111        .irq = ATH79_PCI_IRQ(2),
112    }
113};
114
115static struct mtd_partition rb4xx_partitions[] = {
116    {
117        .name = "routerboot",
118        .offset = 0,
119        .size = 0x0b000,
120        .mask_flags = MTD_WRITEABLE,
121    }, {
122        .name = "hard_config",
123        .offset = 0x0b000,
124        .size = 0x01000,
125        .mask_flags = MTD_WRITEABLE,
126    }, {
127        .name = "bios",
128        .offset = 0x0d000,
129        .size = 0x02000,
130        .mask_flags = MTD_WRITEABLE,
131    }, {
132        .name = "soft_config",
133        .offset = 0x0f000,
134        .size = 0x01000,
135    }
136};
137
138static struct flash_platform_data rb4xx_flash_data = {
139    .type = "pm25lv512",
140    .parts = rb4xx_partitions,
141    .nr_parts = ARRAY_SIZE(rb4xx_partitions),
142};
143
144static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
145    .gpio_base = RB4XX_GPIO_CPLD_BASE,
146};
147
148static struct mmc_spi_platform_data rb4xx_mmc_data = {
149    .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
150};
151
152static struct spi_board_info rb4xx_spi_info[] = {
153    {
154        .bus_num = 0,
155        .chip_select = 0,
156        .max_speed_hz = 25000000,
157        .modalias = "m25p80",
158        .platform_data = &rb4xx_flash_data,
159    }, {
160        .bus_num = 0,
161        .chip_select = 1,
162        .max_speed_hz = 25000000,
163        .modalias = "spi-rb4xx-cpld",
164        .platform_data = &rb4xx_cpld_data,
165    }
166};
167
168static struct spi_board_info rb4xx_microsd_info[] = {
169    {
170        .bus_num = 0,
171        .chip_select = 2,
172        .max_speed_hz = 25000000,
173        .modalias = "mmc_spi",
174        .platform_data = &rb4xx_mmc_data,
175    }
176};
177
178
179static struct resource rb4xx_spi_resources[] = {
180    {
181        .start = AR71XX_SPI_BASE,
182        .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
183        .flags = IORESOURCE_MEM,
184    },
185};
186
187static struct platform_device rb4xx_spi_device = {
188    .name = "rb4xx-spi",
189    .id = -1,
190    .resource = rb4xx_spi_resources,
191    .num_resources = ARRAY_SIZE(rb4xx_spi_resources),
192};
193
194static void __init rb4xx_generic_setup(void)
195{
196    ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
197                   AR71XX_GPIO_FUNC_SPI_CS2_EN);
198
199    ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
200                    rb4xx_leds_gpio);
201
202    ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
203                    ARRAY_SIZE(rb4xx_gpio_keys),
204                    rb4xx_gpio_keys);
205
206    spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
207    platform_device_register(&rb4xx_spi_device);
208    platform_device_register(&rb4xx_nand_device);
209}
210
211static void __init rb411_setup(void)
212{
213    rb4xx_generic_setup();
214    spi_register_board_info(rb4xx_microsd_info,
215                ARRAY_SIZE(rb4xx_microsd_info));
216
217    ath79_register_mdio(0, 0xfffffffc);
218
219    ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
220    ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
221    ath79_eth0_data.phy_mask = 0x00000003;
222
223    ath79_register_eth(0);
224
225    ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
226    ath79_register_pci();
227}
228
229MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
230         rb411_setup);
231
232static void __init rb411u_setup(void)
233{
234    rb411_setup();
235    ath79_register_usb();
236}
237
238MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
239         rb411u_setup);
240
241#define RB433_LAN_PHYMASK BIT(0)
242#define RB433_WAN_PHYMASK BIT(4)
243#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
244
245static void __init rb433_setup(void)
246{
247    rb4xx_generic_setup();
248    spi_register_board_info(rb4xx_microsd_info,
249                ARRAY_SIZE(rb4xx_microsd_info));
250
251    ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
252
253    ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
254    ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
255    ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
256
257    ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
258    ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
259    ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
260
261    ath79_register_eth(1);
262    ath79_register_eth(0);
263
264    ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
265    ath79_register_pci();
266}
267
268MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
269         rb433_setup);
270
271static void __init rb433u_setup(void)
272{
273    rb433_setup();
274    ath79_register_usb();
275}
276
277MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
278         rb433u_setup);
279
280#define RB450_LAN_PHYMASK BIT(0)
281#define RB450_WAN_PHYMASK BIT(4)
282#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
283
284static void __init rb450_generic_setup(int gige)
285{
286    rb4xx_generic_setup();
287    ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
288
289    ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
290    ath79_eth0_data.phy_if_mode = (gige) ?
291        PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
292    ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
293
294    ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
295    ath79_eth1_data.phy_if_mode = (gige) ?
296        PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
297    ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
298
299    ath79_register_eth(1);
300    ath79_register_eth(0);
301}
302
303static void __init rb450_setup(void)
304{
305    rb450_generic_setup(0);
306}
307
308MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
309         rb450_setup);
310
311static void __init rb450g_setup(void)
312{
313    rb450_generic_setup(1);
314    spi_register_board_info(rb4xx_microsd_info,
315                ARRAY_SIZE(rb4xx_microsd_info));
316}
317
318MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
319         rb450g_setup);
320
321static void __init rb493_setup(void)
322{
323    rb4xx_generic_setup();
324
325    ath79_register_mdio(0, 0x3fffff00);
326
327    ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
328    ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
329    ath79_eth0_data.speed = SPEED_100;
330    ath79_eth0_data.duplex = DUPLEX_FULL;
331
332    ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
333    ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
334    ath79_eth1_data.phy_mask = 0x00000001;
335
336    ath79_register_eth(0);
337    ath79_register_eth(1);
338
339    ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
340    ath79_register_pci();
341}
342
343MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
344         rb493_setup);
345
346#define RB493G_GPIO_MDIO_MDC 7
347#define RB493G_GPIO_MDIO_DATA 8
348
349#define RB493G_MDIO_PHYMASK BIT(0)
350
351static struct mdio_gpio_platform_data rb493g_mdio_data = {
352    .mdc = RB493G_GPIO_MDIO_MDC,
353    .mdio = RB493G_GPIO_MDIO_DATA,
354
355    .phy_mask = ~RB493G_MDIO_PHYMASK,
356};
357
358static struct platform_device rb493g_mdio_device = {
359    .name = "mdio-gpio",
360    .id = -1,
361    .dev = {
362        .platform_data = &rb493g_mdio_data,
363    },
364};
365
366static void __init rb493g_setup(void)
367{
368    ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
369                    AR71XX_GPIO_FUNC_SPI_CS2_EN);
370
371    ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
372                    rb4xx_leds_gpio);
373
374    spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
375    platform_device_register(&rb4xx_spi_device);
376    platform_device_register(&rb4xx_nand_device);
377
378    ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
379
380    ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
381    ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
382    ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
383    ath79_eth0_data.speed = SPEED_1000;
384    ath79_eth0_data.duplex = DUPLEX_FULL;
385
386    ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
387    ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
388    ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
389    ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
390    ath79_eth1_data.speed = SPEED_1000;
391    ath79_eth1_data.duplex = DUPLEX_FULL;
392
393    platform_device_register(&rb493g_mdio_device);
394
395    ath79_register_eth(1);
396    ath79_register_eth(0);
397
398    ath79_register_usb();
399
400    ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
401    ath79_register_pci();
402}
403
404MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",
405         rb493g_setup);
406

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