Root/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c

1/*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
14#include <linux/dma-mapping.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/nand.h>
17#include <linux/mtd/partitions.h>
18#include <linux/platform_device.h>
19#include <linux/delay.h>
20#include <linux/slab.h>
21
22#include <linux/platform/ar934x_nfc.h>
23
24#define AR934X_NFC_REG_CMD 0x00
25#define AR934X_NFC_REG_CTRL 0x04
26#define AR934X_NFC_REG_STATUS 0x08
27#define AR934X_NFC_REG_INT_MASK 0x0c
28#define AR934X_NFC_REG_INT_STATUS 0x10
29#define AR934X_NFC_REG_ECC_CTRL 0x14
30#define AR934X_NFC_REG_ECC_OFFSET 0x18
31#define AR934X_NFC_REG_ADDR0_0 0x1c
32#define AR934X_NFC_REG_ADDR0_1 0x24
33#define AR934X_NFC_REG_ADDR1_0 0x20
34#define AR934X_NFC_REG_ADDR1_1 0x28
35#define AR934X_NFC_REG_SPARE_SIZE 0x30
36#define AR934X_NFC_REG_PROTECT 0x38
37#define AR934X_NFC_REG_LOOKUP_EN 0x40
38#define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39#define AR934X_NFC_REG_DMA_ADDR 0x64
40#define AR934X_NFC_REG_DMA_COUNT 0x68
41#define AR934X_NFC_REG_DMA_CTRL 0x6c
42#define AR934X_NFC_REG_MEM_CTRL 0x80
43#define AR934X_NFC_REG_DATA_SIZE 0x84
44#define AR934X_NFC_REG_READ_STATUS 0x88
45#define AR934X_NFC_REG_TIME_SEQ 0x8c
46#define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47#define AR934X_NFC_REG_TIMINGS_SYN 0x94
48#define AR934X_NFC_REG_FIFO_DATA 0x98
49#define AR934X_NFC_REG_TIME_MODE 0x9c
50#define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51#define AR934X_NFC_REG_FIFO_INIT 0xb0
52#define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
53
54#define AR934X_NFC_CMD_CMD_SEQ_S 0
55#define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56#define AR934X_NFC_CMD_SEQ_1C 0x00
57#define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58#define AR934X_NFC_CMD_SEQ_12 0x0c
59#define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60#define AR934X_NFC_CMD_SEQ_S 0x24
61#define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62#define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63#define AR934X_NFC_CMD_SEQ_18 0x32
64#define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65#define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66#define AR934X_NFC_CMD_ADDR_SEL_0 0
67#define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68#define AR934X_NFC_CMD_CMD0_S 8
69#define AR934X_NFC_CMD_CMD0_M 0xff
70#define AR934X_NFC_CMD_CMD1_S 16
71#define AR934X_NFC_CMD_CMD1_M 0xff
72#define AR934X_NFC_CMD_CMD2_S 24
73#define AR934X_NFC_CMD_CMD2_M 0xff
74
75#define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76#define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77#define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78#define AR934X_NFC_CTRL_INT_EN BIT(4)
79#define AR934X_NFC_CTRL_ECC_EN BIT(5)
80#define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81#define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82#define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83#define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84#define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85#define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86#define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87#define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88#define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89#define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90#define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91#define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92#define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93#define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94#define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95#define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96#define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97#define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98#define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99#define AR934X_NFC_CTRL_PROT_EN BIT(14)
100#define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101#define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102#define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103#define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104#define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105#define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106#define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
107
108#define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109#define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110#define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111#define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112#define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113#define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114#define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115#define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116#define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117#define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118#define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119#define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120#define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
121
122#define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123#define AR934X_NFC_INT_CMD_END BIT(1)
124
125/* default timing values */
126#define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
127#define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
128#define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
129
130#define AR934X_NFC_ID_BUF_SIZE 8
131#define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
132#define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
133#define AR934X_NFC_DONE_TIMEOUT 1000
134#define AR934X_NFC_DMA_RETRIES 20
135
136#define AR934X_NFC_USE_IRQ true
137#define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
138
139#define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
140
141#undef AR934X_NFC_DEBUG_DATA
142#undef AR934X_NFC_DEBUG
143
144struct ar934x_nfc;
145
146static inline __attribute__ ((format (printf, 2, 3)))
147void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
148{
149}
150
151#ifdef AR934X_NFC_DEBUG
152#define nfc_dbg(_nfc, fmt, ...) \
153    dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
154#else
155#define nfc_dbg(_nfc, fmt, ...) \
156    _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
157#endif /* AR934X_NFC_DEBUG */
158
159#ifdef AR934X_NFC_DEBUG_DATA
160static void
161nfc_debug_data(const char *label, void *data, int len)
162{
163    print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
164               data, len, 0);
165}
166#else
167static inline void
168nfc_debug_data(const char *label, void *data, int len) {}
169#endif /* AR934X_NFC_DEBUG_DATA */
170
171struct ar934x_nfc {
172    struct mtd_info mtd;
173    struct nand_chip nand_chip;
174    struct device *parent;
175    void __iomem *base;
176    void (*select_chip)(int chip_no);
177    int irq;
178    wait_queue_head_t irq_waitq;
179
180    bool spurious_irq_expected;
181    u32 irq_status;
182
183    u32 ctrl_reg;
184    bool small_page;
185    unsigned int addr_count0;
186    unsigned int addr_count1;
187
188    u8 *buf;
189    dma_addr_t buf_dma;
190    unsigned int buf_size;
191    int buf_index;
192
193    int erase1_page_addr;
194
195    int rndout_page_addr;
196    int rndout_read_cmd;
197
198    int seqin_page_addr;
199    int seqin_column;
200    int seqin_read_cmd;
201};
202
203static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
204
205static inline void
206ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
207{
208    __raw_writel(val, nfc->base + reg);
209}
210
211static inline u32
212ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
213{
214    return __raw_readl(nfc->base + reg);
215}
216
217static inline struct ar934x_nfc_platform_data *
218ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
219{
220    return nfc->parent->platform_data;
221}
222
223static inline struct
224ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
225{
226    return container_of(mtd, struct ar934x_nfc, mtd);
227}
228
229static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
230{
231    return AR934X_NFC_USE_IRQ;
232}
233
234static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
235{
236    wmb();
237
238    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
239    /* flush write */
240    ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
241}
242
243static bool
244__ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
245{
246    u32 status;
247
248    status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
249    return (status & 0xff) == 0xff;
250}
251
252static inline bool
253__ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
254{
255    u32 status;
256
257    status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
258    return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
259}
260
261static int
262ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
263{
264    unsigned long timeout;
265
266    timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
267    do {
268        if (__ar934x_nfc_dev_ready(nfc))
269            return 0;
270    } while time_before(jiffies, timeout);
271
272    nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
273        ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
274        ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
275    return -ETIMEDOUT;
276}
277
278static int
279ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
280{
281    unsigned long timeout;
282
283    timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
284    do {
285        if (__ar934x_nfc_is_dma_ready(nfc))
286            return 0;
287    } while time_before(jiffies, timeout);
288
289    nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
290        ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
291    return -ETIMEDOUT;
292}
293
294static int
295ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
296{
297    long timeout;
298    int ret;
299
300    timeout = wait_event_timeout(nfc->irq_waitq,
301                (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
302                msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
303
304    ret = 0;
305    if (!timeout) {
306        ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
307        ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
308        /* flush write */
309        ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
310
311        nfc_dbg(nfc,
312            "timeout waiting for interrupt, status:%08x\n",
313            nfc->irq_status);
314        ret = -ETIMEDOUT;
315    }
316
317    nfc->irq_status = 0;
318    return ret;
319}
320
321static int
322ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
323{
324    int ret;
325
326    if (ar934x_nfc_use_irq(nfc))
327        ret = ar934x_nfc_wait_irq(nfc);
328    else
329        ret = ar934x_nfc_wait_dev_ready(nfc);
330
331    if (ret)
332        return ret;
333
334    return ar934x_nfc_wait_dma_ready(nfc);
335}
336
337static int
338ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
339{
340    nfc->buf = dma_alloc_coherent(nfc->parent, size,
341                      &nfc->buf_dma, GFP_KERNEL);
342    if (nfc->buf == NULL) {
343        dev_err(nfc->parent, "no memory for DMA buffer\n");
344        return -ENOMEM;
345    }
346
347    nfc->buf_size = size;
348    nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
349
350    return 0;
351}
352
353static void
354ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
355{
356    dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
357}
358
359static void
360ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr,
361            u32 *addr0, u32 *addr1)
362{
363    u32 a0, a1;
364
365    a0 = 0;
366    a1 = 0;
367
368    if (column == -1) {
369        /* ERASE1 */
370        a0 = (page_addr & 0xffff) << 16;
371        a1 = (page_addr >> 16) & 0xf;
372    } else if (page_addr != -1) {
373        /* SEQIN, READ0, etc.. */
374
375        /* TODO: handle 16bit bus width */
376        if (nfc->small_page) {
377            a0 = column & 0xff;
378            a0 |= (page_addr & 0xff) << 8;
379            a0 |= ((page_addr >> 8) & 0xff) << 16;
380            a0 |= ((page_addr >> 16) & 0xff) << 24;
381        } else {
382            a0 = column & 0x0FFF;
383            a0 |= (page_addr & 0xffff) << 16;
384
385            if (nfc->addr_count0 > 4)
386                a1 = (page_addr >> 16) & 0xf;
387        }
388    }
389
390    *addr0 = a0;
391    *addr1 = a1;
392}
393
394static void
395ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
396{
397    u32 cmd_reg;
398
399    cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
400          AR934X_NFC_CMD_SEQ_1C;
401    cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
402
403    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
404    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
405
406    ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
407    ar934x_nfc_wait_dev_ready(nfc);
408}
409
410static void
411ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr,
412             int len, u32 cmd_reg, u32 ctrl_reg, bool write)
413{
414    u32 addr0, addr1;
415    u32 dma_ctrl;
416    int dir;
417    int err;
418    int retries = 0;
419
420    WARN_ON(len & 3);
421
422    if (WARN_ON(len > nfc->buf_size))
423        dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size);
424
425    if (write) {
426        dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
427        dir = DMA_TO_DEVICE;
428    } else {
429        dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
430        dir = DMA_FROM_DEVICE;
431    }
432
433    ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
434
435    dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
436            (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
437             AR934X_NFC_DMA_CTRL_DMA_BURST_S);
438
439    cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
440    ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
441
442    nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
443        (write) ? "write" : "read",
444        addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
445
446retry:
447    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
448    ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
449    ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
450    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
451    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
452    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
453    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
454    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
455
456    if (ar934x_nfc_use_irq(nfc)) {
457        ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
458        /* flush write */
459        ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
460    }
461
462    ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
463    err = ar934x_nfc_wait_done(nfc);
464    if (err) {
465        dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
466            (write) ? "write" : "read", page_addr);
467
468        ar934x_nfc_restart(nfc);
469        if (retries++ < AR934X_NFC_DMA_RETRIES)
470            goto retry;
471
472        dev_err(nfc->parent, "%s operation failed on page %d\n",
473            (write) ? "write" : "read", page_addr);
474    }
475}
476
477static void
478ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
479{
480    u32 cmd_reg;
481
482    nfc_dbg(nfc, "readid, cmd:%02x\n", command);
483
484    cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
485    cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
486
487    ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE, cmd_reg,
488                 nfc->ctrl_reg, false);
489
490    nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
491}
492
493static void
494ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column,
495             int page_addr, int len)
496{
497    u32 cmd_reg;
498
499    nfc_dbg(nfc, "read, column=%d page=%d len=%d\n",
500        column, page_addr, len);
501
502    cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
503
504    if (nfc->small_page) {
505        cmd_reg |= AR934X_NFC_CMD_SEQ_18;
506    } else {
507        cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
508        cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
509    }
510
511    ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
512                 cmd_reg, nfc->ctrl_reg, false);
513
514    nfc_debug_data("[data] ", nfc->buf, len);
515}
516
517static void
518ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column,
519              int page_addr)
520{
521    u32 addr0, addr1;
522    u32 ctrl_reg;
523    u32 cmd_reg;
524
525    ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
526
527    ctrl_reg = nfc->ctrl_reg;
528    if (nfc->small_page) {
529        /* override number of address cycles for the erase command */
530        ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
531                  AR934X_NFC_CTRL_ADDR_CYCLE0_S);
532        ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
533                  AR934X_NFC_CTRL_ADDR_CYCLE1_S);
534        ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
535        ctrl_reg |= (nfc->addr_count0 + 1) <<
536                AR934X_NFC_CTRL_ADDR_CYCLE0_S;
537    }
538
539    cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
540    cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
541    cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
542
543    nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
544        page_addr, addr0, addr1, cmd_reg, ctrl_reg);
545
546    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
547    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
548    ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
549    ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
550
551    ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
552    ar934x_nfc_wait_dev_ready(nfc);
553}
554
555static void
556ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column,
557             int page_addr, int len)
558{
559    u32 cmd_reg;
560
561    nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
562        column, page_addr, len);
563
564    nfc_debug_data("[data] ", nfc->buf, len);
565
566    cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
567    cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
568    cmd_reg |= AR934X_NFC_CMD_SEQ_12;
569
570    ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
571                 cmd_reg, nfc->ctrl_reg, true);
572}
573
574static void
575ar934x_nfc_read_status(struct ar934x_nfc *nfc)
576{
577    u32 cmd_reg;
578    u32 status;
579
580    cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
581    cmd_reg |= AR934X_NFC_CMD_SEQ_S;
582
583    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
584    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
585
586    ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
587    ar934x_nfc_wait_dev_ready(nfc);
588
589    status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
590
591    nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
592        cmd_reg, (status & 0xff));
593
594    nfc->buf[0 ^ 3] = status;
595}
596
597static void
598ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
599           int page_addr)
600{
601    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
602
603    if (command != NAND_CMD_PAGEPROG)
604        nfc->buf_index = 0;
605
606    switch (command) {
607    case NAND_CMD_RESET:
608        ar934x_nfc_send_cmd(nfc, command);
609        break;
610
611    case NAND_CMD_READID:
612        ar934x_nfc_send_readid(nfc, command);
613        break;
614
615    case NAND_CMD_READ0:
616    case NAND_CMD_READ1:
617        if (nfc->small_page) {
618            ar934x_nfc_send_read(nfc, command, column, page_addr,
619                         mtd->writesize + mtd->oobsize);
620        } else {
621            ar934x_nfc_send_read(nfc, command, 0, page_addr,
622                         mtd->writesize + mtd->oobsize);
623            nfc->buf_index = column;
624            nfc->rndout_page_addr = page_addr;
625            nfc->rndout_read_cmd = command;
626        }
627        break;
628
629    case NAND_CMD_READOOB:
630        if (nfc->small_page)
631            ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
632                         column, page_addr,
633                         mtd->oobsize);
634        else
635            ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
636                         mtd->writesize, page_addr,
637                         mtd->oobsize);
638        break;
639
640    case NAND_CMD_RNDOUT:
641        if (WARN_ON(nfc->small_page))
642            break;
643
644        /* emulate subpage read */
645        ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
646                     nfc->rndout_page_addr,
647                     mtd->writesize + mtd->oobsize);
648        nfc->buf_index = column;
649        break;
650
651    case NAND_CMD_ERASE1:
652        nfc->erase1_page_addr = page_addr;
653        break;
654
655    case NAND_CMD_ERASE2:
656        ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
657        break;
658
659    case NAND_CMD_STATUS:
660        ar934x_nfc_read_status(nfc);
661        break;
662
663    case NAND_CMD_SEQIN:
664        if (nfc->small_page) {
665            /* output read command */
666            if (column >= mtd->writesize) {
667                column -= mtd->writesize;
668                nfc->seqin_read_cmd = NAND_CMD_READOOB;
669            } else if (column < 256) {
670                nfc->seqin_read_cmd = NAND_CMD_READ0;
671            } else {
672                column -= 256;
673                nfc->seqin_read_cmd = NAND_CMD_READ1;
674            }
675        } else {
676            nfc->seqin_read_cmd = NAND_CMD_READ0;
677        }
678        nfc->seqin_column = column;
679        nfc->seqin_page_addr = page_addr;
680        break;
681
682    case NAND_CMD_PAGEPROG:
683        if (nfc->small_page)
684            ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
685
686        ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
687                      nfc->seqin_page_addr,
688                      nfc->buf_index);
689        break;
690
691    default:
692        dev_err(nfc->parent,
693            "unsupported command: %x, column:%d page_addr=%d\n",
694            command, column, page_addr);
695        break;
696    }
697}
698
699static int
700ar934x_nfc_dev_ready(struct mtd_info *mtd)
701{
702    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
703
704    return __ar934x_nfc_dev_ready(nfc);
705}
706
707static void
708ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no)
709{
710    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
711
712    if (nfc->select_chip)
713        nfc->select_chip(chip_no);
714}
715
716static u8
717ar934x_nfc_read_byte(struct mtd_info *mtd)
718{
719    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
720    unsigned int buf_index;
721    u8 data;
722
723    WARN_ON(nfc->buf_index >= nfc->buf_size);
724
725    buf_index = nfc->buf_index ^ 3;
726    data = nfc->buf[buf_index];
727    nfc->buf_index++;
728
729    return data;
730}
731
732static void
733ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
734{
735    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
736    int i;
737
738    WARN_ON(nfc->buf_index + len > nfc->buf_size);
739
740    for (i = 0; i < len; i++) {
741        nfc->buf[nfc->buf_index ^ 3] = buf[i];
742        nfc->buf_index++;
743    }
744}
745
746static void
747ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
748{
749    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
750    int buf_index;
751    int i;
752
753    WARN_ON(nfc->buf_index + len > nfc->buf_size);
754
755    buf_index = nfc->buf_index;
756
757    for (i = 0; i < len; i++) {
758        buf[i] = nfc->buf[buf_index ^ 3];
759        buf_index++;
760    }
761
762    nfc->buf_index = buf_index;
763}
764
765static int
766ar934x_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
767{
768    int i;
769
770    for (i = 0; i < len; i++)
771        if (buf[i] != ar934x_nfc_read_byte(mtd))
772            return -EFAULT;
773
774    return 0;
775}
776
777static void
778ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
779{
780    struct ar934x_nfc_platform_data *pdata;
781
782    pdata = ar934x_nfc_get_platform_data(nfc);
783    if (pdata->hw_reset) {
784        pdata->hw_reset(true);
785        pdata->hw_reset(false);
786    }
787
788    /*
789     * setup timings
790     * TODO: make it configurable via platform data
791     */
792    ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
793              AR934X_NFC_TIME_SEQ_DEFAULT);
794    ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
795              AR934X_NFC_TIMINGS_ASYN_DEFAULT);
796    ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
797              AR934X_NFC_TIMINGS_SYN_DEFAULT);
798
799    /* disable WP on all chips, and select chip 0 */
800    ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
801
802    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
803
804    /* initialize Control register */
805    nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
806    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
807
808    if (nfc->small_page) {
809        /* Setup generic sequence register for small page reads. */
810        ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
811                  AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
812    }
813}
814
815static void
816ar934x_nfc_restart(struct ar934x_nfc *nfc)
817{
818    u32 ctrl_reg;
819
820    if (nfc->select_chip)
821        nfc->select_chip(-1);
822
823    ctrl_reg = nfc->ctrl_reg;
824    ar934x_nfc_hw_init(nfc);
825    nfc->ctrl_reg = ctrl_reg;
826
827    if (nfc->select_chip)
828        nfc->select_chip(0);
829
830    ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
831}
832
833static irqreturn_t
834ar934x_nfc_irq_handler(int irq, void *data)
835{
836    struct ar934x_nfc *nfc = data;
837    u32 status;
838
839    status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
840
841    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
842    /* flush write */
843    ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
844
845    status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
846    if (status) {
847        nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
848
849        nfc->irq_status = status;
850        nfc->spurious_irq_expected = true;
851        wake_up(&nfc->irq_waitq);
852    } else {
853        if (nfc->spurious_irq_expected) {
854            nfc->spurious_irq_expected = false;
855        } else {
856            dev_warn(nfc->parent, "spurious interrupt\n");
857        }
858    }
859
860    return IRQ_HANDLED;
861}
862
863static int __devinit
864ar934x_nfc_init_tail(struct mtd_info *mtd)
865{
866    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
867    struct nand_chip *chip = &nfc->nand_chip;
868    u32 ctrl;
869    u32 t;
870    int err;
871
872    switch (mtd->oobsize) {
873    case 16:
874    case 64:
875    case 128:
876        ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
877        break;
878
879    default:
880        dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
881            mtd->oobsize);
882        return -ENXIO;
883    }
884
885    ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
886
887    switch (mtd->erasesize / mtd->writesize) {
888    case 32:
889        t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
890        break;
891
892    case 64:
893        t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
894        break;
895
896    case 128:
897        t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
898        break;
899
900    case 256:
901        t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
902        break;
903
904    default:
905        dev_err(nfc->parent, "unsupported block size: %u\n",
906            mtd->erasesize / mtd->writesize);
907        return -ENXIO;
908    }
909
910    ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
911
912    switch (mtd->writesize) {
913    case 256:
914        nfc->small_page = 1;
915        t = AR934X_NFC_CTRL_PAGE_SIZE_256;
916        break;
917
918    case 512:
919        nfc->small_page = 1;
920        t = AR934X_NFC_CTRL_PAGE_SIZE_512;
921        break;
922
923    case 1024:
924        t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
925        break;
926
927    case 2048:
928        t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
929        break;
930
931    case 4096:
932        t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
933        break;
934
935    case 8192:
936        t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
937        break;
938
939    case 16384:
940        t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
941        break;
942
943    default:
944        dev_err(nfc->parent, "unsupported write size: %d bytes\n",
945            mtd->writesize);
946        return -ENXIO;
947    }
948
949    ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
950
951    if (nfc->small_page) {
952        ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
953
954        if (chip->chipsize > (32 << 20)) {
955            nfc->addr_count0 = 4;
956            nfc->addr_count1 = 3;
957        } else if (chip->chipsize > (2 << 16)) {
958            nfc->addr_count0 = 3;
959            nfc->addr_count1 = 2;
960        } else {
961            nfc->addr_count0 = 2;
962            nfc->addr_count1 = 1;
963        }
964    } else {
965        if (chip->chipsize > (128 << 20)) {
966            nfc->addr_count0 = 5;
967            nfc->addr_count1 = 3;
968        } else if (chip->chipsize > (8 << 16)) {
969            nfc->addr_count0 = 4;
970            nfc->addr_count1 = 2;
971        } else {
972            nfc->addr_count0 = 3;
973            nfc->addr_count1 = 1;
974        }
975    }
976
977    ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
978    ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
979
980    nfc->ctrl_reg = ctrl;
981    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
982
983    ar934x_nfc_free_buf(nfc);
984    err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
985
986    return err;
987}
988
989static int __devinit
990ar934x_nfc_probe(struct platform_device *pdev)
991{
992    static const char *part_probes[] = { "cmdlinepart", NULL, };
993    struct ar934x_nfc_platform_data *pdata;
994    struct ar934x_nfc *nfc;
995    struct resource *res;
996    struct mtd_info *mtd;
997    struct nand_chip *nand;
998    struct mtd_part_parser_data ppdata;
999    int ret;
1000
1001    pdata = pdev->dev.platform_data;
1002    if (pdata == NULL) {
1003        dev_err(&pdev->dev, "no platform data defined\n");
1004        return -EINVAL;
1005    }
1006
1007    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1008    if (!res) {
1009        dev_err(&pdev->dev, "failed to get I/O memory\n");
1010        return -EINVAL;
1011    }
1012
1013    nfc = kzalloc(sizeof(struct ar934x_nfc), GFP_KERNEL);
1014    if (!nfc) {
1015        dev_err(&pdev->dev, "failed to allocate driver data\n");
1016        return -ENOMEM;
1017    }
1018
1019    nfc->base = ioremap(res->start, resource_size(res));
1020    if (nfc->base == NULL) {
1021        dev_err(&pdev->dev, "failed to remap I/O memory\n");
1022        ret = -ENXIO;
1023        goto err_free_nand;
1024    }
1025
1026    nfc->irq = platform_get_irq(pdev, 0);
1027    if (nfc->irq < 0) {
1028        dev_err(&pdev->dev, "no IRQ resource specified\n");
1029        ret = -EINVAL;
1030        goto err_unmap;
1031    }
1032
1033    init_waitqueue_head(&nfc->irq_waitq);
1034    ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, IRQF_DISABLED,
1035              dev_name(&pdev->dev), nfc);
1036    if (ret) {
1037        dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret);
1038        goto err_unmap;
1039    }
1040
1041    nfc->parent = &pdev->dev;
1042    nfc->select_chip = pdata->select_chip;
1043
1044    nand = &nfc->nand_chip;
1045    mtd = &nfc->mtd;
1046
1047    mtd->priv = nand;
1048    mtd->owner = THIS_MODULE;
1049    if (pdata->name)
1050        mtd->name = pdata->name;
1051    else
1052        mtd->name = dev_name(&pdev->dev);
1053
1054    nand->options = NAND_NO_AUTOINCR;
1055    nand->chip_delay = 25;
1056    nand->ecc.mode = NAND_ECC_SOFT;
1057
1058    nand->dev_ready = ar934x_nfc_dev_ready;
1059    nand->cmdfunc = ar934x_nfc_cmdfunc;
1060    nand->read_byte = ar934x_nfc_read_byte;
1061    nand->write_buf = ar934x_nfc_write_buf;
1062    nand->read_buf = ar934x_nfc_read_buf;
1063    nand->verify_buf = ar934x_nfc_verify_buf;
1064    nand->select_chip = ar934x_nfc_select_chip;
1065
1066    ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1067    if (ret)
1068        goto err_free_irq;
1069
1070    platform_set_drvdata(pdev, nfc);
1071
1072    ar934x_nfc_hw_init(nfc);
1073
1074    ret = nand_scan_ident(mtd, 1, NULL);
1075    if (ret) {
1076        dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret);
1077        goto err_free_buf;
1078    }
1079
1080    ret = ar934x_nfc_init_tail(mtd);
1081    if (ret) {
1082        dev_err(&pdev->dev, "init tail failed, err:%d\n", ret);
1083        goto err_free_buf;
1084    }
1085
1086    if (pdata->scan_fixup) {
1087        ret = pdata->scan_fixup(mtd);
1088        if (ret)
1089            goto err_free_buf;
1090    }
1091
1092    ret = nand_scan_tail(mtd);
1093    if (ret) {
1094        dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
1095        goto err_free_buf;
1096    }
1097
1098    memset(&ppdata, '\0', sizeof(ppdata));
1099    ret = mtd_device_parse_register(mtd, part_probes, &ppdata,
1100                    pdata->parts, pdata->nr_parts);
1101    if (ret) {
1102        dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1103        goto err_free_buf;
1104    }
1105
1106    return 0;
1107
1108err_free_buf:
1109    ar934x_nfc_free_buf(nfc);
1110err_free_irq:
1111    free_irq(nfc->irq, nfc);
1112err_unmap:
1113    iounmap(nfc->base);
1114err_free_nand:
1115    kfree(nfc);
1116    platform_set_drvdata(pdev, NULL);
1117    return ret;
1118}
1119
1120static int __devexit
1121ar934x_nfc_remove(struct platform_device *pdev)
1122{
1123    struct ar934x_nfc *nfc;
1124
1125    nfc = platform_get_drvdata(pdev);
1126    if (nfc) {
1127        nand_release(&nfc->mtd);
1128        ar934x_nfc_free_buf(nfc);
1129        free_irq(nfc->irq, nfc);
1130        iounmap(nfc->base);
1131        kfree(nfc);
1132    }
1133
1134    return 0;
1135}
1136
1137static struct platform_driver ar934x_nfc_driver = {
1138    .probe = ar934x_nfc_probe,
1139    .remove = __devexit_p(ar934x_nfc_remove),
1140    .driver = {
1141        .name = AR934X_NFC_DRIVER_NAME,
1142        .owner = THIS_MODULE,
1143    },
1144};
1145
1146module_platform_driver(ar934x_nfc_driver);
1147
1148MODULE_LICENSE("GPL v2");
1149MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1150MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1151MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
1152

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