Root/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c

1/*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include "ag71xx.h"
15
16#define AG71XX_DEFAULT_MSG_ENABLE \
17    (NETIF_MSG_DRV \
18    | NETIF_MSG_PROBE \
19    | NETIF_MSG_LINK \
20    | NETIF_MSG_TIMER \
21    | NETIF_MSG_IFDOWN \
22    | NETIF_MSG_IFUP \
23    | NETIF_MSG_RX_ERR \
24    | NETIF_MSG_TX_ERR)
25
26static int ag71xx_msg_level = -1;
27
28module_param_named(msg_level, ag71xx_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32{
33    DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34        ag->dev->name,
35        ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36        ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37        ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39    DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40        ag->dev->name,
41        ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42        ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43        ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44}
45
46static void ag71xx_dump_regs(struct ag71xx *ag)
47{
48    DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49        ag->dev->name,
50        ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51        ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52        ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53        ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54        ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55    DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56        ag->dev->name,
57        ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58        ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59        ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60    DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61        ag->dev->name,
62        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65    DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66        ag->dev->name,
67        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70}
71
72static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73{
74    DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75        ag->dev->name, label, intr,
76        (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77        (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78        (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79        (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80        (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81        (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82}
83
84static void ag71xx_ring_free(struct ag71xx_ring *ring)
85{
86    kfree(ring->buf);
87
88    if (ring->descs_cpu)
89        dma_free_coherent(NULL, ring->size * ring->desc_size,
90                  ring->descs_cpu, ring->descs_dma);
91}
92
93static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
94{
95    int err;
96    int i;
97
98    ring->desc_size = sizeof(struct ag71xx_desc);
99    if (ring->desc_size % cache_line_size()) {
100        DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101            ring, ring->desc_size,
102            roundup(ring->desc_size, cache_line_size()));
103        ring->desc_size = roundup(ring->desc_size, cache_line_size());
104    }
105
106    ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107                         &ring->descs_dma, GFP_ATOMIC);
108    if (!ring->descs_cpu) {
109        err = -ENOMEM;
110        goto err;
111    }
112
113
114    ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
115    if (!ring->buf) {
116        err = -ENOMEM;
117        goto err;
118    }
119
120    for (i = 0; i < ring->size; i++) {
121        int idx = i * ring->desc_size;
122        ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123        DBG("ag71xx: ring %p, desc %d at %p\n",
124            ring, i, ring->buf[i].desc);
125    }
126
127    return 0;
128
129err:
130    return err;
131}
132
133static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134{
135    struct ag71xx_ring *ring = &ag->tx_ring;
136    struct net_device *dev = ag->dev;
137    u32 bytes_compl = 0, pkts_compl = 0;
138
139    while (ring->curr != ring->dirty) {
140        u32 i = ring->dirty % ring->size;
141
142        if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143            ring->buf[i].desc->ctrl = 0;
144            dev->stats.tx_errors++;
145        }
146
147        if (ring->buf[i].skb) {
148            bytes_compl += ring->buf[i].skb->len;
149            pkts_compl++;
150            dev_kfree_skb_any(ring->buf[i].skb);
151        }
152        ring->buf[i].skb = NULL;
153        ring->dirty++;
154    }
155
156    /* flush descriptors */
157    wmb();
158
159    netdev_completed_queue(dev, pkts_compl, bytes_compl);
160}
161
162static void ag71xx_ring_tx_init(struct ag71xx *ag)
163{
164    struct ag71xx_ring *ring = &ag->tx_ring;
165    int i;
166
167    for (i = 0; i < ring->size; i++) {
168        ring->buf[i].desc->next = (u32) (ring->descs_dma +
169            ring->desc_size * ((i + 1) % ring->size));
170
171        ring->buf[i].desc->ctrl = DESC_EMPTY;
172        ring->buf[i].skb = NULL;
173    }
174
175    /* flush descriptors */
176    wmb();
177
178    ring->curr = 0;
179    ring->dirty = 0;
180    netdev_reset_queue(ag->dev);
181}
182
183static void ag71xx_ring_rx_clean(struct ag71xx *ag)
184{
185    struct ag71xx_ring *ring = &ag->rx_ring;
186    int i;
187
188    if (!ring->buf)
189        return;
190
191    for (i = 0; i < ring->size; i++)
192        if (ring->buf[i].rx_buf) {
193            dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
194                     AG71XX_RX_BUF_SIZE, DMA_FROM_DEVICE);
195            kfree(ring->buf[i].rx_buf);
196        }
197}
198
199static int ag71xx_buffer_offset(struct ag71xx *ag)
200{
201    int offset = NET_SKB_PAD;
202
203    /*
204     * On AR71xx/AR91xx packets must be 4-byte aligned.
205     *
206     * When using builtin AR8216 support, hardware adds a 2-byte header,
207     * so we don't need any extra alignment in that case.
208     */
209    if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
210        return offset;
211
212    return offset + NET_IP_ALIGN;
213}
214
215static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
216                   int offset)
217{
218    void *data;
219
220    data = kmalloc(AG71XX_RX_BUF_SIZE +
221               SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
222               GFP_ATOMIC);
223    if (!data)
224        return false;
225
226    buf->rx_buf = data;
227    buf->dma_addr = dma_map_single(&ag->dev->dev, data,
228                       AG71XX_RX_BUF_SIZE, DMA_FROM_DEVICE);
229    buf->desc->data = (u32) buf->dma_addr + offset;
230    return true;
231}
232
233static int ag71xx_ring_rx_init(struct ag71xx *ag)
234{
235    struct ag71xx_ring *ring = &ag->rx_ring;
236    unsigned int i;
237    int ret;
238    int offset = ag71xx_buffer_offset(ag);
239
240    ret = 0;
241    for (i = 0; i < ring->size; i++) {
242        ring->buf[i].desc->next = (u32) (ring->descs_dma +
243            ring->desc_size * ((i + 1) % ring->size));
244
245        DBG("ag71xx: RX desc at %p, next is %08x\n",
246            ring->buf[i].desc,
247            ring->buf[i].desc->next);
248    }
249
250    for (i = 0; i < ring->size; i++) {
251        if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
252            ret = -ENOMEM;
253            break;
254        }
255
256        ring->buf[i].desc->ctrl = DESC_EMPTY;
257    }
258
259    /* flush descriptors */
260    wmb();
261
262    ring->curr = 0;
263    ring->dirty = 0;
264
265    return ret;
266}
267
268static int ag71xx_ring_rx_refill(struct ag71xx *ag)
269{
270    struct ag71xx_ring *ring = &ag->rx_ring;
271    unsigned int count;
272    int offset = ag71xx_buffer_offset(ag);
273
274    count = 0;
275    for (; ring->curr - ring->dirty > 0; ring->dirty++) {
276        unsigned int i;
277
278        i = ring->dirty % ring->size;
279
280        if (!ring->buf[i].rx_buf &&
281            !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
282            break;
283
284        ring->buf[i].desc->ctrl = DESC_EMPTY;
285        count++;
286    }
287
288    /* flush descriptors */
289    wmb();
290
291    DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
292
293    return count;
294}
295
296static int ag71xx_rings_init(struct ag71xx *ag)
297{
298    int ret;
299
300    ret = ag71xx_ring_alloc(&ag->tx_ring);
301    if (ret)
302        return ret;
303
304    ag71xx_ring_tx_init(ag);
305
306    ret = ag71xx_ring_alloc(&ag->rx_ring);
307    if (ret)
308        return ret;
309
310    ret = ag71xx_ring_rx_init(ag);
311    return ret;
312}
313
314static void ag71xx_rings_cleanup(struct ag71xx *ag)
315{
316    ag71xx_ring_rx_clean(ag);
317    ag71xx_ring_free(&ag->rx_ring);
318
319    ag71xx_ring_tx_clean(ag);
320    netdev_reset_queue(ag->dev);
321    ag71xx_ring_free(&ag->tx_ring);
322}
323
324static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
325{
326    switch (ag->speed) {
327    case SPEED_1000:
328        return "1000";
329    case SPEED_100:
330        return "100";
331    case SPEED_10:
332        return "10";
333    }
334
335    return "?";
336}
337
338static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
339{
340    u32 t;
341
342    t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
343      | (((u32) mac[3]) << 8) | ((u32) mac[2]);
344
345    ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
346
347    t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
348    ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
349}
350
351static void ag71xx_dma_reset(struct ag71xx *ag)
352{
353    u32 val;
354    int i;
355
356    ag71xx_dump_dma_regs(ag);
357
358    /* stop RX and TX */
359    ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
360    ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
361
362    /*
363     * give the hardware some time to really stop all rx/tx activity
364     * clearing the descriptors too early causes random memory corruption
365     */
366    mdelay(1);
367
368    /* clear descriptor addresses */
369    ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
370    ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
371
372    /* clear pending RX/TX interrupts */
373    for (i = 0; i < 256; i++) {
374        ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
375        ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
376    }
377
378    /* clear pending errors */
379    ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
380    ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
381
382    val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
383    if (val)
384        pr_alert("%s: unable to clear DMA Rx status: %08x\n",
385             ag->dev->name, val);
386
387    val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
388
389    /* mask out reserved bits */
390    val &= ~0xff000000;
391
392    if (val)
393        pr_alert("%s: unable to clear DMA Tx status: %08x\n",
394             ag->dev->name, val);
395
396    ag71xx_dump_dma_regs(ag);
397}
398
399#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
400             MAC_CFG1_SRX | MAC_CFG1_STX)
401
402#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
403
404#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
405             FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
406             FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
407             FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
408             FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
409             FIFO_CFG4_VT)
410
411#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
412             FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
413             FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
414             FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
415             FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
416             FIFO_CFG5_17 | FIFO_CFG5_SF)
417
418static void ag71xx_hw_stop(struct ag71xx *ag)
419{
420    /* disable all interrupts and stop the rx/tx engine */
421    ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
422    ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
423    ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
424}
425
426static void ag71xx_hw_setup(struct ag71xx *ag)
427{
428    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
429
430    /* setup MAC configuration registers */
431    ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
432
433    ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
434          MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
435
436    /* setup max frame length */
437    ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
438
439    /* setup FIFO configuration registers */
440    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
441    if (pdata->is_ar724x) {
442        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
443        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
444    } else {
445        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
446        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
447    }
448    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
449    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
450}
451
452static void ag71xx_hw_init(struct ag71xx *ag)
453{
454    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
455    u32 reset_mask = pdata->reset_bit;
456
457    ag71xx_hw_stop(ag);
458
459    if (pdata->is_ar724x) {
460        u32 reset_phy = reset_mask;
461
462        reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
463        reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
464
465        ath79_device_reset_set(reset_phy);
466        mdelay(50);
467        ath79_device_reset_clear(reset_phy);
468        mdelay(200);
469    }
470
471    ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
472    udelay(20);
473
474    ath79_device_reset_set(reset_mask);
475    mdelay(100);
476    ath79_device_reset_clear(reset_mask);
477    mdelay(200);
478
479    ag71xx_hw_setup(ag);
480
481    ag71xx_dma_reset(ag);
482}
483
484static void ag71xx_fast_reset(struct ag71xx *ag)
485{
486    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
487    struct net_device *dev = ag->dev;
488    u32 reset_mask = pdata->reset_bit;
489    u32 rx_ds, tx_ds;
490    u32 mii_reg;
491
492    reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
493
494    mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
495    rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
496    tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
497
498    ath79_device_reset_set(reset_mask);
499    udelay(10);
500    ath79_device_reset_clear(reset_mask);
501    udelay(10);
502
503    ag71xx_dma_reset(ag);
504    ag71xx_hw_setup(ag);
505
506    ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
507    ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
508    ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
509
510    ag71xx_hw_set_macaddr(ag, dev->dev_addr);
511}
512
513static void ag71xx_hw_start(struct ag71xx *ag)
514{
515    /* start RX engine */
516    ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
517
518    /* enable interrupts */
519    ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
520}
521
522void ag71xx_link_adjust(struct ag71xx *ag)
523{
524    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
525    u32 cfg2;
526    u32 ifctl;
527    u32 fifo5;
528
529    if (!ag->link) {
530        ag71xx_hw_stop(ag);
531        netif_carrier_off(ag->dev);
532        if (netif_msg_link(ag))
533            pr_info("%s: link down\n", ag->dev->name);
534        return;
535    }
536
537    if (pdata->is_ar724x)
538        ag71xx_fast_reset(ag);
539
540    cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
541    cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
542    cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
543
544    ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
545    ifctl &= ~(MAC_IFCTL_SPEED);
546
547    fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
548    fifo5 &= ~FIFO_CFG5_BM;
549
550    switch (ag->speed) {
551    case SPEED_1000:
552        cfg2 |= MAC_CFG2_IF_1000;
553        fifo5 |= FIFO_CFG5_BM;
554        break;
555    case SPEED_100:
556        cfg2 |= MAC_CFG2_IF_10_100;
557        ifctl |= MAC_IFCTL_SPEED;
558        break;
559    case SPEED_10:
560        cfg2 |= MAC_CFG2_IF_10_100;
561        break;
562    default:
563        BUG();
564        return;
565    }
566
567    if (pdata->is_ar91xx)
568        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
569    else if (pdata->is_ar724x)
570        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
571    else
572        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
573
574    if (pdata->set_speed)
575        pdata->set_speed(ag->speed);
576
577    ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
578    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
579    ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
580    ag71xx_hw_start(ag);
581
582    netif_carrier_on(ag->dev);
583    if (netif_msg_link(ag))
584        pr_info("%s: link up (%sMbps/%s duplex)\n",
585            ag->dev->name,
586            ag71xx_speed_str(ag),
587            (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
588
589    DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
590        ag->dev->name,
591        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
592        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
593        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
594
595    DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
596        ag->dev->name,
597        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
598        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
599        ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
600
601    DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
602        ag->dev->name,
603        ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
604        ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
605}
606
607static int ag71xx_open(struct net_device *dev)
608{
609    struct ag71xx *ag = netdev_priv(dev);
610    int ret;
611
612    ret = ag71xx_rings_init(ag);
613    if (ret)
614        goto err;
615
616    napi_enable(&ag->napi);
617
618    netif_carrier_off(dev);
619    ag71xx_phy_start(ag);
620
621    ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
622    ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
623
624    ag71xx_hw_set_macaddr(ag, dev->dev_addr);
625
626    netif_start_queue(dev);
627
628    return 0;
629
630err:
631    ag71xx_rings_cleanup(ag);
632    return ret;
633}
634
635static int ag71xx_stop(struct net_device *dev)
636{
637    struct ag71xx *ag = netdev_priv(dev);
638    unsigned long flags;
639
640    netif_carrier_off(dev);
641    ag71xx_phy_stop(ag);
642
643    spin_lock_irqsave(&ag->lock, flags);
644
645    netif_stop_queue(dev);
646
647    ag71xx_hw_stop(ag);
648    ag71xx_dma_reset(ag);
649
650    napi_disable(&ag->napi);
651    del_timer_sync(&ag->oom_timer);
652
653    spin_unlock_irqrestore(&ag->lock, flags);
654
655    ag71xx_rings_cleanup(ag);
656
657    return 0;
658}
659
660static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
661                      struct net_device *dev)
662{
663    struct ag71xx *ag = netdev_priv(dev);
664    struct ag71xx_ring *ring = &ag->tx_ring;
665    struct ag71xx_desc *desc;
666    dma_addr_t dma_addr;
667    int i;
668
669    i = ring->curr % ring->size;
670    desc = ring->buf[i].desc;
671
672    if (!ag71xx_desc_empty(desc))
673        goto err_drop;
674
675    if (ag71xx_has_ar8216(ag))
676        ag71xx_add_ar8216_header(ag, skb);
677
678    if (skb->len <= 0) {
679        DBG("%s: packet len is too small\n", ag->dev->name);
680        goto err_drop;
681    }
682
683    dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
684                  DMA_TO_DEVICE);
685
686    netdev_sent_queue(dev, skb->len);
687    ring->buf[i].skb = skb;
688    ring->buf[i].timestamp = jiffies;
689
690    /* setup descriptor fields */
691    desc->data = (u32) dma_addr;
692    desc->ctrl = (skb->len & DESC_PKTLEN_M);
693
694    /* flush descriptor */
695    wmb();
696
697    ring->curr++;
698    if (ring->curr == (ring->dirty + ring->size)) {
699        DBG("%s: tx queue full\n", ag->dev->name);
700        netif_stop_queue(dev);
701    }
702
703    DBG("%s: packet injected into TX queue\n", ag->dev->name);
704
705    /* enable TX engine */
706    ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
707
708    return NETDEV_TX_OK;
709
710err_drop:
711    dev->stats.tx_dropped++;
712
713    dev_kfree_skb(skb);
714    return NETDEV_TX_OK;
715}
716
717static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
718{
719    struct ag71xx *ag = netdev_priv(dev);
720    int ret;
721
722    switch (cmd) {
723    case SIOCETHTOOL:
724        if (ag->phy_dev == NULL)
725            break;
726
727        spin_lock_irq(&ag->lock);
728        ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
729        spin_unlock_irq(&ag->lock);
730        return ret;
731
732    case SIOCSIFHWADDR:
733        if (copy_from_user
734            (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
735            return -EFAULT;
736        return 0;
737
738    case SIOCGIFHWADDR:
739        if (copy_to_user
740            (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
741            return -EFAULT;
742        return 0;
743
744    case SIOCGMIIPHY:
745    case SIOCGMIIREG:
746    case SIOCSMIIREG:
747        if (ag->phy_dev == NULL)
748            break;
749
750        return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
751
752    default:
753        break;
754    }
755
756    return -EOPNOTSUPP;
757}
758
759static void ag71xx_oom_timer_handler(unsigned long data)
760{
761    struct net_device *dev = (struct net_device *) data;
762    struct ag71xx *ag = netdev_priv(dev);
763
764    napi_schedule(&ag->napi);
765}
766
767static void ag71xx_tx_timeout(struct net_device *dev)
768{
769    struct ag71xx *ag = netdev_priv(dev);
770
771    if (netif_msg_tx_err(ag))
772        pr_info("%s: tx timeout\n", ag->dev->name);
773
774    schedule_work(&ag->restart_work);
775}
776
777static void ag71xx_restart_work_func(struct work_struct *work)
778{
779    struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
780
781    if (ag71xx_get_pdata(ag)->is_ar724x) {
782        ag->link = 0;
783        ag71xx_link_adjust(ag);
784        return;
785    }
786
787    ag71xx_stop(ag->dev);
788    ag71xx_open(ag->dev);
789}
790
791static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
792{
793    u32 rx_sm, tx_sm, rx_fd;
794
795    if (likely(time_before(jiffies, timestamp + HZ/10)))
796        return false;
797
798    if (!netif_carrier_ok(ag->dev))
799        return false;
800
801    rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
802    if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
803        return true;
804
805    tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
806    rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
807    if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
808        ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
809        return true;
810
811    return false;
812}
813
814static int ag71xx_tx_packets(struct ag71xx *ag)
815{
816    struct ag71xx_ring *ring = &ag->tx_ring;
817    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
818    int sent = 0;
819    int bytes_compl = 0;
820
821    DBG("%s: processing TX ring\n", ag->dev->name);
822
823    while (ring->dirty != ring->curr) {
824        unsigned int i = ring->dirty % ring->size;
825        struct ag71xx_desc *desc = ring->buf[i].desc;
826        struct sk_buff *skb = ring->buf[i].skb;
827
828        if (!ag71xx_desc_empty(desc)) {
829            if (pdata->is_ar7240 &&
830                ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
831                schedule_work(&ag->restart_work);
832            break;
833        }
834
835        ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
836
837        bytes_compl += skb->len;
838        ag->dev->stats.tx_bytes += skb->len;
839        ag->dev->stats.tx_packets++;
840
841        dev_kfree_skb_any(skb);
842        ring->buf[i].skb = NULL;
843
844        ring->dirty++;
845        sent++;
846    }
847
848    DBG("%s: %d packets sent out\n", ag->dev->name, sent);
849
850    netdev_completed_queue(ag->dev, sent, bytes_compl);
851    if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
852        netif_wake_queue(ag->dev);
853
854    return sent;
855}
856
857static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
858{
859    struct net_device *dev = ag->dev;
860    struct ag71xx_ring *ring = &ag->rx_ring;
861    int offset = ag71xx_buffer_offset(ag);
862    int done = 0;
863
864    DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
865            dev->name, limit, ring->curr, ring->dirty);
866
867    while (done < limit) {
868        unsigned int i = ring->curr % ring->size;
869        struct ag71xx_desc *desc = ring->buf[i].desc;
870        struct sk_buff *skb;
871        int pktlen;
872        int err = 0;
873
874        if (ag71xx_desc_empty(desc))
875            break;
876
877        if ((ring->dirty + ring->size) == ring->curr) {
878            ag71xx_assert(0);
879            break;
880        }
881
882        ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
883
884        pktlen = ag71xx_desc_pktlen(desc);
885        pktlen -= ETH_FCS_LEN;
886
887        dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
888                 AG71XX_RX_BUF_SIZE, DMA_FROM_DEVICE);
889
890        dev->last_rx = jiffies;
891        dev->stats.rx_packets++;
892        dev->stats.rx_bytes += pktlen;
893
894        skb = build_skb(ring->buf[i].rx_buf);
895        if (!skb) {
896            kfree(ring->buf[i].rx_buf);
897            goto next;
898        }
899
900        skb_reserve(skb, offset);
901        skb_put(skb, pktlen);
902
903        if (ag71xx_has_ar8216(ag))
904            err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
905
906        if (err) {
907            dev->stats.rx_dropped++;
908            kfree_skb(skb);
909        } else {
910            skb->dev = dev;
911            skb->ip_summed = CHECKSUM_NONE;
912            skb->protocol = eth_type_trans(skb, dev);
913            netif_receive_skb(skb);
914        }
915
916next:
917        ring->buf[i].rx_buf = NULL;
918        done++;
919
920        ring->curr++;
921    }
922
923    ag71xx_ring_rx_refill(ag);
924
925    DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
926        dev->name, ring->curr, ring->dirty, done);
927
928    return done;
929}
930
931static int ag71xx_poll(struct napi_struct *napi, int limit)
932{
933    struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
934    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
935    struct net_device *dev = ag->dev;
936    struct ag71xx_ring *rx_ring;
937    unsigned long flags;
938    u32 status;
939    int tx_done;
940    int rx_done;
941
942    pdata->ddr_flush();
943    tx_done = ag71xx_tx_packets(ag);
944
945    DBG("%s: processing RX ring\n", dev->name);
946    rx_done = ag71xx_rx_packets(ag, limit);
947
948    ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
949
950    rx_ring = &ag->rx_ring;
951    if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
952        goto oom;
953
954    status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
955    if (unlikely(status & RX_STATUS_OF)) {
956        ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
957        dev->stats.rx_fifo_errors++;
958
959        /* restart RX */
960        ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
961    }
962
963    if (rx_done < limit) {
964        if (status & RX_STATUS_PR)
965            goto more;
966
967        status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
968        if (status & TX_STATUS_PS)
969            goto more;
970
971        DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
972            dev->name, rx_done, tx_done, limit);
973
974        napi_complete(napi);
975
976        /* enable interrupts */
977        spin_lock_irqsave(&ag->lock, flags);
978        ag71xx_int_enable(ag, AG71XX_INT_POLL);
979        spin_unlock_irqrestore(&ag->lock, flags);
980        return rx_done;
981    }
982
983more:
984    DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
985            dev->name, rx_done, tx_done, limit);
986    return rx_done;
987
988oom:
989    if (netif_msg_rx_err(ag))
990        pr_info("%s: out of memory\n", dev->name);
991
992    mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
993    napi_complete(napi);
994    return 0;
995}
996
997static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
998{
999    struct net_device *dev = dev_id;
1000    struct ag71xx *ag = netdev_priv(dev);
1001    u32 status;
1002
1003    status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1004    ag71xx_dump_intr(ag, "raw", status);
1005
1006    if (unlikely(!status))
1007        return IRQ_NONE;
1008
1009    if (unlikely(status & AG71XX_INT_ERR)) {
1010        if (status & AG71XX_INT_TX_BE) {
1011            ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1012            dev_err(&dev->dev, "TX BUS error\n");
1013        }
1014        if (status & AG71XX_INT_RX_BE) {
1015            ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1016            dev_err(&dev->dev, "RX BUS error\n");
1017        }
1018    }
1019
1020    if (likely(status & AG71XX_INT_POLL)) {
1021        ag71xx_int_disable(ag, AG71XX_INT_POLL);
1022        DBG("%s: enable polling mode\n", dev->name);
1023        napi_schedule(&ag->napi);
1024    }
1025
1026    ag71xx_debugfs_update_int_stats(ag, status);
1027
1028    return IRQ_HANDLED;
1029}
1030
1031#ifdef CONFIG_NET_POLL_CONTROLLER
1032/*
1033 * Polling 'interrupt' - used by things like netconsole to send skbs
1034 * without having to re-enable interrupts. It's not called while
1035 * the interrupt routine is executing.
1036 */
1037static void ag71xx_netpoll(struct net_device *dev)
1038{
1039    disable_irq(dev->irq);
1040    ag71xx_interrupt(dev->irq, dev);
1041    enable_irq(dev->irq);
1042}
1043#endif
1044
1045static const struct net_device_ops ag71xx_netdev_ops = {
1046    .ndo_open = ag71xx_open,
1047    .ndo_stop = ag71xx_stop,
1048    .ndo_start_xmit = ag71xx_hard_start_xmit,
1049    .ndo_do_ioctl = ag71xx_do_ioctl,
1050    .ndo_tx_timeout = ag71xx_tx_timeout,
1051    .ndo_change_mtu = eth_change_mtu,
1052    .ndo_set_mac_address = eth_mac_addr,
1053    .ndo_validate_addr = eth_validate_addr,
1054#ifdef CONFIG_NET_POLL_CONTROLLER
1055    .ndo_poll_controller = ag71xx_netpoll,
1056#endif
1057};
1058
1059static int __devinit ag71xx_probe(struct platform_device *pdev)
1060{
1061    struct net_device *dev;
1062    struct resource *res;
1063    struct ag71xx *ag;
1064    struct ag71xx_platform_data *pdata;
1065    int err;
1066
1067    pdata = pdev->dev.platform_data;
1068    if (!pdata) {
1069        dev_err(&pdev->dev, "no platform data specified\n");
1070        err = -ENXIO;
1071        goto err_out;
1072    }
1073
1074    if (pdata->mii_bus_dev == NULL) {
1075        dev_err(&pdev->dev, "no MII bus device specified\n");
1076        err = -EINVAL;
1077        goto err_out;
1078    }
1079
1080    dev = alloc_etherdev(sizeof(*ag));
1081    if (!dev) {
1082        dev_err(&pdev->dev, "alloc_etherdev failed\n");
1083        err = -ENOMEM;
1084        goto err_out;
1085    }
1086
1087    SET_NETDEV_DEV(dev, &pdev->dev);
1088
1089    ag = netdev_priv(dev);
1090    ag->pdev = pdev;
1091    ag->dev = dev;
1092    ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1093                    AG71XX_DEFAULT_MSG_ENABLE);
1094    spin_lock_init(&ag->lock);
1095
1096    res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1097    if (!res) {
1098        dev_err(&pdev->dev, "no mac_base resource found\n");
1099        err = -ENXIO;
1100        goto err_out;
1101    }
1102
1103    ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1104    if (!ag->mac_base) {
1105        dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1106        err = -ENOMEM;
1107        goto err_free_dev;
1108    }
1109
1110    dev->irq = platform_get_irq(pdev, 0);
1111    err = request_irq(dev->irq, ag71xx_interrupt,
1112              IRQF_DISABLED,
1113              dev->name, dev);
1114    if (err) {
1115        dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1116        goto err_unmap_base;
1117    }
1118
1119    dev->base_addr = (unsigned long)ag->mac_base;
1120    dev->netdev_ops = &ag71xx_netdev_ops;
1121    dev->ethtool_ops = &ag71xx_ethtool_ops;
1122
1123    INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1124
1125    init_timer(&ag->oom_timer);
1126    ag->oom_timer.data = (unsigned long) dev;
1127    ag->oom_timer.function = ag71xx_oom_timer_handler;
1128
1129    ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1130    ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1131
1132    ag->stop_desc = dma_alloc_coherent(NULL,
1133        sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1134
1135    if (!ag->stop_desc)
1136        goto err_free_irq;
1137
1138    ag->stop_desc->data = 0;
1139    ag->stop_desc->ctrl = 0;
1140    ag->stop_desc->next = (u32) ag->stop_desc_dma;
1141
1142    memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1143
1144    netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1145
1146    err = register_netdev(dev);
1147    if (err) {
1148        dev_err(&pdev->dev, "unable to register net device\n");
1149        goto err_free_desc;
1150    }
1151
1152    pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1153        dev->name, dev->base_addr, dev->irq);
1154
1155    ag71xx_dump_regs(ag);
1156
1157    ag71xx_hw_init(ag);
1158
1159    ag71xx_dump_regs(ag);
1160
1161    err = ag71xx_phy_connect(ag);
1162    if (err)
1163        goto err_unregister_netdev;
1164
1165    err = ag71xx_debugfs_init(ag);
1166    if (err)
1167        goto err_phy_disconnect;
1168
1169    platform_set_drvdata(pdev, dev);
1170
1171    return 0;
1172
1173err_phy_disconnect:
1174    ag71xx_phy_disconnect(ag);
1175err_unregister_netdev:
1176    unregister_netdev(dev);
1177err_free_desc:
1178    dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1179              ag->stop_desc_dma);
1180err_free_irq:
1181    free_irq(dev->irq, dev);
1182err_unmap_base:
1183    iounmap(ag->mac_base);
1184err_free_dev:
1185    kfree(dev);
1186err_out:
1187    platform_set_drvdata(pdev, NULL);
1188    return err;
1189}
1190
1191static int __devexit ag71xx_remove(struct platform_device *pdev)
1192{
1193    struct net_device *dev = platform_get_drvdata(pdev);
1194
1195    if (dev) {
1196        struct ag71xx *ag = netdev_priv(dev);
1197
1198        ag71xx_debugfs_exit(ag);
1199        ag71xx_phy_disconnect(ag);
1200        unregister_netdev(dev);
1201        free_irq(dev->irq, dev);
1202        iounmap(ag->mac_base);
1203        kfree(dev);
1204        platform_set_drvdata(pdev, NULL);
1205    }
1206
1207    return 0;
1208}
1209
1210static struct platform_driver ag71xx_driver = {
1211    .probe = ag71xx_probe,
1212    .remove = __exit_p(ag71xx_remove),
1213    .driver = {
1214        .name = AG71XX_DRV_NAME,
1215    }
1216};
1217
1218static int __init ag71xx_module_init(void)
1219{
1220    int ret;
1221
1222    ret = ag71xx_debugfs_root_init();
1223    if (ret)
1224        goto err_out;
1225
1226    ret = ag71xx_mdio_driver_init();
1227    if (ret)
1228        goto err_debugfs_exit;
1229
1230    ret = platform_driver_register(&ag71xx_driver);
1231    if (ret)
1232        goto err_mdio_exit;
1233
1234    return 0;
1235
1236err_mdio_exit:
1237    ag71xx_mdio_driver_exit();
1238err_debugfs_exit:
1239    ag71xx_debugfs_root_exit();
1240err_out:
1241    return ret;
1242}
1243
1244static void __exit ag71xx_module_exit(void)
1245{
1246    platform_driver_unregister(&ag71xx_driver);
1247    ag71xx_mdio_driver_exit();
1248    ag71xx_debugfs_root_exit();
1249}
1250
1251module_init(ag71xx_module_init);
1252module_exit(ag71xx_module_exit);
1253
1254MODULE_VERSION(AG71XX_DRV_VERSION);
1255MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1256MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1257MODULE_LICENSE("GPL v2");
1258MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
1259

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