Root/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-a-wrong-IRQ-number.patch

1From d710990df726cceffb62488e597ecfc4a9e13aa5 Mon Sep 17 00:00:00 2001
2From: Gabor Juhos <juhosg@openwrt.org>
3Date: Wed, 14 Mar 2012 10:36:06 +0100
4Subject: [PATCH 15/47] MIPS: ath79: fix a wrong IRQ number
5
6The Ubiquiti XM board setup code uses an invalid
7IRQ number, because it if above of NR_IRQS. This
8leads to failed 'request_irq' calls:
9
10  ath9k 0000:00:00.0: request_irq failed
11  ath9k: probe of 0000:00:00.0 failed with error -22
12
13Preserve some IRQ numbers for the built-in IRQ
14controller of PCI host controllers in the
15AR71XX/AR724X SoCs, and use the correct IRQ
16number in the board setup code.
17
18Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
19Cc: linux-mips@linux-mips.org
20Patchwork: https://patchwork.linux-mips.org/patch/3495/
21Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
22---
23 arch/mips/ath79/mach-ubnt-xm.c | 5 +++--
24 arch/mips/include/asm/mach-ath79/irq.h | 6 +++++-
25 2 files changed, 8 insertions(+), 3 deletions(-)
26
27--- a/arch/mips/ath79/mach-ubnt-xm.c
28+++ b/arch/mips/ath79/mach-ubnt-xm.c
29@@ -17,6 +17,8 @@
30 #include <linux/ath9k_platform.h>
31 #endif /* CONFIG_PCI */
32 
33+#include <asm/mach-ath79/irq.h>
34+
35 #include "machtypes.h"
36 #include "dev-gpio-buttons.h"
37 #include "dev-leds-gpio.h"
38@@ -33,7 +35,6 @@
39 #define UBNT_XM_KEYS_POLL_INTERVAL 20
40 #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
41 
42-#define UBNT_XM_PCI_IRQ 48
43 #define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
44 
45 static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
46@@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x
47 
48 static struct ar724x_pci_data ubnt_xm_pci_data[] = {
49     {
50- .irq = UBNT_XM_PCI_IRQ,
51+ .irq = ATH79_PCI_IRQ(0),
52         .pdata = &ubnt_xm_eeprom_data,
53     },
54 };
55--- a/arch/mips/include/asm/mach-ath79/irq.h
56+++ b/arch/mips/include/asm/mach-ath79/irq.h
57@@ -10,11 +10,15 @@
58 #define __ASM_MACH_ATH79_IRQ_H
59 
60 #define MIPS_CPU_IRQ_BASE 0
61-#define NR_IRQS 40
62+#define NR_IRQS 46
63 
64 #define ATH79_MISC_IRQ_BASE 8
65 #define ATH79_MISC_IRQ_COUNT 32
66 
67+#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
68+#define ATH79_PCI_IRQ_COUNT 6
69+#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
70+
71 #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
72 #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
73 #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
74

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