| 1 | From fd1dd2f2c317bc0fc2c30fba440d911654bf592e Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Wed, 14 Mar 2012 10:36:11 +0100 |
| 4 | Subject: [PATCH 20/47] MIPS: ath79: allow to use SoC specific PCI IRQ maps |
| 5 | |
| 6 | The PCI controllers in the AR71XX and in the |
| 7 | AR724X SoCs are different, and both of them |
| 8 | uses different IRQ wiring. |
| 9 | |
| 10 | The patch modifies the 'pcibios_map_irq' function |
| 11 | in order to allow to use different IRQ maps for |
| 12 | the different SoCs. The patch also adds a function, |
| 13 | which lets the board setup code to override the |
| 14 | default IRQ map. |
| 15 | |
| 16 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 17 | Cc: linux-mips@linux-mips.org |
| 18 | Patchwork: https://patchwork.linux-mips.org/patch/3500/ |
| 19 | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
| 20 | --- |
| 21 | arch/mips/ath79/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++--- |
| 22 | arch/mips/ath79/pci.h | 9 ++++++ |
| 23 | 2 files changed, 77 insertions(+), 4 deletions(-) |
| 24 | |
| 25 | --- a/arch/mips/ath79/pci.c |
| 26 | +++ b/arch/mips/ath79/pci.c |
| 27 | @@ -8,6 +8,7 @@ |
| 28 | * by the Free Software Foundation. |
| 29 | */ |
| 30 | |
| 31 | +#include <linux/init.h> |
| 32 | #include <linux/pci.h> |
| 33 | #include <asm/mach-ath79/ath79.h> |
| 34 | #include <asm/mach-ath79/irq.h> |
| 35 | @@ -15,9 +16,35 @@ |
| 36 | #include "pci.h" |
| 37 | |
| 38 | static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); |
| 39 | +static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; |
| 40 | +static unsigned ath79_pci_nr_irqs __initdata; |
| 41 | static struct ar724x_pci_data *pci_data; |
| 42 | static int pci_data_size; |
| 43 | |
| 44 | +static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { |
| 45 | + { |
| 46 | + .slot = 17, |
| 47 | + .pin = 1, |
| 48 | + .irq = ATH79_PCI_IRQ(0), |
| 49 | + }, { |
| 50 | + .slot = 18, |
| 51 | + .pin = 1, |
| 52 | + .irq = ATH79_PCI_IRQ(1), |
| 53 | + }, { |
| 54 | + .slot = 19, |
| 55 | + .pin = 1, |
| 56 | + .irq = ATH79_PCI_IRQ(2), |
| 57 | + } |
| 58 | +}; |
| 59 | + |
| 60 | +static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { |
| 61 | + { |
| 62 | + .slot = 0, |
| 63 | + .pin = 1, |
| 64 | + .irq = ATH79_PCI_IRQ(0), |
| 65 | + } |
| 66 | +}; |
| 67 | + |
| 68 | void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) |
| 69 | { |
| 70 | pci_data = data; |
| 71 | @@ -26,13 +53,40 @@ void ar724x_pci_add_data(struct ar724x_p |
| 72 | |
| 73 | int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) |
| 74 | { |
| 75 | - unsigned int devfn = dev->devfn; |
| 76 | int irq = -1; |
| 77 | + int i; |
| 78 | |
| 79 | - if (devfn > pci_data_size - 1) |
| 80 | - return irq; |
| 81 | - |
| 82 | - irq = pci_data[devfn].irq; |
| 83 | + if (ath79_pci_nr_irqs == 0 || |
| 84 | + ath79_pci_irq_map == NULL) { |
| 85 | + if (soc_is_ar71xx()) { |
| 86 | + ath79_pci_irq_map = ar71xx_pci_irq_map; |
| 87 | + ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); |
| 88 | + } else if (soc_is_ar724x()) { |
| 89 | + ath79_pci_irq_map = ar724x_pci_irq_map; |
| 90 | + ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); |
| 91 | + } else { |
| 92 | + pr_crit("pci %s: invalid irq map\n", |
| 93 | + pci_name((struct pci_dev *) dev)); |
| 94 | + return irq; |
| 95 | + } |
| 96 | + } |
| 97 | + |
| 98 | + for (i = 0; i < ath79_pci_nr_irqs; i++) { |
| 99 | + const struct ath79_pci_irq *entry; |
| 100 | + |
| 101 | + entry = &ath79_pci_irq_map[i]; |
| 102 | + if (entry->slot == slot && entry->pin == pin) { |
| 103 | + irq = entry->irq; |
| 104 | + break; |
| 105 | + } |
| 106 | + } |
| 107 | + |
| 108 | + if (irq < 0) |
| 109 | + pr_crit("pci %s: no irq found for pin %u\n", |
| 110 | + pci_name((struct pci_dev *) dev), pin); |
| 111 | + else |
| 112 | + pr_info("pci %s: using irq %d for pin %u\n", |
| 113 | + pci_name((struct pci_dev *) dev), irq, pin); |
| 114 | |
| 115 | return irq; |
| 116 | } |
| 117 | @@ -45,6 +99,13 @@ int pcibios_plat_dev_init(struct pci_dev |
| 118 | return 0; |
| 119 | } |
| 120 | |
| 121 | +void __init ath79_pci_set_irq_map(unsigned nr_irqs, |
| 122 | + const struct ath79_pci_irq *map) |
| 123 | +{ |
| 124 | + ath79_pci_nr_irqs = nr_irqs; |
| 125 | + ath79_pci_irq_map = map; |
| 126 | +} |
| 127 | + |
| 128 | void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) |
| 129 | { |
| 130 | ath79_pci_plat_dev_init = func; |
| 131 | @@ -52,6 +113,9 @@ void __init ath79_pci_set_plat_dev_init( |
| 132 | |
| 133 | int __init ath79_register_pci(void) |
| 134 | { |
| 135 | + if (soc_is_ar71xx()) |
| 136 | + return ar71xx_pcibios_init(); |
| 137 | + |
| 138 | if (soc_is_ar724x()) |
| 139 | return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); |
| 140 | |
| 141 | --- a/arch/mips/ath79/pci.h |
| 142 | +++ b/arch/mips/ath79/pci.h |
| 143 | @@ -15,13 +15,22 @@ struct ar724x_pci_data { |
| 144 | int irq; |
| 145 | }; |
| 146 | |
| 147 | +struct ath79_pci_irq { |
| 148 | + u8 slot; |
| 149 | + u8 pin; |
| 150 | + int irq; |
| 151 | +}; |
| 152 | + |
| 153 | void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); |
| 154 | |
| 155 | #ifdef CONFIG_PCI |
| 156 | +void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); |
| 157 | void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); |
| 158 | int ath79_register_pci(void); |
| 159 | #else |
| 160 | static inline void |
| 161 | +ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {} |
| 162 | +static inline void |
| 163 | ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} |
| 164 | static inline int ath79_register_pci(void) { return 0; } |
| 165 | #endif |
| 166 | |
