Root/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch

1From e9706fc0a97feb7992a98806b69a1fc1fcb910c7 Mon Sep 17 00:00:00 2001
2From: Gabor Juhos <juhosg@openwrt.org>
3Date: Wed, 14 Mar 2012 10:45:22 +0100
4Subject: [PATCH 27/47] MIPS: ath79: add clock initialization code for AR934X
5
6Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
8Cc: linux-mips@linux-mips.org
9Cc: mcgrof@infradead.org
10Patchwork: https://patchwork.linux-mips.org/patch/3507/
11Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
12---
13 arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++
14 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++
15 2 files changed, 134 insertions(+), 0 deletions(-)
16
17--- a/arch/mips/ath79/clock.c
18+++ b/arch/mips/ath79/clock.c
19@@ -1,8 +1,11 @@
20 /*
21  * Atheros AR71XX/AR724X/AR913X common routines
22  *
23+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
24  * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
25  *
26+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
27+ *
28  * This program is free software; you can redistribute it and/or modify it
29  * under the terms of the GNU General Public License version 2 as published
30  * by the Free Software Foundation.
31@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo
32     ath79_uart_clk.rate = ath79_ref_clk.rate;
33 }
34 
35+static void __init ar934x_clocks_init(void)
36+{
37+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
38+ u32 cpu_pll, ddr_pll;
39+ u32 bootstrap;
40+
41+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
42+ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
43+ ath79_ref_clk.rate = 40 * 1000 * 1000;
44+ else
45+ ath79_ref_clk.rate = 25 * 1000 * 1000;
46+
47+ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
48+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
49+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
50+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
51+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
52+ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
53+ AR934X_PLL_CPU_CONFIG_NINT_MASK;
54+ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
55+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
56+
57+ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
58+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
59+ cpu_pll /= (1 << out_div);
60+
61+ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
62+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
63+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
64+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
65+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
66+ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
67+ AR934X_PLL_DDR_CONFIG_NINT_MASK;
68+ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
69+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
70+
71+ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
72+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
73+ ddr_pll /= (1 << out_div);
74+
75+ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
76+
77+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
78+ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
79+
80+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
81+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
82+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
83+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
84+ else
85+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
86+
87+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
88+ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
89+
90+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
91+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
92+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
93+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
94+ else
95+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
96+
97+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
98+ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
99+
100+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
101+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
102+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
103+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
104+ else
105+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
106+
107+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
108+ ath79_uart_clk.rate = ath79_ref_clk.rate;
109+}
110+
111 void __init ath79_clocks_init(void)
112 {
113     if (soc_is_ar71xx())
114@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void)
115         ar913x_clocks_init();
116     else if (soc_is_ar933x())
117         ar933x_clocks_init();
118+ else if (soc_is_ar934x())
119+ ar934x_clocks_init();
120     else
121         BUG();
122 
123--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
124+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
125@@ -151,6 +151,41 @@
126 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
127 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
128 
129+#define AR934X_PLL_CPU_CONFIG_REG 0x00
130+#define AR934X_PLL_DDR_CONFIG_REG 0x04
131+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
132+
133+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
134+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
135+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
136+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
137+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
138+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
139+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
140+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
141+
142+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
143+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
144+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
145+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
146+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
147+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
148+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
149+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
150+
151+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
152+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
153+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
154+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
155+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
156+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
157+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
158+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
159+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
160+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
161+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
162+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
163+
164 /*
165  * USB_CONFIG block
166  */
167@@ -186,6 +221,8 @@
168 #define AR933X_RESET_REG_RESET_MODULE 0x1c
169 #define AR933X_RESET_REG_BOOTSTRAP 0xac
170 
171+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
172+
173 #define MISC_INT_ETHSW BIT(12)
174 #define MISC_INT_TIMER4 BIT(10)
175 #define MISC_INT_TIMER3 BIT(9)
176@@ -242,6 +279,22 @@
177 
178 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
179 
180+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
181+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
182+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
183+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
184+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
185+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
186+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
187+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
188+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
189+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
190+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
191+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
192+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
193+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
194+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
195+
196 #define REV_ID_MAJOR_MASK 0xfff0
197 #define REV_ID_MAJOR_AR71XX 0x00a0
198 #define REV_ID_MAJOR_AR913X 0x00b0
199

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