| 1 | From 902b348cdddd4c858993e02aced615aa6caf04d0 Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Wed, 14 Mar 2012 10:45:30 +0100 |
| 4 | Subject: [PATCH 35/47] MIPS: ath79: add PCI registration code for AR934X |
| 5 | |
| 6 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 7 | Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> |
| 8 | Cc: linux-mips@linux-mips.org |
| 9 | Cc: mcgrof@infradead.org |
| 10 | Patchwork: https://patchwork.linux-mips.org/patch/3516/ |
| 11 | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
| 12 | --- |
| 13 | arch/mips/ath79/Kconfig | 2 ++ |
| 14 | arch/mips/ath79/pci.c | 13 ++++++++++++- |
| 15 | 2 files changed, 14 insertions(+), 1 deletions(-) |
| 16 | |
| 17 | --- a/arch/mips/ath79/Kconfig |
| 18 | +++ b/arch/mips/ath79/Kconfig |
| 19 | @@ -72,6 +72,8 @@ config SOC_AR933X |
| 20 | |
| 21 | config SOC_AR934X |
| 22 | select USB_ARCH_HAS_EHCI |
| 23 | + select HW_HAS_PCI |
| 24 | + select PCI_AR724X if PCI |
| 25 | def_bool n |
| 26 | |
| 27 | config PCI_AR724X |
| 28 | --- a/arch/mips/ath79/pci.c |
| 29 | +++ b/arch/mips/ath79/pci.c |
| 30 | @@ -14,6 +14,7 @@ |
| 31 | |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/pci.h> |
| 34 | +#include <asm/mach-ath79/ar71xx_regs.h> |
| 35 | #include <asm/mach-ath79/ath79.h> |
| 36 | #include <asm/mach-ath79/irq.h> |
| 37 | #include <asm/mach-ath79/pci.h> |
| 38 | @@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct |
| 39 | if (soc_is_ar71xx()) { |
| 40 | ath79_pci_irq_map = ar71xx_pci_irq_map; |
| 41 | ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); |
| 42 | - } else if (soc_is_ar724x()) { |
| 43 | + } else if (soc_is_ar724x() || |
| 44 | + soc_is_ar9342() || |
| 45 | + soc_is_ar9344()) { |
| 46 | ath79_pci_irq_map = ar724x_pci_irq_map; |
| 47 | ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); |
| 48 | } else { |
| 49 | @@ -115,5 +118,13 @@ int __init ath79_register_pci(void) |
| 50 | if (soc_is_ar724x()) |
| 51 | return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); |
| 52 | |
| 53 | + if (soc_is_ar9342() || soc_is_ar9344()) { |
| 54 | + u32 bootstrap; |
| 55 | + |
| 56 | + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); |
| 57 | + if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) |
| 58 | + return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); |
| 59 | + } |
| 60 | + |
| 61 | return -ENODEV; |
| 62 | } |
| 63 | |
